Modeling design and_performance_analysis_of_various_8_bit_adders_for_embedded_applications_kunjan d shinde

Modeling, Design and Performance Analysis of Various
8-bit Adders for Embedded Applications
Kunjan D. Shinde1 and Jayashree C. Nidagundi2
1PG Student, 2Assistant Professor,
Department of E&CE, S.D.M. College of Engineering and Technology, Dharwad 580 002, India.
e-mail: kunjan18m@gmail.com
Abstract. High speed and low power adder circuits are highly demanded in Embedded and VLSI design.
In this paper, a new approach for high speed and low power adder design, with less number of gate counts,
optimization of Area, Power and Delay is proposed, The proposed work presents the design, simulation and
implementation of various 8-bit adders on Cadence Design Suite 6.1.5 with Virtuoso, Assura and ADE toolset,
the designs are implemented in GPDK 45 nm technology with unvaried Width and Length of PMOS and NMOS
device, In this paper the Design and Modelling of Ripple Carry Adder, Carry Skip Adder, Carry Lookahead
Adder and Kogge Stone Adder is done using different design styles like CMOS, GDI and GDI-PTL logic is
applied and comparative analysis is made. From the simulation results it is clear that Parallel Preﬁx Adder (KSA)
provide a better result compared to other adder design, the proposed KSA adder is modelled and designed using
the combination of CMOS-GDI logic to give better performance.
Keywords: Ripple carry adder (RCA), Carry skip adder (CSA), Carry look ahead adder (CLA),
Kogge adder (KSA), Gate count/number of transistors, Power, Delay, Power delay product (PDP).
1. Introduction
Adders are fundamental and most essential blocks in every digital system, Design of effective and reliable adders
plays a important role, As the technology is scaled down the complexity in the design increases with some reduction
is the performance of the adders, In this paper a different set of adders like Ripple Carry Adder (RCA), Carry Skip
Adder (CSA), Carry Lookahead Adder (CLA) and Kogge Stone Adder (KSA) are designed using in Cadence Design
Suite 6.1.5 at GPDK 45 nm technology using CMOS, GDI and CMOS-GDI logic and the comparative analysis of the
adders are tabulated.
A simple adder performs the addition of given two numbers and the result is sum of those two numbers. Adders
can be implemented in different ways using different technologies, Design of reliable and high speed adders is the
prime objective and requirement for embedded applications as the technology is scaled down. Binary addition is a
fundamental operation in most of digital circuits. There are a variety of adders used to perform binary addition, each
has certain performance tradeoffs and drawbacks and hence the adders are selected based on where the adder is to be
used and for which applications.
The rest of the sections in this paper are arranged as, Section 2 gives the literature survey of various adder designs,
here the adders are designed and implemented on different toolsets for VLSI front-end and back-end design, Section 3
gives the methodology to design various adders like RCA, CSA, CLA and KSA, Section 4 gives the simulation results
and performance analysis of the various adders, followed by conclusion and references sections.
2. Literature Survey
Design and modelling of adders for embedded applications is a critical task to perform, the following are the few
references that we have gone through that has helped us in the design of adders for the same, from references [1] the
design of RCA and CLA adders is obtained, it briefs on the working and implementation of the same [2]. Gives the
design of RCA, CSA and CLA adder blocks at the backend VLSI approach [3] and [4]. Gives the detailed explanation
© Elsevier Publications 2014. 823

Kunjan D. Shinde and Jayashree C. Nidagundi
of various adders and KSA adder design methodologies [5]. Give a brief working of design and implementation
of 8-bit KSA adder using Cadence tool [6–8] and [9]. Gives a design and implementation of various adders using
different toolset for both front end and back end VLSI design [10]. Gives the design and implementation of KSA
adder using PTL logic. [11] and [12] gives the design of 1-bit full adder using various area, power and delay optimised
techniques [13]. Gives the comparative analysis of high performance of full adders [15]. Gives the graphical method
to design of KSA adder [14] and [16]. Gives a brief on the design and modelling of various adders.
3. Design of Various 8-bit Adders
3.1 Ripple carry adder
The design of a simple n-bit adder circuit can be achieved with a combinational circuit that adds two bits along with
the carry in bit are called as full adder. The ripple carry adder is constructed by cascading full adder blocks in series,
figure 1 and 2 shows the block diagram and gate level schematic of 1-bit full adder. To obtain the 8-bit Ripple Carry
Adder it requires 8 stages of 1-bit full adders, the carryout of one stage is fed directly to the carry-in of the next stage
which is shown in figure 3. For an n-bit parallel adder, it requires n full adder.
Drawbacks of ripple carry adder
• Not very efficient when large bit numbers are used and Delay increases linearly with the bit length.
Equation of ripple carry adder
Si = Ai XOR Bi XOR Ci-1 (1)
Ci+1 = (Ai AND Bi) OR (Bi AND Ci) OR (Ci AND Ai) (2)
The worst case of delay might happen when the inputs at 1st stage are at logic ‘1’ and any one of the input is at logic ‘1’
an at this time the carry in is also at logic ‘1’, at this state the carryout is generated and if the rest of Ai or Bi are at
logic ‘1’ then the carry propagation is carried out till the last stage and the delay introduced in generating proper result
Figure 1. Block diagram of 1-bit full adder. Figure 2. Schematic of 1-bit full adder.
Table 1. Comparative analysis of various 1-bit full adders.
Figure 3. Block diagram of Ripple carry adder.
824 © Elsevier Publications 2014.

Modeling, Design and Performance Analysis of Various 8-bit Adders
is equal to delay required to generate last stage carryout which is quite large and hence it the largest carry propagation
path that can occur in the RCA.
Figure 11 shows the schematic and the simulation results of the 8-bit RCA, the inputs to the adder are Cin = ‘1’,
Ai=[00000001] and Bi=[11111111] giving the worst case delay as mentioned earlier. As the design of 1-bit full
adder plays a very important role in RCA and hence table 1 is used for the selection of 1-bit full adder, table 1
gives the comparative analysis of full adder design using various design styles mentioned, the CMOS and GDI-PTL
is considered in this paper. Table 2 and 3 gives the comparative analysis of various adders in which RCA adder
comparison can be observed in the column 1 gives the worst case delay for RCA designed with CMOS and GDI-PTL
full adder.
3.2 Carry skip adder (CSA)
The design of a carry-skip adder is based on the classical definition propagate signals as given in equation 3, the CSA
can be designed with different block size using the RCA as the building block, where the size of the block determines
the numbers of carry stages to be considered and minimizing the carry propagation path. Figure 4 shows the general
block diagram of an 8-bit CSA, the CSA can be designed with the block size 2 and block size 4 as shown in the figure 5
and 6 respectively. The carry skip network for the CSA can be obtained from equation 6 and the final sum out from
the equation 4.
Pi = Ai XOR Bi (3)
Si = Pi XOR Ci (4)
Ci+1 = (Ai AND Bi) OR (Pi AND Ci) (5)
Cout = C present OR (Pi:j AND C previous) (6)
where Pi is the propagate signal, Gi is Generate signal and Ai and Bi are the input operands to the ith adder cell, Ci
is the carry input to the ith cell, Pi:j are the partial sum terms of the ith block with j number of sum terms given by
equation 3.
Figure 4 shows the block diagram of 8-bit Carry Skip Adder, the design of carry skip network depends on the block
size, figure 5 and 6 shows the schematic 8-bit CSA with block size 2 and block size 4 respectively, figure 12 and 13
schematic simulation of CSA with block size 2 and 4 respectively, the inputs to the adder are Cin = ‘1’, Ai=[00000001]
and Bi=[11111111], this gives rise for the worst case consideration of the delay and a better approach to compare the
results with other adders, table 2 and 3 gives the performance analysis of CSA with block size 2 and 4 using CMOS
and Optimized Full adder with CMOS and GDI Carry generation stages.
Figure 4. Block diagram of carry Skip adder. Figure 5. Block diagram of CSA with block size 2.
Figure 6. Block diagram of CSA with block size 4.

Figure 7. Processing stages of carry lookahead adder. Figure 8. Block diagram of carry lookahead adder.
It is stated and proved that CSA provides better results in generating carryout signal when compared with RCA,
where as the area occupied is larger than that of RCA [table 2 and 3].
3.3 Carry lookahead adder (CLA)
The carry lookahead adder (CLA) solves the carry delay problem by calculating the carry signals in advance based on
the input signals. It is based on the fact that a carry signal will be generated in two cases:
1. When both bits Ai and Bi are at logic ‘1’.
2. When one of the two bits Ai and Bi is at logic ‘1’ and the carry-in is at logic ‘1’.
Equations of carry lookahead adder
Pi = Ai OR Bi (7)
Gi = Ai AND Bi (8)
Xi = Ai XOR Bi (9)
Si = Xi XOR Ci (10)
Ci+1 = Gi OR (Pi AND Ci) (11)
where Pi is propagate Signal and Gi is generate signal and Si is the final sum output. The carry out of ith adder is
obtained by equation (2) and the same can be modified to obtain the carry network which is shown in equation (10),
for a given ith state Ci is calculated depending on initial Ai and Bi signals.
Figure 8 shows the block diagram of the 8-bit CLA, figure 14 shows the schematic and simulation result of 8-bit
CLA, the inputs to the adder are Cin = ‘1’, Ai=[00000001] and Bi=[11111111], this gives rise for the worst case
consideration of the delay and a better approach to compare the results with other adders, Table 2 and 3 gives the
performance analysis of CLA with CMOS and GDI logics, it is clear from the table that CLA adder gives better
performance than CSA and RCA.
3.4 Kogge stone adder (KSA)
KSA is a parallel prefix form carry lookahead adder, it generates carry in O (logn) time and is widely considered as
the fastest adder and is widely used in the industry for high performance arithmetic circuits [3]. In KSA, carries are
computed fast by computing them in parallel at the cost of increased area. The complete functioning of KSA can be
easily comprehended by analyzing it in terms of three distinct parts as explained below.
1. Pre Processing: This step involves computation of generate and propagate signals corresponding too each pair of
bits in A and B. These signals are given by the logic equations below:
Pi = Ai XOR Bi (12)
Gi = Ai AND Bi (13)

Figure 9. Parallel prefix adder stages. Figure 10. Schematic of 8-bit Kogge stone adder.
2. Carry Lookahead Network: This block differentiates KSA from other adders and is the main force behind its high
performance. This step involves computation of carries corresponding to each bit. It uses Black Cell and Gray
Cell for the design of carry generate network and the cells are arranged according prefix tree of KSA, the cells
output act as intermediate signals which are given by the logic equations below:
A. Black Cell: The black cell takes two pairs of generate and propagate signals (Gi, Pi) and (Gj, Pj) as input
and computes a pair of generate and propagate signals (G, P) as output
G = Gi OR (Pi AND Pj) (14)
P = Pi AND Pj (15)
B. Grey Cell: The gray cell takes two pairs of generate and propagate signals (Gi, Pi) and (Gj, Pj) as inputs and
computes a generate signal G as output
G = Gi OR (Pi AND Pj) (16)
3. Post Processing: This is the final step and is common to all adders of this family (carry look ahead). It involves
computation of sum bits. Sum bits are computed by the logic given below:
Si = Pi XOR Ci-1 (17)
As mentioned earlier the Kogge Stone Adder is a parallel prefix form of Carry Look ahead Adder and the figure 9
shows the processing stages of Carry Look ahead network of KSA and its equation for implementing the same.
Figure and figure shows the schematic and simulation result of 8-bit KSA, the inputs to the adder are Cin = ‘1’,
Ai=[00000001] and Bi=[11111111], this gives rise for the worst case consideration of the delay and a better approach
to compare the results with other adders, table 2 and 3 gives the performance analysis of KSA with CMOS and GDI
logics, it is clear that the KSA adder gives better performance than CLA,CSA and RCA in terms of delay and power
with a increased in number of gate count.
4. Results and Discussions
4.1 Simulation results
The following are the schematic and simulation results of various 8-bit adders used in this paper, modelled and design
of adders are done using CMOS, GDI and CMOS-GDI logics. The adders are designed on Cadence Design Suite 6.1.5
at GPDK 45 nm technology with unvaried Width and Length of all the PMOS and NMOS devices.
The schematics of various 8-bit adders like RCA, CSA with block size 2 and block size 4, CLA and KSA is shown
below which are designed as explained earlier, figures shown below are the schematics of adders designed using
CMOS logic and the blocks of adders remain same for GDI logic also but the internal logic is GDI in case of KSA,
CLA and CSA with block size 2 and block size 4 (only carry skip network), for RCA we have designed 1-bit full
adder using different design styles and coated the comparative analysis of 1-bit full adder in table 1 and hence from
the comparative result we have selected the CMOS logic and GDI-PTL logic for the implementation of 1-bit full
adder.

Figure 11. Schematic and simulation results of 8-bit RCA.
Figure 12. Schematic and simulation results of 8-bit CSA with block size 2.
Figure 13. Schematic and simulation results of 8-bit CSA with block size 4.
Figure 14. Schematic and simulation results of 8-bit CLA.

Figure 15. Schematic and simulation results of 8-bit KSA.
Table 2. Comparative analysis of 8bit various adders designed using CMOS logic.
Table 3. Comparative analysis of 8-bit various adders designed using GDI logic.
4.2 Performance analysis
The section below gives the performance analysis of various 8-bit adders like RCA, CSA, CLA and KSA with Delay,
Power, Power Delay product (PDP) and Number of transistors/ gate count as the performance measures. The measure
of performance is carried out on Cadence Design Suite using Virtuoso and ADE environment at GPDK45 nanometer
technology.
The table 2 shows comparative analysis of various 8-bit adders modeled and designed using CMOS logic as
performance measures as Number of transistors/gate count, worst case delay and power consumption, from the table it
is clear that KSA adder provides a better results in terms of Delay and Power, where as the gate count is large enough
compared to other adders.
The table 3 gives comparative analysis of various 8-bit adders modeled and designed using optimized and GDI logic
with performance measures as Number of transistors/ gate count, worst case delay and power consumption, from the
table it is clear that KSA adder provides a better results in terms of gate count, where as the power and delay is bit

Table 4. Comparative analysis of 8-bit KSA adder designed using different logic.
Table 5. Comparative analysis of 8-bit KSA adders with performance measure as power delay
product (PDP).
more compared to other adders. The CLA adder is designed using both CMOS and GDI logic here, as the number of
gate levels is increased in carry generate stage which increases the voltage drop from the GDI cell due to which the
output voltage gets degraded, and hence to have proper results at the ﬁnal stage the CMOS gate are used in the logic
path were the degradation of the results is observed due to which the gate count is larger in the CLA design using GDI
logic but the gate count is less compared to CMOS CLA adder design.
The table 4 gives the comparative analysis of various 8-bit KSA adders modeled and designed using CMOS, GDI
and combination of CMOS-GDI logic with performance measures as Number of transistors/gate count, worst case
delay and power consumption, from the table it is clear that KSA adder using CMOS-GDI type-2(CMOS logic only
at ﬁnal carryout stage and other stages with GDI, GDI-PTL logic) logic adder gives a best results in terms of Delay,
Power and Gate count/Number of Transistors, hence the proposed design is best in all the performance measures hence
this design can be chosen for embedded application without compromising in any of the performance measure.
The table 5 shows comparative analysis of various 8-bit adders modelled and designed using CMOS, GDI and
combination of CMOS-GDI logic with performance measures as Power Delay Product (PDP), from the table 5 it is
clear that the design of KSA adder using CMOS-GDI type-1 and KSA CMOS-GDI type-2 logic adder gives best
results in terms of PDP.
5. Conclusion
The KSA adder design gives least worst case delay compared to CLA, CSA and RCA adder design using conventional
and optimal design techniques. The proposed design of KSA adder which is modeled using both conventional and

optimal logic to give the best performance in terms of gate count, worst case delay, power consumption and PDP.
Table 4 and 5 gives the comparative analysis of the same & hence the designed KSA adder gives the best and optimal
results overall.
References
[1] Donald D. Givone, “Digital Principles and Design”, Tata McGraw-Hill Edition, chapter 5, pp. 231–240, (2002).
[2] Douglas A. Pucknell and Kamran Eshraghian, “Basic VLSI Design”, third edition, chapter 8, pp. 192–220.
[3] http://en.wikipedia.org/wiki/Kogge%E2%80%93Stone−adder.
[4] http://en.wikipedia.org/wiki/Adder−(electronics).
[5] Anurag Sindhu and Ashish Bhatia, “8-bit Kogge Stone Adder”, Course project.
[6] R. Kathiresan, M. Thangavel, K .Rathinakumar and S. Maragadharaj, “Analysis of Different Bit Carry Look Ahead Adder
Using Verilog Code”, International Journal of Electronics and Communication Engineering & Technology (IJECET),
ISSN 0976–6464(Print), ISSN 0976–6472(Online), IAEME, vol. 4, issue 4, July–August (2013).
[7] Lakshmi Phani and Deepthi Bollepalli, “Design and Implementation of Fault Tolerant Adders on Field Programmable Gate
Arrays”, A thesis report, The University of Texas at Tyler, May (2012).
[8] Mr. Pakkiraiah Chakali and Mr. Madhu Kumar Patnala, “Design of High Speed Kogge-Stone Based Carry Select Adder”,
International Journal of Emerging Science and Engineering (IJESE) ISSN: 2319–6378, vol. 1, issue 4, February (2013).
[9] Ms. Madhu Thakur and Prof. Javed Ashraf, “Design of Braun Multiplier with Kogge Stone Adder & It’s Implementation on
FPGA”, International Journal of Scientiﬁc & Engineering Research, 1 ISSN 2229-5518 vol. 3, issue 10, October (2012).
[10] Adilakshmi Siliveru and M. Bharathi, “Design of Kogge-Stone and Brent-Kung adders using Degenerate Pass Transistor
Logic”, International Journal of Emerging Science and Engineering (IJESE) ISSN: 2319–6378, vol. 1, issue 4,
February (2013).
[11] Saradindu Panda, A. Banerjee, B. Maji and Dr. A. K. Mukhopadhyay, “Power and Delay Comparison in between Different
Types of Full Adder circuits”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation
Engineering, ISSN 2278–8875, vol. 1, issue 3, September (2012).
[12] Rajkumar Sarma and Veerati Raju “Design and Performance Analysis of Hybrid Adders for High Speed Arithmetic Circuit”,
International Journal of VLSI design & Communication Systems (VLSICS), vol. 3, no. 3, June (2012).
[13] Tripti Sharma, K. G. Sharma and Prof. B. P. Singh, “High Performance Full Adder Cell: A Comparative Analysis”,
Proceedings of the 2010 IEEE Student’s Technology Symposium, IIT Kharagpur, 3–4 April (2010).
[14] http://www.goddard.net.nz/ﬁles/js/ksaddergen/ksaddergen.html.
[15] http://www.minecraftforum.net/topic/394747-4-bit-kogge-stone-adder/.
[16] http://venividiwiki.ee.virginia.edu/mediawiki/index.php/Group−name:−NAND.

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