This document discusses the modeling, design, and performance analysis of various 8-bit adders for embedded applications. It summarizes the design and implementation of Ripple Carry Adder (RCA), Carry Skip Adder (CSA), Carry Lookahead Adder (CLA), and Kogge Stone Adder (KSA) using CMOS, GDI, and CMOS-GDI logic in Cadence Design Suite at 45 nm technology. Simulation results show that the Parallel Prefix Adder (KSA) provides better performance compared to other adders. The proposed KSA adder is modeled using a combination of CMOS-GDI logic to improve performance further.
This document compares the performance of five 8-bit adders: Ripple Carry Adder, Carry Skip Adder, Carry Lookahead Adder, and Kogge Stone Adder. It analyzes the design and working of each adder and evaluates them based on delay and area. The results show that the Kogge Stone Adder provides the least delay but uses more area than the other adders. In summary, this paper presents a comparative study of different 8-bit adder circuits to determine the most efficient design for embedded applications.
This document proposes an efficient higher order and high speed carry select adder (CSLA) using a Kogge-Stone parallel prefix adder and common Boolean logic. It aims to reduce the delay and area of CSLAs by replacing ripple carry adders with faster Kogge-Stone adders. Simulation results show the proposed CSLA achieves a 3-46% reduction in delay and 5-21% reduction in area compared to regular and modified CSLAs for word sizes ranging from 16 to 128 bits.
VLSI Implementation of 32-Bit Unsigned Multiplier Using CSLA & CLAAIJMTST Journal
In this project we are going to compare the performance of different adders implemented to the multipliers based on area and time needed for calculation. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31 % by the CSLA based multiplier to complete the multiplication operation.
High performance parallel prefix adders with fast carry chain logiciaemedu
This document discusses and compares different types of parallel prefix adders. It begins by introducing binary adders and describing the three stages of prefix addition: pre-computation, prefix-computation, and post-computation. It then describes various parallel prefix adders like Brent-Kung, Kogge-Stone, Ladner-Fischer, and Han-Carlson adders. For FPGA implementation, simple adders typically perform better than parallel prefix adders due to fast carry chains. The document proposes modifying the Kogge-Stone adder using fast carry logic to make it more suitable for FPGAs. Simulation results show that for higher bit widths, the modified Kogge-Stone adder provides better delay than a simple ad
Designing of Adders and Vedic Multiplier using Gate Diffusion InputIRJET Journal
This document discusses the design of adders and Vedic multipliers using Gate Diffusion Input (GDI) logic. GDI logic is introduced as an alternative to traditional CMOS logic for low power VLSI design. Various adders including Ripple Carry Adder, Kogge Stone Adder, and Brent Kung Adder are designed using GDI logic. Vedic multipliers are also designed using the Urdhva-Tiryagbhyam multiplication technique along with the GDI-based adders. Comparative analysis shows that designs using GDI logic have lower power consumption, transistor count, and area compared to equivalent CMOS designs.
HARDWARE EFFICIENT SCALING FREE VECTORING AND ROTATIONAL CORDIC FOR DSP APPLI...VLSICS Design
1) The document presents a new scaling free CORDIC algorithm for vectoring and rotational modes that requires no pre or post processing. It uses a third order Taylor approximation of sine and cosine functions.
2) The algorithm was implemented on a FPGA using Verilog. Results showed it was fully scaling free, with low power consumption of 0.06mW and delays of 4.123ns and 9.925ns for rotational and vectoring modes respectively.
3) Mathematical verification confirmed the accuracy of 12-16 bits, within expected error bounds for a 16-bit implementation. The proposed algorithm offers improved efficiency over conventional CORDIC.
FPGA Implementation of Pipelined CORDIC Sine Cosine Digital Wave Generator cscpconf
The coordinate rotation digital computer (CORDIC) algorithm is well known iterative
algorithm for performing rotations in digital signal processing applications. Hardware
implementation of CORDIC results increase in Critical path delay. Pipelined architecture isused in CORDIC to increase the clock speed and to reduce the Critical path delay. In this paper a hardware efficient Digital sine and cosine wave generator is designed and implemented using Pipelined CORDIC architecture. FPGA based architecture is presented and design has been implemented using Xilinx 12.3 device
Design of High Speed 128 bit Parallel Prefix AddersIJERA Editor
In this paper, we propose 128-bit Kogge-Stone, Ladner-Fischer, Spanning tree parallel prefix adders and
compared with Ripple carry adder. In general N-bit adders like Ripple Carry Adders (slow adders compare to
other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most
Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix
adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor
while performing addition. While when we want to design any 128-bit operating systems and processors we can
use these adders in place of regular adders. We simulate and synthesis different types of 128-bit prefix adders
using Xilinx ISE 12.3 tool. By using these synthesis results, we noted the performance parameters like number
of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values.
This document compares the performance of five 8-bit adders: Ripple Carry Adder, Carry Skip Adder, Carry Lookahead Adder, and Kogge Stone Adder. It analyzes the design and working of each adder and evaluates them based on delay and area. The results show that the Kogge Stone Adder provides the least delay but uses more area than the other adders. In summary, this paper presents a comparative study of different 8-bit adder circuits to determine the most efficient design for embedded applications.
This document proposes an efficient higher order and high speed carry select adder (CSLA) using a Kogge-Stone parallel prefix adder and common Boolean logic. It aims to reduce the delay and area of CSLAs by replacing ripple carry adders with faster Kogge-Stone adders. Simulation results show the proposed CSLA achieves a 3-46% reduction in delay and 5-21% reduction in area compared to regular and modified CSLAs for word sizes ranging from 16 to 128 bits.
VLSI Implementation of 32-Bit Unsigned Multiplier Using CSLA & CLAAIJMTST Journal
In this project we are going to compare the performance of different adders implemented to the multipliers based on area and time needed for calculation. The CLAA based multiplier uses the delay time of 99ns for performing multiplication operation where as in CSLA based multiplier also uses nearly the same delay time for multiplication operation. But the area needed for CLAA multiplier is reduced to 31 % by the CSLA based multiplier to complete the multiplication operation.
High performance parallel prefix adders with fast carry chain logiciaemedu
This document discusses and compares different types of parallel prefix adders. It begins by introducing binary adders and describing the three stages of prefix addition: pre-computation, prefix-computation, and post-computation. It then describes various parallel prefix adders like Brent-Kung, Kogge-Stone, Ladner-Fischer, and Han-Carlson adders. For FPGA implementation, simple adders typically perform better than parallel prefix adders due to fast carry chains. The document proposes modifying the Kogge-Stone adder using fast carry logic to make it more suitable for FPGAs. Simulation results show that for higher bit widths, the modified Kogge-Stone adder provides better delay than a simple ad
Designing of Adders and Vedic Multiplier using Gate Diffusion InputIRJET Journal
This document discusses the design of adders and Vedic multipliers using Gate Diffusion Input (GDI) logic. GDI logic is introduced as an alternative to traditional CMOS logic for low power VLSI design. Various adders including Ripple Carry Adder, Kogge Stone Adder, and Brent Kung Adder are designed using GDI logic. Vedic multipliers are also designed using the Urdhva-Tiryagbhyam multiplication technique along with the GDI-based adders. Comparative analysis shows that designs using GDI logic have lower power consumption, transistor count, and area compared to equivalent CMOS designs.
HARDWARE EFFICIENT SCALING FREE VECTORING AND ROTATIONAL CORDIC FOR DSP APPLI...VLSICS Design
1) The document presents a new scaling free CORDIC algorithm for vectoring and rotational modes that requires no pre or post processing. It uses a third order Taylor approximation of sine and cosine functions.
2) The algorithm was implemented on a FPGA using Verilog. Results showed it was fully scaling free, with low power consumption of 0.06mW and delays of 4.123ns and 9.925ns for rotational and vectoring modes respectively.
3) Mathematical verification confirmed the accuracy of 12-16 bits, within expected error bounds for a 16-bit implementation. The proposed algorithm offers improved efficiency over conventional CORDIC.
FPGA Implementation of Pipelined CORDIC Sine Cosine Digital Wave Generator cscpconf
The coordinate rotation digital computer (CORDIC) algorithm is well known iterative
algorithm for performing rotations in digital signal processing applications. Hardware
implementation of CORDIC results increase in Critical path delay. Pipelined architecture isused in CORDIC to increase the clock speed and to reduce the Critical path delay. In this paper a hardware efficient Digital sine and cosine wave generator is designed and implemented using Pipelined CORDIC architecture. FPGA based architecture is presented and design has been implemented using Xilinx 12.3 device
Design of High Speed 128 bit Parallel Prefix AddersIJERA Editor
In this paper, we propose 128-bit Kogge-Stone, Ladner-Fischer, Spanning tree parallel prefix adders and
compared with Ripple carry adder. In general N-bit adders like Ripple Carry Adders (slow adders compare to
other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most
Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix
adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor
while performing addition. While when we want to design any 128-bit operating systems and processors we can
use these adders in place of regular adders. We simulate and synthesis different types of 128-bit prefix adders
using Xilinx ISE 12.3 tool. By using these synthesis results, we noted the performance parameters like number
of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values.
Implementation of Low Power and Area-Efficient Carry Select AdderIJMTST Journal
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform
fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area
and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to
significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-,-b square-root
CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA
architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA
with only a slight increase in the delay. This work evaluates the performance of the proposed designs in
terms of delay, area, power, and their products by hand with logical effort and through custom design and
layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is
better than the regular SQRT CSLA.
Design of 32 bit Parallel Prefix Adders IOSR Journals
In this paper, we propose 32 bit Kogge-Stone, Brent-Kung, Ladner-Fischer parallel prefix adders. In
general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead
adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix
adders because of their advantages compare to other adders. Parallel prefix adders are faster and area
efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing
addition. We simulate and synthesis different types of 32-bit prefix adders using Xilinx ISE 10.1i tool. By using
these synthesis results, we noted the performance parameters like number of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values.
Implementation and Comparison of Efficient 16-Bit SQRT CSLA Using Parity Pres...IJERA Editor
In Very Large Scale Integration (VLSI) outlines, Carry Select Adder (CSLA) is one of the quickest adder utilized as a part of numerous data processing processors to perform quick number crunching capacities. In this paper we proposed the design of SQRT CSLA using parity preserving reversible gate (P2RG). Reversible logic is emerging field in today VLSI design. In conventional circuits, the logic gates such as AND gate, OR gate is irreversible in nature and computing with irreversible logic results in energy dissipation. This problem can be circumvented by using reversible logic. In ideal condition, the reversible logic gate produces zero power dissipation. The proposed design is efficient in terms of delay as compare to irreversible SQRT CSLA. The simulation is done using Xilinx.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document describes a novel design for a 32-bit unsigned multiplier using a modified carry select adder (MCSLA). It begins with background on adders and multipliers in VLSI design. It then describes the conventional carry select adder (CSLA) and proposes a modified CSLA (MCSLA) that uses common boolean logic to reduce area and power. The document presents the design and VHDL simulation results of a 32-bit unsigned multiplier using both CSLA and the proposed MCSLA. The results show the MCSLA based multiplier achieves a 45% reduction in power-area-delay product compared to the CSLA based multiplier.
High Speed and Area Efficient Booth Multiplier Using SQRT CSLA with Zero Find...IJERA Editor
Addition is one of the common and widely used fundamental arithmetic operation in many VLSI systems. The critical elements in general purpose and digital-signal processing processors are High performance VLSI integer adders as they are employed in the design of Arithmetic-Logic Units, in floating-point arithmetic data paths and in address generation units. The performance parameters for any adder are area, speed and delay. By using Square Root Carry Select Adder (SQRT CSLA), speed can be achieved. In designing new architecture, the Tradeoff between those parameters plays the major role. We can reduce area by using Zero Finding Logic (ZFC) technique, from the structure of SQRT CSLA. By using the Modified architecture we can reduce area. We can implement Booth multiplier by using the CSLA and SQRT CSLA with Zero finding logic. Implementation of Booth multiplier by using CSLA and SQRT CSLA with Zero finding logic is proposed for better speed applications and efficient area applications.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document compares the design and implementation of 32-bit unsigned integer multipliers using carry look-ahead adders (CLAA) and carry select adders (CSLA). It finds that a CSLA-based multiplier has 31% less area than a CLAA-based multiplier, while both achieve nearly the same delay time of 99ns. VHDL models are developed and simulated for both multipliers. Analysis shows the CSLA design has better area efficiency with comparable speed performance.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Area, Delay and Power Comparison of Adder TopologiesVLSICS Design
This document compares the area, delay, and power characteristics of different adder topologies, including ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder, and carry bypass adder. It analyzes the functionality and performance of 8-bit implementations of each adder type using Microwind simulation software at a 0.12μm CMOS technology node. The ripple carry adder has the simplest design but the longest propagation delay that scales with the number of bits, while other topologies like the carry look-ahead adder and carry skip adder reduce delay but have more complex circuitry. The document aims to
In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier
Performance Study of BCH Error Correcting Codes Using the Bit Error Rate Term...IJERA Editor
The quality of a digital transmission is mainly dependent on the amount of errors introduced into the transmission channel. The codes BCH (Bose-Chaudhuri-Hocquenghem) are widely used in communication systems and storage systems. In this paper a Performance study of BCH error correcting codes is proposed. This paper presents a comparative study of performance between the Bose-Chaudhuri-Hocquenghem codes BCH (15, 7, 2) and BCH (255, 231, 3) using the bit error rate term (BER). The channel and the modulation type are respectively AWGN and PSK where the order of modulation is equal to 2. First, we generated and simulated the error correcting codes BCH (15, 7, 2) and BCH (255, 231, 3) using Math lab simulator. Second, we compare the two codes using the bit error rate term (BER), finally we conclude the coding gain for a BER = 10-4.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IRJET- A Review of Approximate Adders for Energy-Efficient Digital Signal Pro...IRJET Journal
The document reviews recent progress in approximate adders for energy-efficient digital signal processing. It summarizes various types of approximate adders that have been proposed, including speculative adders, segmented adders, carry select adders, and adders using approximate full adders. The document provides details on the design and operation of several specific approximate adder circuits. It also compares the delay and area complexity of different approximate adder designs.
IRJET - A Speculative Approximate Adder for Error Recovery UnitIRJET Journal
This document presents a speculative approximate adder for error recovery. The adder is partitioned into non-overlapping blocks whose carries are predicted based on input signals of the current and next blocks. This reduces the critical path delay on average to one block. An error recovery unit is also proposed to further reduce output error rates. Simulation results show the proposed adder achieves lower error rates and error metrics compared to state-of-the-art approximate adders, with only a small increase in delay and area due to the error recovery unit.
This document proposes a modified design for a 64-bit carry select adder (CSLA) to reduce area and power consumption. A regular CSLA uses two ripple carry adders (RCA) per group, one with a carry input of 0 and one with a carry input of 1. The modified design replaces the RCA with a carry input of 1 with a binary to excess-1 converter (BEC) in each group. Simulation results show the modified 64-bit CSLA reduces area and power compared to the regular CSLA, with only a slight increase in delay. The BEC performs the addition similarly to the RCA it replaces, using less area than a second RCA. This improvement
Modification on Energy Efficient Design of DVB-T2 Constellation De-mapperIJERA Editor
The second generation of terrestrial digital video broadcasting standard (DVB-T2) offers several advantages for greater efficiency. Signal Space Diversity (SSD) contains rotated constellation and Q-Delay (RQD), which is one of advantage that offered to improve the performance over fading channels compared to the non-rotated modulation. In this journal, the proposed low-power de-mapper design of this work attempts to employ the introduced SSD to reduce power through replacing LLR calculations by a significantly less complex projection-based de-mapping whenever possible. It benefits from an algorithm that applies projection-based de-mapping to significantly reduce LLR computations without deteriorating performance. Two versions are introduced for hard de-mapping and soft de-mapping. The design uses several techniques simultaneously to be even more energy efficient without affecting the performance. Prototype results indicate significant reduction of LLR calculations as Eb/N0 increases with no performance degradation. The idea and energy saving techniques can be easily applied to any rotated constellation de-mapper.
1) The document describes the modular design of adders using domino logic. It focuses on a 4-bit slice carry look-ahead adder implemented using domino CMOS logic in TSMC 180nm technology.
2) Multiple 4-bit slices can be connected in a ripple carry fashion to create higher-order adders like 8, 16, 32 bits etc. A 64-bit adder is designed using 16 slices with a latency of 33 clocks and 1504 transistors.
3) The 4-bit slice uses carry look-ahead equations for sum, generate, and propagate blocks implemented with domino logic circuits. Simulation results show the adder architecture achieves an average power of 4.
This document discusses categorizing and standardizing levels of risk from human error in order to develop safety management policies. It aims to assess, classify and set standards for human error risk and criticality levels based on error rates, error consequences and criticality indexes. The methodology is demonstrated using data from underground coal mines in India. Human errors are analyzed and categorized into risk levels using clustering techniques. Standards are then set to guide risk and safety management policies based on the risk-criticality analysis. The goal is to identify target areas and interventions to reduce risks from human errors.
This document presents a comparative analysis of different designs for a 1-bit full adder circuit. It describes full adder designs using CMOS, TG, GDI, 9T GDI-PTL, and GDI-PTL logic. The designs are simulated in Cadence at 45nm technology with uniform transistor widths and lengths. Simulation results show that the GDI-PTL design has the lowest power delay product, making it well-suited for low-power applications. It provides satisfactory output levels with no conflicting voltage levels, using fewer transistors than CMOS or TG designs. The CMOS and TG designs have undistorted outputs but use more transistors, while the GDI and 9T designs use fewer transistors
High speed and low power adder circuits are highly demanded in Embedded and VLSI design.
In this paper, a new approach for high speed and low power adder design, with less number of gate counts,
optimization of Area, Power and Delay is proposed, The proposed work presents the design, simulation and
implementation of various 8-bit adders on Cadence Design Suite 6.1.5 with Virtuoso, Assura and ADE toolset,
the designs are implemented in GPDK 45 nm technology with unvaried Width and Length of PMOS and NMOS
device, In this paper the Design and Modelling of Ripple Carry Adder, Carry Skip Adder, Carry Lookahead
Adder and Kogge Stone Adder is done using different design styles like CMOS, GDI and GDI-PTL logic is
applied and comparative analysis ismade. From the simulation results it is clear that Parallel Prefix Adder (KSA)
provide a better result compared to other adder design, the proposed KSA adder is modelled and designed using
the combination of CMOS-GDI logic to give better performance.
Implementation of Low Power and Area-Efficient Carry Select AdderIJMTST Journal
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform
fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area
and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to
significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-,-b square-root
CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA
architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA
with only a slight increase in the delay. This work evaluates the performance of the proposed designs in
terms of delay, area, power, and their products by hand with logical effort and through custom design and
layout in 0.18-m CMOS process technology. The results analysis shows that the proposed CSLA structure is
better than the regular SQRT CSLA.
Design of 32 bit Parallel Prefix Adders IOSR Journals
In this paper, we propose 32 bit Kogge-Stone, Brent-Kung, Ladner-Fischer parallel prefix adders. In
general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead
adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix
adders because of their advantages compare to other adders. Parallel prefix adders are faster and area
efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing
addition. We simulate and synthesis different types of 32-bit prefix adders using Xilinx ISE 10.1i tool. By using
these synthesis results, we noted the performance parameters like number of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values.
Implementation and Comparison of Efficient 16-Bit SQRT CSLA Using Parity Pres...IJERA Editor
In Very Large Scale Integration (VLSI) outlines, Carry Select Adder (CSLA) is one of the quickest adder utilized as a part of numerous data processing processors to perform quick number crunching capacities. In this paper we proposed the design of SQRT CSLA using parity preserving reversible gate (P2RG). Reversible logic is emerging field in today VLSI design. In conventional circuits, the logic gates such as AND gate, OR gate is irreversible in nature and computing with irreversible logic results in energy dissipation. This problem can be circumvented by using reversible logic. In ideal condition, the reversible logic gate produces zero power dissipation. The proposed design is efficient in terms of delay as compare to irreversible SQRT CSLA. The simulation is done using Xilinx.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document describes a novel design for a 32-bit unsigned multiplier using a modified carry select adder (MCSLA). It begins with background on adders and multipliers in VLSI design. It then describes the conventional carry select adder (CSLA) and proposes a modified CSLA (MCSLA) that uses common boolean logic to reduce area and power. The document presents the design and VHDL simulation results of a 32-bit unsigned multiplier using both CSLA and the proposed MCSLA. The results show the MCSLA based multiplier achieves a 45% reduction in power-area-delay product compared to the CSLA based multiplier.
High Speed and Area Efficient Booth Multiplier Using SQRT CSLA with Zero Find...IJERA Editor
Addition is one of the common and widely used fundamental arithmetic operation in many VLSI systems. The critical elements in general purpose and digital-signal processing processors are High performance VLSI integer adders as they are employed in the design of Arithmetic-Logic Units, in floating-point arithmetic data paths and in address generation units. The performance parameters for any adder are area, speed and delay. By using Square Root Carry Select Adder (SQRT CSLA), speed can be achieved. In designing new architecture, the Tradeoff between those parameters plays the major role. We can reduce area by using Zero Finding Logic (ZFC) technique, from the structure of SQRT CSLA. By using the Modified architecture we can reduce area. We can implement Booth multiplier by using the CSLA and SQRT CSLA with Zero finding logic. Implementation of Booth multiplier by using CSLA and SQRT CSLA with Zero finding logic is proposed for better speed applications and efficient area applications.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document compares the design and implementation of 32-bit unsigned integer multipliers using carry look-ahead adders (CLAA) and carry select adders (CSLA). It finds that a CSLA-based multiplier has 31% less area than a CLAA-based multiplier, while both achieve nearly the same delay time of 99ns. VHDL models are developed and simulated for both multipliers. Analysis shows the CSLA design has better area efficiency with comparable speed performance.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Area, Delay and Power Comparison of Adder TopologiesVLSICS Design
This document compares the area, delay, and power characteristics of different adder topologies, including ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder, and carry bypass adder. It analyzes the functionality and performance of 8-bit implementations of each adder type using Microwind simulation software at a 0.12μm CMOS technology node. The ripple carry adder has the simplest design but the longest propagation delay that scales with the number of bits, while other topologies like the carry look-ahead adder and carry skip adder reduce delay but have more complex circuitry. The document aims to
In this project 31 % area delay product reduction is possible with the use of the CSLA based 32 bit unsigned parallel multiplier than CLAA based 32 bit unsigned parallel multiplier
Performance Study of BCH Error Correcting Codes Using the Bit Error Rate Term...IJERA Editor
The quality of a digital transmission is mainly dependent on the amount of errors introduced into the transmission channel. The codes BCH (Bose-Chaudhuri-Hocquenghem) are widely used in communication systems and storage systems. In this paper a Performance study of BCH error correcting codes is proposed. This paper presents a comparative study of performance between the Bose-Chaudhuri-Hocquenghem codes BCH (15, 7, 2) and BCH (255, 231, 3) using the bit error rate term (BER). The channel and the modulation type are respectively AWGN and PSK where the order of modulation is equal to 2. First, we generated and simulated the error correcting codes BCH (15, 7, 2) and BCH (255, 231, 3) using Math lab simulator. Second, we compare the two codes using the bit error rate term (BER), finally we conclude the coding gain for a BER = 10-4.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IRJET- A Review of Approximate Adders for Energy-Efficient Digital Signal Pro...IRJET Journal
The document reviews recent progress in approximate adders for energy-efficient digital signal processing. It summarizes various types of approximate adders that have been proposed, including speculative adders, segmented adders, carry select adders, and adders using approximate full adders. The document provides details on the design and operation of several specific approximate adder circuits. It also compares the delay and area complexity of different approximate adder designs.
IRJET - A Speculative Approximate Adder for Error Recovery UnitIRJET Journal
This document presents a speculative approximate adder for error recovery. The adder is partitioned into non-overlapping blocks whose carries are predicted based on input signals of the current and next blocks. This reduces the critical path delay on average to one block. An error recovery unit is also proposed to further reduce output error rates. Simulation results show the proposed adder achieves lower error rates and error metrics compared to state-of-the-art approximate adders, with only a small increase in delay and area due to the error recovery unit.
This document proposes a modified design for a 64-bit carry select adder (CSLA) to reduce area and power consumption. A regular CSLA uses two ripple carry adders (RCA) per group, one with a carry input of 0 and one with a carry input of 1. The modified design replaces the RCA with a carry input of 1 with a binary to excess-1 converter (BEC) in each group. Simulation results show the modified 64-bit CSLA reduces area and power compared to the regular CSLA, with only a slight increase in delay. The BEC performs the addition similarly to the RCA it replaces, using less area than a second RCA. This improvement
Modification on Energy Efficient Design of DVB-T2 Constellation De-mapperIJERA Editor
The second generation of terrestrial digital video broadcasting standard (DVB-T2) offers several advantages for greater efficiency. Signal Space Diversity (SSD) contains rotated constellation and Q-Delay (RQD), which is one of advantage that offered to improve the performance over fading channels compared to the non-rotated modulation. In this journal, the proposed low-power de-mapper design of this work attempts to employ the introduced SSD to reduce power through replacing LLR calculations by a significantly less complex projection-based de-mapping whenever possible. It benefits from an algorithm that applies projection-based de-mapping to significantly reduce LLR computations without deteriorating performance. Two versions are introduced for hard de-mapping and soft de-mapping. The design uses several techniques simultaneously to be even more energy efficient without affecting the performance. Prototype results indicate significant reduction of LLR calculations as Eb/N0 increases with no performance degradation. The idea and energy saving techniques can be easily applied to any rotated constellation de-mapper.
1) The document describes the modular design of adders using domino logic. It focuses on a 4-bit slice carry look-ahead adder implemented using domino CMOS logic in TSMC 180nm technology.
2) Multiple 4-bit slices can be connected in a ripple carry fashion to create higher-order adders like 8, 16, 32 bits etc. A 64-bit adder is designed using 16 slices with a latency of 33 clocks and 1504 transistors.
3) The 4-bit slice uses carry look-ahead equations for sum, generate, and propagate blocks implemented with domino logic circuits. Simulation results show the adder architecture achieves an average power of 4.
This document discusses categorizing and standardizing levels of risk from human error in order to develop safety management policies. It aims to assess, classify and set standards for human error risk and criticality levels based on error rates, error consequences and criticality indexes. The methodology is demonstrated using data from underground coal mines in India. Human errors are analyzed and categorized into risk levels using clustering techniques. Standards are then set to guide risk and safety management policies based on the risk-criticality analysis. The goal is to identify target areas and interventions to reduce risks from human errors.
This document presents a comparative analysis of different designs for a 1-bit full adder circuit. It describes full adder designs using CMOS, TG, GDI, 9T GDI-PTL, and GDI-PTL logic. The designs are simulated in Cadence at 45nm technology with uniform transistor widths and lengths. Simulation results show that the GDI-PTL design has the lowest power delay product, making it well-suited for low-power applications. It provides satisfactory output levels with no conflicting voltage levels, using fewer transistors than CMOS or TG designs. The CMOS and TG designs have undistorted outputs but use more transistors, while the GDI and 9T designs use fewer transistors
High speed and low power adder circuits are highly demanded in Embedded and VLSI design.
In this paper, a new approach for high speed and low power adder design, with less number of gate counts,
optimization of Area, Power and Delay is proposed, The proposed work presents the design, simulation and
implementation of various 8-bit adders on Cadence Design Suite 6.1.5 with Virtuoso, Assura and ADE toolset,
the designs are implemented in GPDK 45 nm technology with unvaried Width and Length of PMOS and NMOS
device, In this paper the Design and Modelling of Ripple Carry Adder, Carry Skip Adder, Carry Lookahead
Adder and Kogge Stone Adder is done using different design styles like CMOS, GDI and GDI-PTL logic is
applied and comparative analysis ismade. From the simulation results it is clear that Parallel Prefix Adder (KSA)
provide a better result compared to other adder design, the proposed KSA adder is modelled and designed using
the combination of CMOS-GDI logic to give better performance.
This document summarizes an FPGA implementation of fast error correction for memories using Euclidean geometry low density parity check (EG-LDPC) codes and majority logic decoding. Key points:
- EG-LDPC codes and majority logic decoding provide simple and low-complexity error correction for memories.
- An encoder and parallel majority logic decoder for a (15,7,5) EG-LDPC code were implemented in Verilog on FPGA.
- The decoder uses a control logic that can detect if no errors are present after 3 cycles, stopping decoding early for improved performance.
The document discusses various data link control protocols including framing techniques, error control, and flow control. It describes fixed and variable size framing and several automatic repeat request (ARQ) protocols for reliable data transmission over noisy channels, including stop-and-wait ARQ, go-back-N ARQ, and selective repeat ARQ. It also covers HDLC as a bit-oriented protocol and discusses its frame format, error detection, and flow control.
1. The document discusses network models including the OSI model and TCP/IP protocol suite. It describes the seven layers of the OSI model and the functions of each layer.
2. It also discusses different types of networks used for data communication, including telephone networks, digital subscriber line (DSL), and cable TV networks. It provides details on the components and technologies used in these different network types.
3. The document focuses on explaining data communication networks and protocols, with examples and diagrams. It specifically examines the OSI model in detail along with examples of physical, logical, and port addressing.
The document summarizes key aspects of optical fiber communication including:
1) It describes the advantages of optical fiber communication over copper wire communication such as smaller size, lower transmission loss, higher bandwidth, and immunity to electromagnetic interference.
2) The basic components of an optical fiber are described including the core, cladding, buffer, and jacket. Total internal reflection is explained as the mechanism that guides light through the fiber.
3) Different types of optical fibers are discussed including plastic optical fiber, single-mode fiber, multimode step-index fiber, and multimode graded-index fiber.
IRJET- FPGA Implementation of High Speed and Low Power Speculative AdderIRJET Journal
This document presents a design for a high-speed and low-power speculative adder implemented using FPGA. It describes a carry lookahead adder based inexact speculative adder architecture that is further fine-grain pipelined to reduce delay and enhance operating frequency. Implementation of pipelining reduced the delay by up to 6ns compared to the non-pipelined architecture and reduced power by up to 4W. Synthesis and simulation results on FPGA show that the 32-bit pipelined architecture operates at 127.72MHz while consuming 17.634W, 4.235W less than the non-pipelined version. Pipelining and clock gating techniques help improve the speed and power efficiency of
DESIGN AND PERFORMANCE ANALYSIS OF BINARY ADDERS_editedShital Badaik
The document describes the design and performance analysis of various binary adders. It discusses the design of ripple carry adders of sizes 4-bit, 8-bit and 16-bit. The designs are implemented using Verilog HDL and simulated using Xilinx ISE simulator. The performance parameters like area and delay are determined and compared for different adder designs including carry look ahead adder, carry select adder, carry skip adder, carry increment adder and carry save adder.
Design and Estimation of delay, power and area for Parallel prefix addersIJERA Editor
The document describes a study comparing the delay, power, and area of different types of parallel prefix adders implemented on a Xilinx Spartan 6 FPGA, including Kogge Stone, Han Carlson, and Brent Kung adders. It discusses the structures and computation methods of parallel prefix adders and traditional ripple carry and carry lookahead adders. The adders were designed in Verilog HDL and synthesized on the FPGA, then their delay, power usage, and resource usage were measured and compared. Simulation results showing the logic diagrams and outputs of sample adders like the ripple carry and Kogge Stone adder are also presented.
Design and Implementation of Low-Power and Area-Efficient 64 bit CSLA using VHDLIJSRD
All processor consisting ALU and adder plays important role for design of ALU. Design of low area and power efficient adder helps to reduce power consumption and area of any processor. Now a day’s major area of research in VLSI system is design of area, high speed and low power data path logic systems. In digital adders, the speed of addition is restricted by the time necessary to send a carry signal through the adder. The area and power consumption is reduced by modifying regular CSLA architecture. The proposed architecture is developed with the help of a simple ripple carry adder (RCA) and gate-level architecture. It consists of single RCA which improves the performance of the proposed designs then the regular designs in terms of power consumption and area.
DESIGN AND IMPLEMENTATION OF AN IMPROVED CARRY INCREMENT ADDERVLSICS Design
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the
design of this basic adder unit. The speed of operation of a circuit is one of the important performance
criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many
research works have been devoted in improving the delay of the adder circuit. In this paper we have
proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The
improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the
previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for
comparative analysis. The coding is done in Verilog hardware description language (HDL) and the
simulation is carried out in Xilinx ISE 13.1 environment.
Design of 32 bit Parallel Prefix AddersIOSR Journals
Abstract: In this paper, we propose 32 bit Kogge-Stone, Brent-Kung, Ladner-Fischer parallel prefix adders. In general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 32-bit prefix adders using Xilinx ISE 10.1i tool. By using these synthesis results, we noted the performance parameters like number of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values. Keywords− prefix adder, carry operator, Kogge-Stone, Brent-Kung, Ladner-Fischer
Evaluation of High Speed and Low Memory Parallel Prefix AddersIOSR Journals
This document discusses and compares different types of parallel prefix adders, including the Kogge-Stone adder, sparse Kogge-Stone adder, and spanning tree adder. It analyzes the performance of these adders in terms of speed and resource usage. The Kogge-Stone adder is identified as one of the fastest adder designs possible, as it can generate carry signals in logarithmic time. However, it requires more logic levels than some other designs like the sparse Kogge-Stone adder.
128-Bit Area Efficient Reconfigurable Carry Select Adder ijcisjournal
Adders are one of the most critical arithmetic circuits in a system and their throughput affects the overall
performance of the system. Carry Select Adder (CSLA) is one of the fastest adders used in many dataprocessing
processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that
there is scope for reducing the area and power consumption in the CSLA. In this paper, we proposed an
area-efficient carry select adder by sharing the common Boolean logic term. After logic optimization and
sharing partial circuit, we only need one XOR gate and one inverter gate for sum generation. Through the
multiplexer, we can select the final-sum only and for carry selection we need only one AND gate and one
OR gate. Based on this modification 16-, 32-, 64-, and 128-bit CSLA architecture have been developed and
compared with the conventional CSLA architecture. The proposed design greatly reduces the area
compared to other CSLAs. From this improvement, the gate count of a 128-bit carry select adder can be
reduced from 3320 to 1664. The proposed structure is implemented in Artix-7 FPGA. Compared with the
proposed design, the conventional CSLA has 65.80% less area.
DESIGN AND IMPLEMENTATION OF AN IMPROVED CARRY INCREMENT ADDERVLSICS Design
A complex digital circuit comprises of adder as a basic unit. The performance of the circuit depends on the design of this basic adder unit. The speed of operation of a circuit is one of the important performance criteria of many digital circuits which ultimately depends on the delay of the basic adder unit. Many research works have been devoted in improving the delay of the adder circuit. In this paper we have
proposed an improved carry increment adder (CIA) that improves the delay performance of the circuit. The improvement is achieved by incorporating carry look adder (CLA) in the design of CIA contrary to the previous design of CIA that employs ripple carry adder (RCA). A simulation study is carried out for comparative analysis. The coding is done in Verilog hardware description language (HDL) and the simulation is carried out in Xilinx ISE 13.1 environment.
Design and implementation of Closed Loop Control of Three Phase Interleaved P...IJMTST Journal
A single-phase, three-level, single-stage power-factor corrected AC/DC converter operated under closed
loop manner is presented. That operates with a single controller to regulate the output voltage and the input
inductor act as a boost inductor to have a single stage power factor correction with good output response. The
paper deals with a new single stage three level ac-dc converter which performs both power factor correction
and voltage regulation in a single stage. The proposed converter has two separate controllers, one for power
factor correction and the other for regulating the output voltage. A comprehensive review of the existing single
stage topologies has been carried out. Then the operating principle, control scheme and the design of the new
converter are presented. The proposed converter is having an input power factor close to unity and better
voltage regulation compared to the conventional ac-dc converter topologies. Proposed topology is evaluated
through Matlab/Simulink platform and simulation results are conferred.
Area Delay Power Efficient and Implementation of Modified Square-Root Carry S...IJTET Journal
Abstract: In VLSI Technology, Carry Propagation Delay is the most important concern for the Adders. Adder is the most unavoidable component for the arithmetic performances. This paper is Modified Square Root-Carry Select Adder (SQRT-CSLA) design reduces the delay with 16 bit adder. Carry select adder have two units for Carry Generation (CG) and Carry Selection (CS). The modified SQRT-CSLA design can gives parallel path for carry propagation. So the overall adder delay has reduced. Modified design is obtained using Ripple Carry Adder (RCA) with Boolean Excess-1 Converter (BEC). BEC produces an output i.e., is an excess one result for given input bits. Then input bits and BEC output is given to multiplexer for carry selection. Use of BEC instead of dual RCA gives efficient carry propagation delay and it consumes the lower power and overall gates using in design is reduced with compared to carry select adder with dual RCA. The final sum is calculated using final sum generation.
Design and Implementation of Different types of Carry skip adderIRJET Journal
The document describes the design and implementation of different types of carry skip adders. It begins with an introduction to carry skip adders and their advantages over other adder types in terms of speed, area usage, and transistor count. It then reviews existing carry skip adder designs and their limitations. A new design called the Common Boolean Logic (CBL) carry skip adder is proposed that aims to reduce area and power consumption by eliminating redundant adder cells through shared logic. Simulation results show that an 8-bit CBL carry skip adder has 64.6% lower power and 18.7% smaller area than a conventional carry skip adder. In conclusion, the CBL carry skip adder achieves improved performance and efficiency.
Layout and Design Analysis of Carry Look Ahead Adder using 90nm Technology IJEEE
Addition is the fundamental operation in any digital system. The propagation time is more in addition due to large time required for the carry bits.A carry look ahead adder improves the speed by reducing the time required to solve carry bits. It is mostly used in electronics devices. An efficient implementation of two bit carry look ahead adder is proposed using fully automatic and semi-custom design steps. This paper is a comparison of complexity of automatic generated design against semi-custom design. A two bit CLA adder was designed in 90nm low power high speed technology. The performance of the CLA is measured by comparing the results in terms of power dissipation and area efficiency. Simulation results showed 56% gain in power and 28% in Area.
This document describes the design and analysis of a carry look ahead adder using a 90nm technology. It compares an automatically generated carry look ahead adder design to a semi-custom designed version. The semi-custom design reduced power consumption by 56% and area by 28% compared to the automatic design. The document outlines the basic concept of carry look ahead adders and describes building one using logic gates. It provides layouts and simulation results for both the automatic and semi-custom designs, showing the semi-custom approach performs better in terms of power and area.
This document describes the design and analysis of a carry look ahead adder using a 90nm technology. It compares an automatically generated carry look ahead adder design to a semi-custom designed version. The semi-custom design reduced power consumption by 56% and area by 28% compared to the automatic design. The document outlines the basic concept of carry look ahead adders and describes building one using logic gates. It provides layouts and simulation results for both the automatic and semi-custom designs, showing the semi-custom approach performs better in terms of power and area.
This document summarizes the delay and area analysis of a regular 16-bit square root carry select adder (SQRT CSLA) architecture and a proposed modified architecture. The regular design contains five groups of ripple carry adders of different sizes. The delay and area of each group is evaluated based on the delays of basic blocks like full adders and multiplexers. The proposed design aims to reduce area and power by replacing one ripple carry adder in each group with a binary to excess-1 converter, which requires fewer logic gates. Implementation results show the proposed design has lower area and power with a slight increase in delay compared to the regular SQRT CSLA architecture.
Highly -increasing requirement for mobile and several electronic devices want the use of VLSI circuits which are highly power efficient. The most primitive arithmetic operation in processors is addition and the adder is the most highly used arithmetic component of the processor. Carry Select Adder (CSA) is one of the fastest adders and the structure of the CSA shows that there is a possibility for increasing its efficiency by reducing the power dissipation and area in the CSA. This research paper presents power and delay analysis of various adders and proposed a 32-bit CSA that is implemented using variable size of the combination of adders, thus the proposed Carry select Adder (CSA) which has minimum Delay, and less power consumption hence improving the efficiency and speed of the Carry Select Adder.
Design and Verification of Area Efficient Carry Select Adderijsrd.com
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 16, 32 square - root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area.
— Parallel Prefix adders have been one of the most
notable among several designs proposed in the past. The
advantage of utilizing the flexibility in implementing these
structures based upon through put requirements. Due to
continuing integrating intensity and the growing needs of
portable devices, low power and high performance designs are of
prime importance. The classical parallel prefix adder structures
presented in the literature over the years optimize for logic depth,
area, and fan-out and interconnect count of logic circuits. In this
proposed system, Kogge-Stone adder which is one of types of
parallel prefix adder is used. Kogge stone is the fastest adder
because of its minimum fan-out. When parallel prefix adder is
compared with classical adders it is advantageous in every aspect.
The study reveals that Parallel Prefix adder has the least power
delay product when compared with its peer existing adder
structures (Ripple carry adder, Carry save adders etc).
Simulation results are verified using Xilinx 10.1 and
MODELSIM 6.4a softwares.
This document describes the design of a 32-bit parallel multiplier using VHDL. It compares the use of carry save adders (CSA) versus carry lookahead adders (CLA) in the partial product lines. CSA is used to add each group of partial products in parallel. Simulation waveforms are shown for half adders, full adders, and 4, 8, and 32-bit multipliers. Output is also shown on an FPGA for half and full adders. The conclusion is that using CSA in the partial product lines improves performance over other adders in terms of speed and efficiency for large multiplications.