IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Implementation of FPGA Based Image Processing Algorithm using Xilinx System G...IRJET Journal
This document describes the implementation of various image processing algorithms using the Xilinx System Generator integrated with the Matlab/Simulink environment. It discusses algorithms for converting an RGB image to grayscale, generating a negative image, enhancing contrast and brightness, thresholding, background subtraction, erosion, dilation, edge detection, and masking. The algorithms are modeled in Simulink using Xilinx System Generator blocks and hardware co-simulation is used to verify the results. The key steps involve image pre-processing to prepare input data, implementing the algorithm using Xilinx blocks, and image post-processing to display the output. This allows image processing algorithms to be implemented on FPGAs for real-time applications.
The document provides an overview of the Dirac video codec and compares its performance to H.264/MPEG-4 AVC. Dirac is an open source video compression format developed by the BBC that uses wavelet transforms and arithmetic coding. It achieves compression performance close to H.264/AVC at lower bitrates, with less complexity, though H.264 provides slightly better compression at higher resolutions. Testing showed Dirac performs better than H.264 at low bitrates for QCIF sequences.
This document discusses the unique challenges in static timing analysis (STA) for field programmable gate arrays (FPGAs). It notes that FPGA timing analysis must account for the programmable logic blocks and routing in the device. Specifically, it outlines three main challenges: 1) modeling the delays of look-up tables (LUTs) which can implement different logic functions based on their configuration, 2) avoiding an explosion in the number of timing modes when analyzing hierarchical or complex blocks, and 3) accurately modeling the delays of pass gate multiplexers. It provides examples and potential approaches for addressing each challenge.
Why a zynq should power your next projectMark Smith
Intro to FPGA's I presented to the Melbourne PC users group on 11th April 2018. I demo'ed blinking LEDS on a Zybo board using bare metal and then a memory mapped application process.
This document discusses image processing applications using Vivado for FPGAs. It provides information on FPGA architecture including distributed memory, block RAM features, and core generator. An example of a real-time breast cancer diagnosis application using YOLO on an FPGA board is described. A second example discusses implementing CCSDS standard DWT-based hyperspectral image decompression on an FPGA using techniques like Haar wavelet transform and MAP encoding.
The document describes the Xilinx XA Zynq UltraScale+ MPSoC family of devices. The family integrates a 64-bit quad-core ARM Cortex-A53 processing system with a dual-core ARM Cortex-R5 real-time processing system and programmable logic on a single chip. The devices include on-chip memory, external memory interfaces, and peripheral connectivity interfaces to support a wide range of applications including automotive systems. Key features of the processing system include CPU cores, graphics processing, DMA controllers, and interfaces. The programmable logic contains configurable logic blocks, block RAM, DSP slices, transceivers, and other programmable resources.
Lightweight DNN Processor Design (based on NVDLA)Shien-Chun Luo
https://sites.google.com/view/itri-icl-dla/
(Public Information Share) This is our lightweight DNN inference processor presentation, including a system solution (from Caffe prototxt to HW controls files), hardware features, and an example of object detection (Tiny YOLO) RTL simulation results. We modified open-source NVDLA, small configuration, and developed a RISC-V MCU in this accelerating system.
Implementation of FPGA Based Image Processing Algorithm using Xilinx System G...IRJET Journal
This document describes the implementation of various image processing algorithms using the Xilinx System Generator integrated with the Matlab/Simulink environment. It discusses algorithms for converting an RGB image to grayscale, generating a negative image, enhancing contrast and brightness, thresholding, background subtraction, erosion, dilation, edge detection, and masking. The algorithms are modeled in Simulink using Xilinx System Generator blocks and hardware co-simulation is used to verify the results. The key steps involve image pre-processing to prepare input data, implementing the algorithm using Xilinx blocks, and image post-processing to display the output. This allows image processing algorithms to be implemented on FPGAs for real-time applications.
The document provides an overview of the Dirac video codec and compares its performance to H.264/MPEG-4 AVC. Dirac is an open source video compression format developed by the BBC that uses wavelet transforms and arithmetic coding. It achieves compression performance close to H.264/AVC at lower bitrates, with less complexity, though H.264 provides slightly better compression at higher resolutions. Testing showed Dirac performs better than H.264 at low bitrates for QCIF sequences.
This document discusses the unique challenges in static timing analysis (STA) for field programmable gate arrays (FPGAs). It notes that FPGA timing analysis must account for the programmable logic blocks and routing in the device. Specifically, it outlines three main challenges: 1) modeling the delays of look-up tables (LUTs) which can implement different logic functions based on their configuration, 2) avoiding an explosion in the number of timing modes when analyzing hierarchical or complex blocks, and 3) accurately modeling the delays of pass gate multiplexers. It provides examples and potential approaches for addressing each challenge.
Why a zynq should power your next projectMark Smith
Intro to FPGA's I presented to the Melbourne PC users group on 11th April 2018. I demo'ed blinking LEDS on a Zybo board using bare metal and then a memory mapped application process.
This document discusses image processing applications using Vivado for FPGAs. It provides information on FPGA architecture including distributed memory, block RAM features, and core generator. An example of a real-time breast cancer diagnosis application using YOLO on an FPGA board is described. A second example discusses implementing CCSDS standard DWT-based hyperspectral image decompression on an FPGA using techniques like Haar wavelet transform and MAP encoding.
The document describes the Xilinx XA Zynq UltraScale+ MPSoC family of devices. The family integrates a 64-bit quad-core ARM Cortex-A53 processing system with a dual-core ARM Cortex-R5 real-time processing system and programmable logic on a single chip. The devices include on-chip memory, external memory interfaces, and peripheral connectivity interfaces to support a wide range of applications including automotive systems. Key features of the processing system include CPU cores, graphics processing, DMA controllers, and interfaces. The programmable logic contains configurable logic blocks, block RAM, DSP slices, transceivers, and other programmable resources.
Lightweight DNN Processor Design (based on NVDLA)Shien-Chun Luo
https://sites.google.com/view/itri-icl-dla/
(Public Information Share) This is our lightweight DNN inference processor presentation, including a system solution (from Caffe prototxt to HW controls files), hardware features, and an example of object detection (Tiny YOLO) RTL simulation results. We modified open-source NVDLA, small configuration, and developed a RISC-V MCU in this accelerating system.
The document describes the implementation of an FPGA-based video capture card that takes in an analog VGA video source, captures the video at 1024x768 resolution and 30 frames per second, compresses the data, and outputs it through a USB 2.0 port to a PC. The design uses a Xilinx Spartan 3A FPGA board with a video capture daughter board, Xilinx Platform Studio for hardware/software integration, and AccelDSP for implementing a video compression core. Challenges included integrating the various hardware and software components and developing the USB interface.
11 Synchoricity as the basis for going Beyond MooreRCCSRENKEI
The document discusses synchronicity as a basis for going beyond Moore's law through the use of silicon lego (SiLago) blocks. SiLago blocks allow for the temporal and spatial composition of designs by ensuring clock and grid cell alignment during composition. This enables very large designs to be synthesized from higher levels of abstraction. Example SiLago block types include functional units like dense linear algebra blocks as well as infrastructure units like networks-on-chips. The document argues that treating SiLago blocks as the new standard cells could enable new design methodologies and computational paradigms like computation in memory to achieve major improvements in performance, energy, and cost beyond what is possible with conventional CMOS scaling alone.
Distributed Video Coding (DVC) has become increasingly popular in recent times among the researchers in video coding due to its attractive and promising features. DVC primarily has a modified complexity balance between the encoder and decoder, in contrast to conventional video codecs. However, Most of the reported DVC schemes have a high time-delay in decoder which hinders its practical application in real-time systems. In this work, we focus on speed up the Side Information(SI) generation module in DVC, which is a major function in the DVC coding algorithm and one of the time-consuming factor at the decoder. By applied it through Compute Unified Device Architecture (CUDA) based on General-Purpose Graphics Processing Unit (GPGPU), the experimental results show that a considerable speedup can be obtained by using the proposed parallelized SI generation algorithm.
The document discusses accelerators for improving performance in digital systems. It describes how accelerators can perform operations in parallel to speed up algorithms. Key points include:
- Accelerators use custom hardware to perform parallel operations that would be too slow on a general-purpose processor.
- Amdahl's law describes how speeding up part of an algorithm affects the overall speedup achievable.
- Common parallel architectures include replication for independent data elements and pipelining to break computations into sequential steps.
- The document then provides an example accelerator for edge detection in images using the Sobel algorithm. It describes the algorithm, data rates, memory bandwidth considerations, and pipeline architecture.
Monte Carlo simulation is well-suited for GPU acceleration due to its highly parallel nature. GPUs provide lower cost and higher performance than CPUs for Monte Carlo applications. Numerical libraries for GPUs allow developers to focus on their models rather than reimplementing basic components. NAG has developed GPU libraries including random number generators and is working with financial institutions to apply Monte Carlo simulations to problems in finance.
This document presents a sequential quadratic programming (SQP) algorithm for sizing clock meshes to minimize area while meeting skew constraints. The algorithm uses adjoint sensitivity analysis and a compact gate model to efficiently compute sensitivities. It formulates and solves a quadratic programming subproblem at each iteration to determine wire width updates. Experimental results on ISCAS and ISPD benchmarks show up to 33% reduction in clock mesh area compared to initial designs. Future work will extend the approach to simultaneously size interconnects and buffers.
Tarun Arora is seeking an internship in analog domain. He has a Master's degree in Electrical Engineering from Arizona State University and a Bachelor's degree from Kurukshetra University in India. His relevant coursework includes analog integrated circuits and VLSi design. He has experience with Cadence and other design tools. His projects include designing operational transconductance amplifiers and constant current references using Cadence. He also has experience with embedded systems and microcontrollers from projects in college. Previously he interned at a power plant and worked as a systems engineer at Tata Consultancy Services.
The document is a resume for Tarun Arora seeking an internship in Analog and Mixed Signal Design. It summarizes his education, including a Master's degree in Electrical Engineering from Arizona State University and a Bachelor's degree from Kurukshetra University in India. It also lists his relevant coursework, technical skills, projects, and professional experience which include various circuit and system design projects as well as work experience at Tata Consultancy Services and an internship at a National Thermal Power Plant.
This document describes the design and development of a fault-tolerant and dynamically reconfigurable payload processing unit (PPU) for the Pakistan National Student Satellite-1 (PNSS-1). The proposed PPU uses a Xilinx Virtex 5QV field-programmable gate array (FPGA) and a radiation-hardened Leon 3 FT processor. Triple modular redundancy is implemented to minimize effects of single event upsets, single event latchups, and total ionizing dose from radiation in space. The PPU is responsible for receiving, storing, processing, and transmitting data from various satellite payloads. It will provide telemetry to and receive commands from the satellite's data handling unit over a CAN bus or dedicated
The signal processing algorithms can be implemented on hardware using various strategies such as DSP processors and ASIC. This PPT compares and contrasts the two methods.
This document discusses the architecture of Xilinx Cool Runner CPLDs. It provides an overview of Xilinx CPLD technologies including Cool Runner XPLA3 and Cool Runner-II. For the Cool Runner XPLA3, it describes the features and specifications, and details the architecture including the high-level block diagram, function block, macrocell, and I/O cell. For the Cool Runner-II, it lists the key features and specifications. The document is intended to explain the architectures of these Xilinx CPLD families.
The document discusses processors and embedded systems. It covers embedded computer components like processor cores, memory, and I/O controllers. It also describes different types of processors like microprocessors, microcontrollers, processor cores, and digital signal processors. The remainder of the document focuses on the instruction set and programming of the Gumnut processor core, including details about its instructions, memory organization, and assembler.
This document summarizes several papers on implementing feedforward neural networks using field programmable gate arrays (FPGAs). It discusses how FPGAs offer parallelism and flexibility for neural network designs while reducing costs compared to application-specific integrated circuits. The document reviews mathematical models of artificial neurons and different types of neural network architectures. It also examines challenges in efficiently implementing activation functions like the sigmoid on FPGAs. Several papers presented hardware implementations of multilayer feedforward neural networks in VHDL for applications such as digital pre-distortion.
This document provides an abstract for a project report on image non-uniformity correction in infrared focal plane arrays. The project involved implementing a two-point non-uniformity correction algorithm using an ADSP TigerSHARC digital signal processor. The algorithm aims to reduce fixed pattern noise in images acquired by an infrared focal plane array, which can vary in response across detectors. Software was developed using the VisualDSP++ integrated development environment to calibrate and correct detector outputs based on measurements from a blackbody at two reference temperatures. Graphs of temperature versus corrected output and root-mean-square error show the results of the non-uniformity correction.
Volume ray casting algorithms benefit greatly with recent increase of GPU capabilities and power. In this paper,
we present a novel memory efficient ray casting algorithm for unstructured grids completely implemented on GPU
using a recent off-the-shelf nVidia graphics card. Our approach is built upon a recent CPU ray casting algorithm,
called VF-Ray, that considerably reduces the memory footprint while keeping good performance. In addition to
the implementation of VF-Ray in the graphics hardware, we also propose a restructuring in its data structures. As
a result, our algorithm is much faster than the original software version, while using significantly less memory, it
needed only one-half of its previous memory usage. Comparing our GPU implementation to other hardware-based
ray casting algorithms, our approach used between three to ten times less memory. These results made it possible
for our GPU implementation to handle larger datasets on GPU than previous approaches.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
This document discusses test data compression techniques for system-on-chip designs. It presents the XMatchPro algorithm that combines dictionary-based and bit mask-based compression to significantly reduce testing time and memory requirements. The algorithm was applied to benchmarks and achieved a 92% compression efficiency while improving decompression efficiency by up to 90% compared to other techniques without additional overhead. International lossless compression techniques are also overviewed, including dictionary-based Lempel-Ziv methods that have been implemented in hardware using systolic arrays or content addressable memories.
Design and analysis of optimized CORDIC based GMSK system on FPGA platform IJECEIAES
The gaussian minimum shift keying (GMSK) is one of the best suited digital modulation schemes in the global system for mobile communication (GSM) because of its constant envelop and spectral efficiency characteristics. Most of the conventional GMSK approaches failed to balance the digital modulation with efficient usage of spectrum. In this article, the hardware architecture of the optimized CORDIC-based GMSK system is designed, which includes GMSK Modulation with the channel and GMSK Demodulation. The modulation consists of non-return zero (NRZ) encoder, an integrator followed by Gaussian filtering and frequency modulation (FM). The GMSK demodulation consists of FM demodulator, followed by differentiation and NRZ decoder. The FM Modulation and demodulation use the optimized CORDIC model for an In-phase (I) and quadrature (Q) phase generation. The optimized CORDIC is designed by using quadrant mapping and pipelined structure to improve the hardware and computational complexity in GMSK systems. The GMSK system is designed on the Xilinx platform and implemented on Artix-7 and Spartan-3EFPGA. The hardware constraints like area, power, and timing utilization are summarized. The comparison of the optimized CORDIC model with similar CORDIC approaches is tabulated with improvements.
Enabling Machine Learning on the Edge using SRAM Conserving Efficient Neural ...Bharath Sudharsan
Paper Pdf: https://scholarcommons.sc.edu/aii_fac_pub/520/
Edge analytics refers to the application of data analytics and Machine Learning (ML) algorithms on IoT devices. The concept of edge analytics is gaining popularity due to its ability to perform AI-based analytics at the device level, enabling autonomous decision-making, without depending on the cloud. However, the majority of Internet of Things (IoT) devices are embedded systems with a low-cost microcontroller unit (MCU) or a small CPU as its brain, which often are incapable of handling complex ML algorithms.
In this paper, we propose an approach for the efficient execution of already deeply compressed, large neural networks (NNs) on tiny IoT devices. After optimizing NNs using state-of-the-art deep model compression methods, when the resultant models are executed by MCUs or small CPUs using the model execution sequence produced by our approach, higher levels of conserved SRAM can be achieved. During the evaluation for nine popular models, when comparing the default NN execution sequence with the sequence produced by our approach, we found that 1.61-38.06\% less SRAM was used to produce inference results, the inference time was reduced by 0.28-4.9 ms, and energy consumption was reduced by 4-84 mJ. Despite achieving such high conserved levels of SRAM, our method 100% preserved the accuracy, F1 score, etc. (model performance).
This document summarizes a research paper that analyzes the linear growth rate of perturbations in magneto-thermal convection of a couple-stress fluid in a porous medium. The authors establish that the growth rate of oscillatory perturbations must lie within a semi-circle in the right half of the complex plane. This region is bounded based on material properties like permeability, porosity, thermal and magnetic Prandtl numbers. The results provide upper limits to the growth rate for any combination of perfectly conducting free and rigid boundaries, without requiring exact solutions.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
The document describes the implementation of an FPGA-based video capture card that takes in an analog VGA video source, captures the video at 1024x768 resolution and 30 frames per second, compresses the data, and outputs it through a USB 2.0 port to a PC. The design uses a Xilinx Spartan 3A FPGA board with a video capture daughter board, Xilinx Platform Studio for hardware/software integration, and AccelDSP for implementing a video compression core. Challenges included integrating the various hardware and software components and developing the USB interface.
11 Synchoricity as the basis for going Beyond MooreRCCSRENKEI
The document discusses synchronicity as a basis for going beyond Moore's law through the use of silicon lego (SiLago) blocks. SiLago blocks allow for the temporal and spatial composition of designs by ensuring clock and grid cell alignment during composition. This enables very large designs to be synthesized from higher levels of abstraction. Example SiLago block types include functional units like dense linear algebra blocks as well as infrastructure units like networks-on-chips. The document argues that treating SiLago blocks as the new standard cells could enable new design methodologies and computational paradigms like computation in memory to achieve major improvements in performance, energy, and cost beyond what is possible with conventional CMOS scaling alone.
Distributed Video Coding (DVC) has become increasingly popular in recent times among the researchers in video coding due to its attractive and promising features. DVC primarily has a modified complexity balance between the encoder and decoder, in contrast to conventional video codecs. However, Most of the reported DVC schemes have a high time-delay in decoder which hinders its practical application in real-time systems. In this work, we focus on speed up the Side Information(SI) generation module in DVC, which is a major function in the DVC coding algorithm and one of the time-consuming factor at the decoder. By applied it through Compute Unified Device Architecture (CUDA) based on General-Purpose Graphics Processing Unit (GPGPU), the experimental results show that a considerable speedup can be obtained by using the proposed parallelized SI generation algorithm.
The document discusses accelerators for improving performance in digital systems. It describes how accelerators can perform operations in parallel to speed up algorithms. Key points include:
- Accelerators use custom hardware to perform parallel operations that would be too slow on a general-purpose processor.
- Amdahl's law describes how speeding up part of an algorithm affects the overall speedup achievable.
- Common parallel architectures include replication for independent data elements and pipelining to break computations into sequential steps.
- The document then provides an example accelerator for edge detection in images using the Sobel algorithm. It describes the algorithm, data rates, memory bandwidth considerations, and pipeline architecture.
Monte Carlo simulation is well-suited for GPU acceleration due to its highly parallel nature. GPUs provide lower cost and higher performance than CPUs for Monte Carlo applications. Numerical libraries for GPUs allow developers to focus on their models rather than reimplementing basic components. NAG has developed GPU libraries including random number generators and is working with financial institutions to apply Monte Carlo simulations to problems in finance.
This document presents a sequential quadratic programming (SQP) algorithm for sizing clock meshes to minimize area while meeting skew constraints. The algorithm uses adjoint sensitivity analysis and a compact gate model to efficiently compute sensitivities. It formulates and solves a quadratic programming subproblem at each iteration to determine wire width updates. Experimental results on ISCAS and ISPD benchmarks show up to 33% reduction in clock mesh area compared to initial designs. Future work will extend the approach to simultaneously size interconnects and buffers.
Tarun Arora is seeking an internship in analog domain. He has a Master's degree in Electrical Engineering from Arizona State University and a Bachelor's degree from Kurukshetra University in India. His relevant coursework includes analog integrated circuits and VLSi design. He has experience with Cadence and other design tools. His projects include designing operational transconductance amplifiers and constant current references using Cadence. He also has experience with embedded systems and microcontrollers from projects in college. Previously he interned at a power plant and worked as a systems engineer at Tata Consultancy Services.
The document is a resume for Tarun Arora seeking an internship in Analog and Mixed Signal Design. It summarizes his education, including a Master's degree in Electrical Engineering from Arizona State University and a Bachelor's degree from Kurukshetra University in India. It also lists his relevant coursework, technical skills, projects, and professional experience which include various circuit and system design projects as well as work experience at Tata Consultancy Services and an internship at a National Thermal Power Plant.
This document describes the design and development of a fault-tolerant and dynamically reconfigurable payload processing unit (PPU) for the Pakistan National Student Satellite-1 (PNSS-1). The proposed PPU uses a Xilinx Virtex 5QV field-programmable gate array (FPGA) and a radiation-hardened Leon 3 FT processor. Triple modular redundancy is implemented to minimize effects of single event upsets, single event latchups, and total ionizing dose from radiation in space. The PPU is responsible for receiving, storing, processing, and transmitting data from various satellite payloads. It will provide telemetry to and receive commands from the satellite's data handling unit over a CAN bus or dedicated
The signal processing algorithms can be implemented on hardware using various strategies such as DSP processors and ASIC. This PPT compares and contrasts the two methods.
This document discusses the architecture of Xilinx Cool Runner CPLDs. It provides an overview of Xilinx CPLD technologies including Cool Runner XPLA3 and Cool Runner-II. For the Cool Runner XPLA3, it describes the features and specifications, and details the architecture including the high-level block diagram, function block, macrocell, and I/O cell. For the Cool Runner-II, it lists the key features and specifications. The document is intended to explain the architectures of these Xilinx CPLD families.
The document discusses processors and embedded systems. It covers embedded computer components like processor cores, memory, and I/O controllers. It also describes different types of processors like microprocessors, microcontrollers, processor cores, and digital signal processors. The remainder of the document focuses on the instruction set and programming of the Gumnut processor core, including details about its instructions, memory organization, and assembler.
This document summarizes several papers on implementing feedforward neural networks using field programmable gate arrays (FPGAs). It discusses how FPGAs offer parallelism and flexibility for neural network designs while reducing costs compared to application-specific integrated circuits. The document reviews mathematical models of artificial neurons and different types of neural network architectures. It also examines challenges in efficiently implementing activation functions like the sigmoid on FPGAs. Several papers presented hardware implementations of multilayer feedforward neural networks in VHDL for applications such as digital pre-distortion.
This document provides an abstract for a project report on image non-uniformity correction in infrared focal plane arrays. The project involved implementing a two-point non-uniformity correction algorithm using an ADSP TigerSHARC digital signal processor. The algorithm aims to reduce fixed pattern noise in images acquired by an infrared focal plane array, which can vary in response across detectors. Software was developed using the VisualDSP++ integrated development environment to calibrate and correct detector outputs based on measurements from a blackbody at two reference temperatures. Graphs of temperature versus corrected output and root-mean-square error show the results of the non-uniformity correction.
Volume ray casting algorithms benefit greatly with recent increase of GPU capabilities and power. In this paper,
we present a novel memory efficient ray casting algorithm for unstructured grids completely implemented on GPU
using a recent off-the-shelf nVidia graphics card. Our approach is built upon a recent CPU ray casting algorithm,
called VF-Ray, that considerably reduces the memory footprint while keeping good performance. In addition to
the implementation of VF-Ray in the graphics hardware, we also propose a restructuring in its data structures. As
a result, our algorithm is much faster than the original software version, while using significantly less memory, it
needed only one-half of its previous memory usage. Comparing our GPU implementation to other hardware-based
ray casting algorithms, our approach used between three to ten times less memory. These results made it possible
for our GPU implementation to handle larger datasets on GPU than previous approaches.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
This document discusses test data compression techniques for system-on-chip designs. It presents the XMatchPro algorithm that combines dictionary-based and bit mask-based compression to significantly reduce testing time and memory requirements. The algorithm was applied to benchmarks and achieved a 92% compression efficiency while improving decompression efficiency by up to 90% compared to other techniques without additional overhead. International lossless compression techniques are also overviewed, including dictionary-based Lempel-Ziv methods that have been implemented in hardware using systolic arrays or content addressable memories.
Design and analysis of optimized CORDIC based GMSK system on FPGA platform IJECEIAES
The gaussian minimum shift keying (GMSK) is one of the best suited digital modulation schemes in the global system for mobile communication (GSM) because of its constant envelop and spectral efficiency characteristics. Most of the conventional GMSK approaches failed to balance the digital modulation with efficient usage of spectrum. In this article, the hardware architecture of the optimized CORDIC-based GMSK system is designed, which includes GMSK Modulation with the channel and GMSK Demodulation. The modulation consists of non-return zero (NRZ) encoder, an integrator followed by Gaussian filtering and frequency modulation (FM). The GMSK demodulation consists of FM demodulator, followed by differentiation and NRZ decoder. The FM Modulation and demodulation use the optimized CORDIC model for an In-phase (I) and quadrature (Q) phase generation. The optimized CORDIC is designed by using quadrant mapping and pipelined structure to improve the hardware and computational complexity in GMSK systems. The GMSK system is designed on the Xilinx platform and implemented on Artix-7 and Spartan-3EFPGA. The hardware constraints like area, power, and timing utilization are summarized. The comparison of the optimized CORDIC model with similar CORDIC approaches is tabulated with improvements.
Enabling Machine Learning on the Edge using SRAM Conserving Efficient Neural ...Bharath Sudharsan
Paper Pdf: https://scholarcommons.sc.edu/aii_fac_pub/520/
Edge analytics refers to the application of data analytics and Machine Learning (ML) algorithms on IoT devices. The concept of edge analytics is gaining popularity due to its ability to perform AI-based analytics at the device level, enabling autonomous decision-making, without depending on the cloud. However, the majority of Internet of Things (IoT) devices are embedded systems with a low-cost microcontroller unit (MCU) or a small CPU as its brain, which often are incapable of handling complex ML algorithms.
In this paper, we propose an approach for the efficient execution of already deeply compressed, large neural networks (NNs) on tiny IoT devices. After optimizing NNs using state-of-the-art deep model compression methods, when the resultant models are executed by MCUs or small CPUs using the model execution sequence produced by our approach, higher levels of conserved SRAM can be achieved. During the evaluation for nine popular models, when comparing the default NN execution sequence with the sequence produced by our approach, we found that 1.61-38.06\% less SRAM was used to produce inference results, the inference time was reduced by 0.28-4.9 ms, and energy consumption was reduced by 4-84 mJ. Despite achieving such high conserved levels of SRAM, our method 100% preserved the accuracy, F1 score, etc. (model performance).
This document summarizes a research paper that analyzes the linear growth rate of perturbations in magneto-thermal convection of a couple-stress fluid in a porous medium. The authors establish that the growth rate of oscillatory perturbations must lie within a semi-circle in the right half of the complex plane. This region is bounded based on material properties like permeability, porosity, thermal and magnetic Prandtl numbers. The results provide upper limits to the growth rate for any combination of perfectly conducting free and rigid boundaries, without requiring exact solutions.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a study on deconvoluting the flood hydrograph at the outlet of the Kolondieba watershed in Mali to understand the runoff process. Monitoring of physicochemical parameters was conducted from 2009-2011 at rainfall, surface water, and groundwater sites. Analysis using electrical conductivity and total dissolved solids as tracers showed runoff was composed of 77% rapid flow from rainfall and 23% delayed flow from shallow aquifers during 2010's wet season. In 2011, rapid flow increased 3% as shallow aquifer discharge declined 6.8% due to lower rainfall. The study found groundwater contributes little to hydrologic balance at the outlet, and surface runoff from rainfall heavily influenced by degraded land
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a study estimating and mapping evapotranspiration in the Kolondièba-Tiendaga basin in Mali from 2003 to 2010 using the SEBS (Surface Energy Balance System) model and AATSR satellite imagery. The study finds a strong correlation between evapotranspiration and evaporative fraction from 2003 to 2008, with correlation coefficients between 0.60 and 0.90, but lower correlations (0.34 to 0.40) in 2009-2010. Evapotranspiration values ranged from 1 to 3mm/J-1. The results indicate the potential of using remote sensing to estimate evapotranspiration over large areas.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document summarizes a study on wall pressure distribution in a suddenly expanded flow for an area ratio of 2.56. Experiments were conducted by attaching an enlarged duct to the exit of an axisymmetric convergent-divergent nozzle. Wall pressure was measured for nozzle pressure ratios of 3-11 and Mach numbers of 1.87, 2.2, and 2.58. Microjets were used as an active control method to study their effect on wall pressure distribution. Results showed that microjets did not adversely affect the oscillatory wall pressure field for most conditions tested. At Mach 2.58 and NPR of 9, microjets significantly increased the reattachment length in the duct. In general, microjets were found
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
This document discusses built-in self-test (BIST) techniques for testing field programmable gate arrays (FPGAs). It describes how the FPGA can be configured with BIST logic during offline testing to test the programmable logic blocks and interconnects. For online testing, the FPGA can be configured as a processor with an arithmetic logic unit (ALU) that has a BIST feature. The design implements a reduced instruction set computer (RISC) architecture on the FPGA with the ALU and is verified through simulation. BIST allows exhaustive testing of the FPGA at operating speed without external test equipment.
This document summarizes a study characterizing a landfill in Mohammedia, Morocco. Samples were taken from 5 stations around the landfill and near the El Maleh river to analyze physical and chemical properties. Heavy metals like lead and chromium were found in high concentrations in leachates from the landfill and sediments near the river. Pollution from the landfill's discharge was impacting the river water quality. The aim was to evaluate the physico-chemical quality of El Maleh river water in relation to leachate from the converted clay quarry landfill and identify a rehabilitation plan.
The document analyzes supersonic flow through conical rocket nozzles using computational fluid dynamics (CFD). It discusses nozzle design and simulations conducted at divergence angles of 7, 20, and 30 degrees. The results show variations in parameters like Mach number, pressure, temperature, and turbulence intensity across the different configurations. Mach number increases from subsonic to supersonic values through the nozzle, while pressure decreases rapidly after the throat. Higher divergence angles produce higher exit Mach numbers but more over-expansion.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
The document summarizes the municipal solid waste management scenario of Kakinada City, India. Some key points:
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- Increasing population is leading to more waste generation but inadequate infrastructure and management, posing environmental and health problems.
5 boys and 3 girls liked football, while 5 boys and 3 girls liked basketball. Of the 16 students surveyed, 3 girls liked both football and basketball, while 5 boys liked football and 5 different boys liked basketball. The survey found that 19% of girls and 31% of boys liked basketball, for a total of 49% of students who preferred that sport.
La Universidad Fermín Toro está implementando un Sistema de Aprendizaje Interactivo a Distancia para ofrecer un Diplomado en Educación Interactiva a Distancia en mayo de 2013. El documento fue escrito por Luz Mary Castillo y detalla el nuevo programa de educación en línea de la universidad.
Keenan Jellison-Knock was a person who inspired Sheena Brubaker from 1994 to 2013. Brubaker wrote about her inspiration, Keenan Jellison-Knock, in a short piece that included his name and dates of life but provided no further details about who he was or what specifically inspired Brubaker.
Pemerintah Indonesia berencana mengembangkan industri halal untuk meningkatkan ekspor dan pariwisata. Beberapa langkah yang akan dilakukan antara lain mempromosikan produk halal ke pasar global, meningkatkan sertifikasi produk halal, serta melatih SDM agar mampu bersaing di industri halal.
This document discusses techniques for effective compression of digital video. It introduces several key algorithms used in video compression, including discrete cosine transform (DCT) for spatial redundancy reduction, motion estimation (ME) for temporal redundancy reduction, and embedded zerotree wavelet (EZW) transforms. DCT is used to compress individual video frames by removing spatial correlations within frames. Motion estimation compares blocks of pixels between frames to find and encode motion vectors rather than full pixel values, reducing file size. Combined, these techniques can achieve high compression ratios while maintaining high video quality for storage and transmission.
Secured Data Transmission Using Video Steganographic SchemeIJERA Editor
Steganography is the art of hiding information in ways that avert the revealing of hiding messages. Video Steganography is focused on spatial and transform domain. Spatial domain algorithm directly embedded information in the cover image with no visual changes. This kind of algorithms has the advantage in Steganography capacity, but the disadvantage is weak robustness. Transform domain algorithm is embedding the secret information in the transform space. This kind of algorithms has the advantage of good stability, but the disadvantage of small capacity. These kinds of algorithms are vulnerable to steganalysis. This paper proposes a new Compressed Video Steganographic scheme. The data is hidden in the horizontal and the vertical components of the motion vectors. The PSNR value is calculated so that the quality of the video after the data hiding is evaluated.
Fast and Secure Transmission of Image by using Byte Rotation Algorithm in Net...IRJET Journal
This document proposes a new secure image transmission method using byte rotation algorithm that improves encryption speed and security. The key steps are:
1. The input image is divided into four blocks which are shuffled using byte rotation.
2. A cover image is used to embed the shuffled secret image blocks for transmission.
3. At the receiver, byte rotation is applied again to extract the original secret image blocks from the embedded image.
Experimental results show the proposed method recovers images with high PSNR quality scores while increasing encryption speed over other algorithms like AES. This provides a more secure and fast way to transmit encrypted images over networks.
This document is a mini project report on digital image processing using MATLAB. It discusses various image processing techniques and applications implemented in MATLAB, including image formats, operations, and tools. Applications demonstrated include text recognition, color tracking, solving an engineering problem using image processing, creating a virtual slate using laser tracking, face detection, and distance estimation. The report provides examples of MATLAB functions used for tasks like importing, displaying, converting and cropping images, as well as analyzing and manipulating them.
This document summarizes an article that proposes modifications to the JPEG 2000 image compression standard to achieve higher compression ratios while maintaining acceptable error rates. The proposed Adaptive JPEG 2000 technique involves pre-processing images with a transfer function to make them more suitable for compression by JPEG 2000. This is intended to provide higher compression ratios than the original JPEG 2000 standard while keeping root mean square error within allowed thresholds. The document provides background on JPEG 2000 and lossy image compression techniques, describes the proposed pre-processing approach, and indicates it was tested on single-channel images.
This document discusses various image compression methods and algorithms. It begins by explaining the need for image compression in applications like transmission, storage, and databases. It then reviews different types of compression, including lossless techniques like run length encoding and Huffman encoding, and lossy techniques like transformation coding, vector quantization, fractal coding, and subband coding. The document also describes the JPEG 2000 image compression algorithm and applications of JPEG 2000. Finally, it discusses self-organizing feature maps (SOM) and learning vector quantization (VQ) for image compression.
Design of digital video watermarking scheme using matlab simulinkeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Design of digital video watermarking scheme using matlab simulinkeSAT Journals
Abstract
Due to increase in growth of internet users of networks are increasing rapidly. Owners of the digital products are concerned about illegal copying of their products. Security and copyright protection are becoming important issues in multimedia applications and services. Digital watermarking is a technology used for copyright protection of digital media. Here ownership information data called watermark is embedded into the digital media without affecting its perceptual quality. In case of any dispute, the watermark data can be detected or extracted from the media and use as a proof of ownership. Digital video watermarking scheme based on Discrete Wavelet Transform is addressed in this paper. Design of this scheme using Matlab Simulink is proposed. Embedded watermark is robust against various attacks that can be carried out on the watermarked video. Index Terms:Digital video, Discrete Wavelet Transform, Binary watermark.
IRJET- A Non Uniformity Process using High Picture Range QualityIRJET Journal
This document discusses image compression techniques using high picture quality. It proposes a non-uniformity process that can compress entire images and videos to low storage space while maintaining high quality. The process dynamically selects images for compression based on their properties. It implements encoding and decoding algorithms with quantization to reconstruct compressed data efficiently while fully compressing videos and images. This achieves high coding efficiency and reduces storage requirements for images and videos.
IRJET- Mosaic Image Creation in Video for Secure TransmissionIRJET Journal
This document proposes a new method for securely transmitting images over a medium using mosaic image creation in video. The method has two main phases:
1) Mosaic video creation: A video is selected and its frames are used to create a mosaic image that resembles a target secret image. Color transformations are applied to fit tiles of the secret image into blocks of frames. Relevant information for recovery is embedded into the mosaic video.
2) Secret image recovery: At the receiving end, the frames are extracted from the video. The embedded information is extracted to recover tiles of the secret image from the mosaic frames through inverse transformations. The secret image is thus reconstructed without any loss.
Lossless Encryption using BITPLANE and EDGEMAP Crypt AlgorithmsIRJET Journal
The document discusses two lossless image encryption algorithms: the bit plane crypt algorithm and the edge map crypt algorithm. Both algorithms use a key image of the same size as the original image to encrypt the image. The bit plane algorithm extracts a bit plane from another image to generate the key image. It then performs an XOR operation between the key image and each bit plane of the original image. The edge map algorithm generates the key image by detecting edges in another image and encrypts each bit plane of the original image using an XOR with the edge map. Both algorithms invert the bit plane order and combine them to produce the encrypted image. Simulation results show the original image can be recovered losslessly from the encrypted image using the decryption process for
Digital image processing involves compressing images to reduce file sizes. Image compression removes redundant data using three main techniques: coding redundancy reduction assigns shorter codes to more common pixel values; spatial and temporal redundancy reduction exploits correlations between neighboring pixel values; and irrelevant information removal discards visually unimportant data. Compression is achieved by an encoder that applies these techniques, while a decoder reconstructs the image for viewing. Popular compression methods include Huffman coding and arithmetic coding. Compression allows storage and transmission of images and video using less data while maintaining acceptable visual quality.
An overview Survey on Various Video compressions and its importanceINFOGAIN PUBLICATION
With the rise of digital computing and visual data processing, the need for storage and transmission of video data became prevalent. Storage and transmission of uncompressed raw visual data is not a good practice, because it requires a large storage space and great bandwidth. Video compression algorithms can compress this raw visual data or video into smaller files with a little sacrifice on the quality. This paper an overview and comparison of standard efforts on video compression algorithm of: MPEG-1, MPEG-2, MPEG-4, MPEG-7
Efficient video compression using EZWTIJERA Editor
In this article, wavelet based lossy video compression algorithm is presented. The motion estimation and compensation, being an important part in the compression, is based on segment movements. The proposed work is based on wavelet transform algorithm Embedded Zeroed WaveletTransform (EZWT). Based on the results of peak signal to noise ratio (PSNR), mean squared error (MSE), different videos are analyzed. Maintaining the PSNR to acceptable limits the proposed EZWT algorithm achieves very good compression ratios making the technique more efficient than the 2-Discrete Cosine Transform (DCT) in the H.264/AVC codec. The method is being suitable for low bit rate video showing highest compression ratio and very good PSNR of more than 30dB.
The Computation Complexity Reduction of 2-D Gaussian FilterIRJET Journal
This document discusses reducing the computational complexity of a 2D Gaussian filter for image smoothing. It begins with an abstract that notes 2D Gaussian filters are commonly used for image smoothing but require heavy computational resources. It then proposes using fixed-point arithmetic rather than floating point to implement the filter on an FPGA, which can increase efficiency and decrease area and complexity. The document is divided into sections that cover the theory behind image filtering, image smoothing and sharpening, quality metrics for evaluation, and an energy scalable Gaussian smoothing filter architecture. It concludes by discussing results and benefits of implementing the filter using fixed-point arithmetic on an FPGA.
International Journal of Computational Engineering Research(IJCER)ijceronline
The document describes a Simulink model for splitting real-time video/images into four blocks in real-time. The model takes in an RGB video, splits it into four 128x128 blocks using a submatrix block, resizes the blocks back to the original resolution, and displays each block on a separate screen. The model is implemented using various Simulink blocks like resize, color space conversion, matrix concatenation, and submatrix selection to split, process, and display the video/image in real-time across multiple screens.
This document summarizes the development of real-time video processing IP cores in FPGA by NeST including a video scaler, sharpness enhancer, gamma correction, and picture quality enhancer modules. It describes the specifications, algorithms, and architectures of each module developed as reusable IP cores. The video scaler uses bilinear interpolation for scaling up and nearest neighbor for scaling down. The sharpness enhancer uses a Laplacian filter. Gamma correction uses programmable lookup tables. The picture quality enhancer contains brightness, contrast, and color adjustment modules. Together these cores form a video processing suite for applications like surveillance and medical imaging.
This document discusses a digital image processing (DIP) based system for identifying defects in industrial materials like steel rods. Images of reference and test samples are taken and compared using techniques like thresholding, histograms, and cell segmentation in MATLAB. Defects are identified by variations between the images. The system is implemented on an FPGA for hardware acceleration. Images of steel rods with and without defects are compared to demonstrate the system's ability to detect cracks. The DIP based approach can replace manual inspection and provides faster quality evaluation of industrial materials compared to software-only methods.
A High Performance Modified SPIHT for Scalable Image CompressionCSCJournals
In this paper, we present a novel extension technique to the Set Partitioning in Hierarchical Trees (SPIHT) based image compression with spatial scalability. The present modification and the preprocessing techniques provide significantly better quality (both subjectively and objectively) reconstruction at the decoder with little additional computational complexity. There are two proposals for this paper. Firstly, we propose a pre-processing scheme, called Zero-Shifting, that brings the spatial values in signed integer range without changing the dynamic ranges, so that the transformed coefficient calculation becomes more consistent. For that reason, we have to modify the initialization step of the SPIHT algorithms. The experiments demonstrate a significant improvement in visual quality and faster encoding and decoding than the original one. Secondly, we incorporate the idea to facilitate resolution scalable decoding (not incorporated in original SPIHT) by rearranging the order of the encoded output bit stream. During the sorting pass of the SPIHT algorithm, we model the transformed coefficient based on the probability of significance, at a fixed threshold of the offspring. Calling it a fixed context model and generating a Huffman code for each context, we achieve comparable compression efficiency to that of arithmetic coder, but with much less computational complexity and processing time. As far as objective quality assessment of the reconstructed image is concerned, we have compared our results with popular Peak Signal to Noise Ratio (PSNR) and with Structural Similarity Index (SSIM). Both these metrics show that our proposed work is an improvement over the original one.
Performance Analysis of Digital Watermarking Of Video in the Spatial Domainpaperpublications3
Abstract:In this paper, we have suggested the spatial domain method for the digital video watermarking for both visible and invisible watermarks. The methods are used for the copyright protection as well as proof of ownership. In this paper we first extracted the frames from the video and then used spatial domain characteristics of the frames where we directly worked on the pixel value of the frame according to the watermark and calculated different parameters.
Keywords:Digital video watermarking, copyright protection, spatial domain watermarking, Least Significant bit substitution.
Performance Analysis of Digital Watermarking Of Video in the Spatial Domain
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1. Swamy.TN, Rashmi. KM, Dr.P.Cyril Prasanna Raj, Dr.S.L.Pinjare / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1244-1247
FPGA Implementation Of Efficient Algorithm Of Image Splitting
For Video Streaming Data
Swamy.TN*, Rashmi. KM**, Dr.P.Cyril Prasanna Raj ***, Dr.S.L.Pinjare
****
*(Assistant Prof, Rajiv Gandhi Institute of Technology, Bangalore)
** (Assistant Prof, SDMIT, Ujire, Mangalore)
***(Director, NXG semiconductor Technologies, Bangalore)
****(PG coordinator, Nitte Meenakshi Institute of Technology, Bangalore)
ABSTRACT
Video splitting is the process of dividing it can be processed as a steady and continuous
the video into non overlapping parts. Then row stream over the network. With streaming the client
mean and column mean or each part is obtained. browser or plug in can start displaying the
After applying transform on these, features sets multimedia data before the entire file has been
can be obtained to be used in image retrieval. By transmitted.
using splitting higher precision and recall can be
obtained. Streaming refers to transferring video
data such that it can be processed as a steady and
continuous stream over the network. With
streaming the client browser or plug in can start
displaying the multimedia data before the entire
file has been transmitted. In this paper original
image of particular size is split into blocks. Each
block is enlarged to the original dimension
without blurring. Enlarged image is displayed on
the big screen. This can be done on video
streaming data. Designs are implemented using
Xilinx and Mat lab tools and Xilinx Vertex-2p
FPGA board.
Keywords– Croma, interpolation, luma,
simulink, system generator.
I. INTRODUCTION Fig1. Original image and splitted image
1.1 Video splitting
Video splitting is the process of dividing 1.2 Interpolation
the video into non overlapping parts. Then row The goal of interpolation is to produce the
mean and column mean of each part is obtained. acceptable images at different resolution from a
After applying transform on these, feature sets can single low resolution image. The actual resolution of
be obtained to be used in image retrieval. By using the image is defined as the number of pixels. Image
splitting higher precision and recall can be obtained. interpolation is a basic tool used extensively in
Natural images are captured using image sensors in zooming, shrinking, rotating and geometric
the form of voltage intensities that are digitized and corrections. Interpolation is the process of using
stored in memory banks. Large storage space is known data to estimate values of unknown
required to store and process these digital samples locations, suppose that an image of size 500*500
[1]. For example, a color image of size 256*256 pixels has to be enlarged 1.5 times to 750*750
represented using 24-bit requires a storage space of pixels. A simple way to visualize zooming is to
47 Mega bits. Similarly the storage space for a three create an imaginary 750*750 grid with the same
hour movie requires 92000 Giga bits. pixel spacing as the original, and then shrink it so
Processing and transmission of huge image that if fits exactly over the original image.
data is time consuming and very cumbersome. Obviously, the pixel spacing in the shrunken
Hence the project has a major application in all 750*750 grid will be less than the pixel spacing in
areas of image processing. Fig1 shows original and the original image [2]. To perform intensity-level
spitted non overlapping parts respectively. assignment for any point in the overlay, we look for
Streaming refers to transferring video data such that its closest pixel in the original image and assign the
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2. Swamy.TN, Rashmi. KM, Dr.P.Cyril Prasanna Raj, Dr.S.L.Pinjare / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1244-1247
intensity of that pixel to the new pixel in the
750*750 grid. When we are finished assigning
intensities to all the points in the overlay grid, we
expand it to the original size to obtain the zoomed
image. This method is called nearest neighbor
interpolation because it assigns to each new location
the intensity of its nearest neighbor. The basic
criteria for a good interpolation method are
geometric invariance, contrast invariance, noise,
edge preservation, aliasing, texture preservation,
over smoothing, application awareness, and
sensitivity to parameters [3].
Fig3. Image matrix to serial format
II. DESIGN
The block diagram of the design is shown The conversion of serial data into matrix
in Fig2. Video from a web camera at 30 frames per format is shown in Fig4. The hardware design using
second is applied to the video input block. Resize the system generator is shown in Fig5.
block enlarge or shrinks image size. Captured video
will be in RGB format. Input video is converted into
croma and luma components.
Luma represents the brightness in an image
and it represents the achromatic image without any
color while the croma component represents the
color information. Image split block splits the image
into number of blocks. Each spitted block is resized
using bicubic interpolation technique. The split
image is displayed using the video display output
block.
Fig4. Image serial to parallel conversion
Video Resize RGB to
input 256*256 YCrCb
Splitting
Video Resize YCbCr to
output 256*256 RGB
Fig5. System generator model
Fig2. Block diagram of image splitting
III. PARAMETERS
The design is implemented using simulink and 3.1 Video input block
system generator [3][4] environment. 3.1.1 Device
Image will be in matrix format. It has to be Device describes the image acquisition
converted into serial data before applying into the device to which we want to connect. The items in
system generator block. The design for converting the drop down list of device vary depending on
matrix to serial format is as shown in Fig3. which devices we have connected to the system. All
Transpose block is used to convert M*N video capture devices supported by image
matrix into N*M matrix. The block named convert acquisition toolbox are supported by the block.
2D to 1D block reshapes an M*N matrix into a 1D
vector with length M*N. Frame conversion block 3.1.2 Video format.
specifies the frame status of the output signal. The Video format shows the video formats
unbuffer block unbuffers frame based input into supported by the selected device. The drop down list
sample based output. of video format varies with each device. If the
device supports the use of camera files, from camera
file will be one of the choices in the list.
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3. Swamy.TN, Rashmi. KM, Dr.P.Cyril Prasanna Raj, Dr.S.L.Pinjare / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1244-1247
The input image/video is splitted into four blocks of
3.1.3 Block sample time. dimension 128*128 each as shown in Fig7.
It specify the sample time of the block
during the simulation. This is the rate at which the
block is executed during simulation. The default is
1/30.
3.1.4 Ports model.
It is used to specify either a single output
port for all color spaces, or one part for each band
(for example R, G, B). When you select one
multidimensional signal, the output signal will be
combined into one line consisting of signal
information for all color signals. Select separated
color signals if you want to use three ports Fig7. Splitted image(128*128*3)
corresponding to the uncompressed red, green, and
blue color bands. These splitted images are interpolated to the original
dimension of the input, i.e. 256*256. Bicubic
3.1.5 Data type interpolation is used to resize the splitted image into
Image data type when the block outputs the original dimension. The resized image is of good
frames. This data type indicated how image frames quality because it resembles almost the resolution of
are output from the block to simulink. It supports all the original image. The interpolated images are
Matlab data types and single is the default. shown in Fig8.
3.2 Color space conversion
The color space conversion block converts
color information between color spaces. Conversion
parameter is used to specify the color spaces we are
converting. Conversion between RGB and YCbCr
and vice-versa are defined by the following
Equation (1).
(1)
Fig8. Interpolated image(256*256*3)
IV. RESULTS
4.1 Simulink output 4.2 Hardware output
The input image is in RGB format and of size The RGB image of dimension 128*128*3
256*256*3 shown in Fig6. is considered as input image as shown in Fig9.
Fig9. Input image for hardware(128*128*3)
Fig6. Original image 256*256*3 The image is resized to 128*128 and converted into
gray image as shown in Fig10.
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4. Swamy.TN, Rashmi. KM, Dr.P.Cyril Prasanna Raj, Dr.S.L.Pinjare / International Journal of
Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 2, Issue 5, September- October 2012, pp.1244-1247
DSP with xilinx system generator for
Matlab, processdings of 35th south eastern
symposium, Vol 15, page 2226-2238, 2006
[1] [5]Akhtar. P and Azhar. F, A single image
interpolation scheme for enchanced super
resolution in Bio-Medical Imaging, 4th
International Conference on Bio-
informatics and Bio medical Engineering,
pages 1-5, June 2010.
Fig10. Gray image(128*128) [6] Fatma T. Arslan and Artyom M.
Grigoryan, Method of image enhancement
The output on the FPGA hardware is as shown in by splitting signal, IEEE international
Fig11. Conference on Acoustics, speech and
signal processing, vol 4, page iv/177 -
iv/180, March 2005
[7] Rafael C. Gonzalez and Richard E. Woods,
Digital Image Processing, Pearson Prentice
Hall, 3 Edition, 2008.
[8] Samir Palnitkar, Verilog HDL a Guide to
Digital Design and Synthesis, Pearson
Education, 2 Edition, 2009.
Fig11. Hardware output image(128*128)
V. CONCLUSION
This paper is very useful in displaying
wider images for commercial purposes in
Aerodromes and railway stations. And can be
widely used in medical fields. In medical field
doctor can easily indentify the affected area by
zooming that part without zooming entire image.
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gap between FPGAs and ASICS, IEEE
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[2] Marco Aurelio,Nunu maganda, Real time
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and FPGAs, 2005
[3] T.Saidani, D. Dia, W. Elhamzi, M. Atri,
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