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Features of VLSI:
Compactness.
Speed of access.
Ease of maintenance.
Cost effective.
Life of the product.
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Gordon Moore’s (in 1965) said that transistors on a
chip would double every year.
He then recalibrated it to every two years in 1975.
 David House, an Intel executive at the time, noted
that the changes would cause computer performance
to double every18 months for a foreseeable future.
MOORE’S LAW:
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DIGITAL DESIGN FLOW:
 RTL Coding
 synthesis
 Floor planning
 Placement
 Clock routing
 Routing
 Physical verification
Front end
(Logical design)
Back end
(physical design)
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Programming Languages
 VHDL
 VERILOG HDL
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RAM:
RAM is our working memory storage. All the data, which the PC
uses and works with during operation, are stored here. Data are stored on
drives, typically the hard drive. However, for the CPU to work with those
data, they must be read into the working memory storage, which is made
up of RAM chips.
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RAM access time is in nanoseconds,
Hard disk access time is in milliseconds.
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If reset is switched high
Output is set to ‘0’.
If is in write mode
The i/p is assigned to write pointer of RAM.
If is in write mode
The read pointer of RAM is assigned to o/p.
Program Logic:
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If value of read pointer and write pointer is same then it is
defined to be empty.
If write location is 31 locations next to read [3:0] then it is
defined to be full.
Program Logic:
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If both read mode and write mode are switched high and
both pointers specify same location then we need send an
error message.
Program Logic:
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Technical schematic of RAM :
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Mnr

  • 1.
  • 2.
    Page 2 Features ofVLSI: Compactness. Speed of access. Ease of maintenance. Cost effective. Life of the product.
  • 3.
    Page 3 Gordon Moore’s(in 1965) said that transistors on a chip would double every year. He then recalibrated it to every two years in 1975.  David House, an Intel executive at the time, noted that the changes would cause computer performance to double every18 months for a foreseeable future. MOORE’S LAW:
  • 4.
    Page 4 DIGITAL DESIGNFLOW:  RTL Coding  synthesis  Floor planning  Placement  Clock routing  Routing  Physical verification Front end (Logical design) Back end (physical design)
  • 5.
  • 6.
  • 7.
    Page 7 RAM: RAM isour working memory storage. All the data, which the PC uses and works with during operation, are stored here. Data are stored on drives, typically the hard drive. However, for the CPU to work with those data, they must be read into the working memory storage, which is made up of RAM chips.
  • 8.
    Page 8 RAM accesstime is in nanoseconds, Hard disk access time is in milliseconds.
  • 9.
    Page 9 If resetis switched high Output is set to ‘0’. If is in write mode The i/p is assigned to write pointer of RAM. If is in write mode The read pointer of RAM is assigned to o/p. Program Logic:
  • 10.
    Page 10 If valueof read pointer and write pointer is same then it is defined to be empty. If write location is 31 locations next to read [3:0] then it is defined to be full. Program Logic:
  • 11.
    Page 11 If bothread mode and write mode are switched high and both pointers specify same location then we need send an error message. Program Logic:
  • 12.
  • 13.