This document describes a proposed LUT optimization technique for memory-based computation. The authors aim to design an APC-OMS combined LUT structure to efficiently perform the multiplication of a W-bit fixed coefficient A with a 5-bit input X. This would reduce the size of the LUT to one-fourth that of a conventional design by applying a modified form of the Address Pre-Computation (APC) and Orthogonal Matching Search (OMS) techniques. A block diagram and benefits are presented, showing the combined approach can cut the area-delay product over 30% for 16-bit widths and 50% for 32-bit widths compared to conventional signed-digit multipliers.

1. LUT Optimization for
Memory-Based Computation
By
N.Tharun Kumar
S.Vijay
CH.John Williams
Guided By:
Tara Sai Kumar

2. Objective:
To design LUT optimization for memory based
computation.
Design of APC-OMS combined LUT design for
the multiplication of W-bit fixed coefficient A
with 5-bit input X.

3. Abstract:
We have APC and OMS techniques for lookup
table .
These techniques reduce LUT size by a factor
two.
The modified APC and OMS ,combine
approach provides reduction in LUT size to
one by fourth of conventional.

4. Introduction:
LUT optimization is a technique used in:
Digital Signal Processing
Multiplication and Data Selection Process.
It is used to decrease size and the memory
required with the LUT without degrading its
performance.

5. APC for LUT Optimization
Modified OMS for LUT Optimization

6. Conventional LUT-based multiplier

7. Tools
Xilinx
VHDL

8. Proposed:
 A different form of APC and combined that
with a modified form of the OMS scheme for
efficient memory based multiplication.

9. Block Diagram:

10. Benefits
APC and OMS techniques reduce LUT by a
factor of 2.
Size of LUT is reduced to one by fourth of the
conventional.
For 16-bit and 32-bit word sizes, respectively,
it offers more than 30% and 50% of saving in
area-delay product over the corresponding
CSD multipliers.

11. Thank You