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MIPI DevCon 2016: How to Use the VESA Display Stream Compression (DSC) Standard to Create Higher Resolution Displays
The document outlines how to use the VESA Display Stream Compression (DSC) standard to improve resolution in consumer electronics, detailing the necessity for DSC, its applications, and integration into semiconductor designs. It explains that DSC provides visually lossless compression, reducing power, cost, and area for devices while supporting high-resolution outputs. Additionally, the document covers various use cases for DSC, including mobile, automotive, AR/VR, and high-definition video transmission.
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Overview of VESA Display Stream Compression (DSC) and its agenda for integration in electronics.
Introduction to DSC and its necessity evident in modern display technologies influencing mobile, automotive, and computing.
Display technology trends showing rising resolutions (from WXGA to 8K) with bandwidth requirements and compression trade-offs.
Details on DSC algorithm and testing methodologies focusing on compression efficiency and image quality.
DSC facilitates power savings, reduces area and costs through efficient data transport in display systems.
Overview of transport standards supporting DSC and products like Qualcomm’s Snapdragon that utilize it.
Utilization of DSC in various consumer electronics applications including mobile devices, automotive infotainment, and professional video transport.
Guidelines for integrating DSC in semiconductor design including encoder and decoder specifications.
Contact details for Alain Legault at Hardent Inc. for further discussion on DSC integration.
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MIPI DevCon 2016: How to Use the VESA Display Stream Compression (DSC) Standard to Create Higher Resolution Displays
- 1. VESA Display Stream Compression (DSC) Howto Use the VESA Display Stream Compression (DSC) Standard to Create Higher Resolution Displays for Consumer Electronics Applications Alain Legault, Hardent, Inc.
- 2. Agenda • What IsDSC? • DSC in Consumer Electronics Applications • How To Integrate DSC In Your Next Semiconductor Design
- 3. PART 1: WHAT ISDSC?
- 4. Why Is DSCNeeded? Mobile applica+on processor MIPI DSI DDIC Computer GPU card DisplayPort cable Computer monitor Car applica+on processor Proprietary transport Car infotainment display Processor TX Port Display Module RX Port To Display Video In
- 5. 2011 2012 2013 2014 2015 2016 WXGA HD FHD QHD UHD 5K Mind the Gap PHY trend +20%/year PHY per Lane Gb/s Display resolution CAGR >2x / year MPixels 1.0 2.0 3.0 4.0 5.0 Source: Dale Stolitzka & David Hoffman Samsung Display Company 1 4 4 4 1 2 1 0 8 6 4 2 0
- 6. Compression Power &Area Trade-off SWEET SPOT 2x – 3x compression Source: Dale Stolitzka & David Hoffman Samsung Display Company
- 7. Increase In AvailableBandwidth Time PHY Speed Bit Coding (8b/10b ! 128b/ 132b) Image Coding Link Speed T = 0 1x 1x 1x 1x T + 2 years 1.44x 1,23x 2x – 3x 3.5 – 5x PHY Bit Coding (if applicable) Image Coding Pixel Data Link Payload
- 8. PHY Speed /Display Resolution ResoluYon FHD (1080x1920) WQHD (1440x2560) WQXGA (1600x2560) UHD (2160x3840) WQUXGA (2400x3840) 5K (2880x5120) 8K (4320x8192) Bandwidth 3.58Gbps 6.37Gbps 7.08Gbps 14.33Gbps 15.93Gbps 25.49Gbps 61.16Gbps No compression 3 lanes 6 or 8 lanes 6 or 8 lanes N/A N/A N/A N/A 2x compression 2 lanes 3 lanes 3 lanes 8 or 6 lanes 8 or 6 lanes N/A N/A 3x compression 1 lane 2 lanes 2 lanes 4 lanes 4 lanes 8 lanes N/A D-PHY v1.1 1.5 Gbps / lane ResoluYon FHD (1080x1920) WQHD (1440x2560) WQXGA (1600x2560) UHD (2160x3840) WQUXGA (2400x3840) 5K (2880x5120) 8K (4320x8192) Bandwidth 3.58Gbps 6.37Gbps 7.08Gbps 14.33Gbps 15.93Gbps 25.49Gbps 61.16Gbps No compression 2 lanes 3 lanes 3 lanes 8 or 6 lanes 8 lanes N/A N/A 2x compression 1 lane 2 lanes 2 lanes 3 lanes 4 lanes 8 or 6 lanes N/A 3x compression 1 lane 1 lane 1 lane 2 lanes 3 lanes 4 lanes N/A D-PHY v1.2 2.5 Gbps / lane
- 9.
- 10. VESA DSC TaskGroup - 2013
- 11. VESA DSC TaskGroup: Work Completed • Call for proposals in the industry • Six proposals were presented • Selection committee • Reviewed proposals • Conducted video quality tests using various types of content (images, text, and graphics) • Broadcom BDC algorithm was chosen • Liaison committee with the MIPI Alliance • Several image quality test iterations and algorithmic improvements • DSC C-model golden reference code • Version 31 was released
- 12.
- 13. VESA DSC TaskGroup - 2016
- 14. Overview of DSCAlgorithm
- 15. Overview of DSCAlgorithm • Intra-frame Constant Bit Rate (CBR) encoder • Based on Delta Pulse Code Modulation (DPCM) • Mid Point (MPP), Block Predictor (BP) • Modified Median Adaptive Predictor (MMAP) • Indexed Color History (ICH) • Requires a single line of pixel storage + rate buffer • Visually lossless compression between 2X – 3X • Video quality excellent with all types of content • Natural and test images, text and graphics
- 16. Subjective Testing EvaluatesImage Quality ISO/IEC IS 29170-2 test method Ref Test Ref Test Ref Test Ref vs. 5Hz Source: Dale Stolitzka & David Hoffman Samsung Display Company
- 17. Objective Metrics DoNot Predict Performance Mean response fractionMean response fraction log10(HDRVDP2) PSNR PSNR = peak signal to noise ratio HDR VDP2 = high dynamic range visual difference predictor #2 Visually lossless Barely perceptible Impaired Source: Dale Stolitzka & David Hoffman Samsung Display Company
- 18. Subjective Testing Guidelines E= 30 pixels/degree (PPD)5⁰ Source: Dale Stolitzka & David Hoffman Samsung Display Company ISO/IEC IS 29170-2 Display Conditions ISO 3664, ISO 9241-303 Monitor Calibrated monitor Color sRGB, BT.709, BT.2010 Viewing Distance Distance at 30 PPD EvaluaYon procedure for nearly lossless coding Image Viewing 1:1 side/side or interleaved Image Sets Wide set of images, graphics, text and engineered images Video Sets SVT fairytale and game screen captures ISO/IEC IS 29170-2 Evalua+on procedure for nearly lossless coding
- 19.
- 20. DSC Helps SavePower, Area, and Cost MIPI DSI Transport Lanes DSC Encoder MIPI DSI Tx ApplicaYon Processor MIPI DSI Tx MIPI DSI Rx MIPI DSI Rx DSC Decoder SDRAM Display Driver IC Frame Buffer SDRAM SDRAM
- 21. DSC Helps SavePower, Area, and Cost MIPI DSI Transport Lanes DSC Encoder MIPI DSI Tx ApplicaYon Processor MIPI DSI Tx MIPI DSI Rx MIPI DSI Rx DSC Decoder SDRAM Display Driver IC Frame Buffer SDRAM SDRAM Remove MIPI Tx + PHY MIPI Rx + PHY
- 22. DSC Helps SavePower, Area, and Cost MIPI DSI Transport Lanes DSC Encoder MIPI DSI Tx ApplicaYon Processor MIPI DSI Tx MIPI DSI Rx MIPI DSI Rx DSC Decoder SDRAM Display Driver IC Frame Buffer SDRAM Remove SDRAMs SDRAM
- 23. DSC Helps SavePower, Area, and Cost MIPI DSI Transport Lanes DSC Encoder MIPI DSI Tx ApplicaYon Processor MIPI DSI Rx DSC Decoder Display Driver IC Frame Buffer SDRAM Less power Smaller footprint Lower cost
- 24. Transport Standards UsingDSC MIPI® DSI 1.2 eDisplayPort™ 1.4b DisplayPort™ 1.4
- 25. DSC Standard Availabilityand Support Source: VESA
- 26. Products Using DSC Qualcomm Snapdragon 820 NVIDIA Tegra X1
- 27. PART 2: DSC INCONSUMER ELECTRONICS APPLICATIONS
- 28. DSC Decoder Display Driver IC MIPI DSI Transport Lanes ApplicaYon Processor MIPI DSI and D-PHY MIPI DSI and D-PHY DSC Encoder GPU Use Case: Mobileand Tablet Applications • Application processor • DDIC (Display Driver IC) and touch panel controller High-DefiniYon Display Source: MIPI Alliance
- 29. Use Case: In-carVideo Applications • Application processor • Infotainment display module • Video cameras • HDMI sources • Ability to transport multiple video sources simultaneously • Automotive serial interfaces and transport DISPLAY Display I /F MIPI DSI Enet I/F IP Decap Disp Ctlr DSC Dec Telematic Hub Hub Infotainment Hub HubHub Hub Sensor I /F MIPI I3C IP Encap Enet I/F SENSOR Camera I /F MIPI CSI Enet I/F IP Encap ISP DSC Enc CAMERA
- 30. Use Case: AR/ VR Head-Mounted Display • Video capture • Application processor and GPU • Micro-display driver IC SDRAMSDRAMSDRAM Shared Memory Bus APU/GPU DSC Encoder DSC Decoder Capture System DSC Encoder DMA Ctrl MIPI CSI MIPI CSI µDisplay L µDisplay R LPDDR ISP ISP DMA Ctrl DMA Ctrl µDisplay Driver DSC Decoder DMA Ctrl MIPI DSI MIPI DSI Display Controller Display Controller
- 31. Use Case: USBType-C Laptop & Extended Display (1) • USB Type-C triple use • Peripheral • DisplayPort (Alt Mode) • Power delivery • Shared bandwidth • Ex. Dual external monitors USB type-C DP 1.4 transport • Storage • Networking • DSC usage saves bandwidth for other external devices (storage, networking) DisplayPort Alt-Mode for USB Type-C Image source: Cadence
- 32. Use Case: USBType-C Laptop & Extended Display (2) • Laptop with GPU • Dual external monitors • USB Type C DisplayPort 1.4 transport Peripheral (Storage , etc) Peripheral (Storage, etc) Internal Display CPU GPU DP Tx DSC Encoder eDP Tx USB-CEthernet WIFI I/F Display Driver IC eDP Rx Display Driver IC SDRAMSDRAMSDRAM DP Rx DSC Decoder Display 4K @ 60Hz External Monitor #1 USB/DP I/F USB Hub DDR Ctrl Laptop Single USB Type-C Connector Display Driver IC DP Rx DSC Decoder Display 4K @ 60Hz External Monitor #2 Peripheral (Storage, etc) USB-C Peripheral (Storage, etc) USB-C
- 33. Use Case: ProfessionalVideo Transport • Compression of UHD signals allows transport over inexpensive Ethernet links • Ex. UHD (14.33Gbps) over 10GE with 2:1 compression Encoder System DSC Encoder Video Interface IP Encapsulation Video Input Uncompressed Video Ethermet I/F Video Ouput Uncompressed Video Decoder System DSC Decoder Video Interface IP Decapsulation Ethermet I/F
- 34. Use Case: 8KDigital TV • TVs, STBs, and DVRs • Multimedia SoC processor • TCON (Timing controller) • Inside 8K TV • Based on DSC 1.2 Ethernet DISPLAY 8K @ 60Hz TCON IC Multimedia SoC DDR Controller Audio CPU GPU H.264/5 Video/Audio Decoder DTV Tuner I/F eDP Tx DSC Encoder Ethernet I/F WIFI I/F eDP Rx DSC Decoder RF USB-Type C or DisplayPort 1.4 Over USB-C Alt Mode 4x 10Gb/s lanes S/PDIF USB-C TS DeMUX DP Rx DSC Decoder SDRAMSDRAMSDRAM HDMI HDMI
- 35. PART 3: HOW TOINTEGRATE DSC IN YOUR NEXT SEMICONDUCTOR DESIGN
- 36. DSC Encoder andDecoder IP DSC Encoder DSC Decoder
- 37. How Are ImagesProcessed by DSC? 1 VerYcal Slice 2 VerYcal Slices 4 VerYcal Slices
- 38. Use Case: TwoVertical Slices • Example: 4K video 60 fps • ASIC with pixel clock at 350 MHz • Each slice = 350 Mpixels / sec • Two vertical slices are needed • Number of slices need to match between DSC Encoder and Decoder DSC Encoder DSC Decoder
- 39. Single DSC –Single DSI Stream Solution 1600 x 2560 x 60 fps 7 Gbps
- 40. Dual DSC –Dual DSI Stream Solution 2400 x 3860 x 60 fps 16 Gbps
- 41. Conformance Test Guideline(CTG) Uncompressed Source Picture Compressed Picture Reconstructed Display Picture DSC Encoder DSC Decoder CRC Uncompressed Source Picture CRC Compressed Picture CRC Reconstructed Pixel Stream
- 42.
- 43. Further Reading • DSCwhite paper • http://www.vesa.org/wp-content/uploads/2014/04/VESA_DSC- ETP200.pdf • DSC standard • http://www.vesa.org/vesa-standards/ • VESA membership • http://www.vesa.org/join-vesamemberships/
- 44.