In this presentation, Lalan Mishra and Satwant Singh, leaders of the MIPI Reduced Input/Output Working Group, provide an overview of MIPI VGI. MIPI VGI aims to consolidate these sideband GPIOs and low-speed messaging over a 2- or 3-wire interface using a low-complexity finite state machine (FSM) which takes select I/Os from the SOC’s GPIO map and serializes them over the VGI link. This serialization essentially virtualizes the GPIOs inside the SOC I/O map. Since the VGI FSM interacts with the GPIO map, the CPU software sees no difference between a virtualized GPIO versus a real GPIO. The VGI protocol allows I/O and message data sent in a distinctive way. Thus, MIPI VGI is a simple yet power concept, essential to addressing I/O reduction in the next generation of mobile-handheld products.

1. Mobile System
Sideband GPIO
Minimization and
Secondary IPC
Messaging Using MIPI
VGI (Virtual GPIO
Interface)
Lalan Mishra, Qualcomm Technologies, Inc.
Satwant Singh, Lattice Semiconductor

2. Agenda
• The Problem Statement
• Virtual GPIO Interface (VGI): Concept
• MIPI VGI Architecture
• Application Scenarios
• Summary
• Q&A
2

3. Mobile Connectivity Expansion Trends
3
Cellular
! 2G/3G/4G " LTE-Advanced
WiFi
! 802.11a/b/g/n/ac " 802.11ad/
WiGig
Video
! VGA/SD/HD " 4K
Docking
! Charging/audio/video "
Productivity, Games and External
Storage

4. The Problem of Sideband Proliferation
4

5. The Problem of Sideband Proliferation
5
Domain
Number of
Sideband I/O
Camera/Imaging 6 to 12
Audio CODEC 4 to 7
Cellular Modem 3 to 10
Wireless LAN
Modem
3 to 10
Bridge Chip 3 to 8
Sensor Hub 4 to 18
Typical Sideband U9liza9on
Typical Sideband GPIOs: 23 to 65

6. VGI : Solution to Sideband Proliferation
6

7. MIPI VGI : The Concept
7
• MIPI VGI consolidates N-
sideband GPIOs and sub-100
MHz serial messaging over 2 or
3 wire interface in a Point-to-
Point configuration
• 2-wire VGI : Asynchronous, Full-
Duplex
• 3-wire VGI : Synchronous, Full-
Duplex
• VGI Rev-1 Max Speed:
38.4MHz
SB
GPIOs
Tx # Rx
Virtual GPIO Interface(VGI)
$ Consolidates Low Speed Messaging Interface and
and Sideband GPIOs (N-pins to 2/3-pins reduction)
LS Msg
SB
GPIOs
VGI VGI
Dev-1
Rx % Tx
Clock
(Opt.)
N
Sideband
GPIOs
Dev-2
Dev-1 Dev-2

8. Limitation of Conventional Techniques
$ HLOS processing latency varies widely
$ Deep-sleep to acWve-state typical latency : Typically # 30 to 100-mS
$ Timing uncertainty not suitable for the key IPC side-band signaling
e.g., I2C, UART, SPI

9. VGI Architectural Block-Diagram

10. VGI Physical Interface
VGI
Device#1
VGI
Device#2
Tx # Rx
Rx % Tx
CLK
1
2
Asynchronous VGI
! Initial and Power State Transition mode communication over 2-wire
1
2
Synchronous VGI
! Common clock (Up to 38.4 MHz in VGI Rev-1)
! Sleep clock based operation supported in Low Power Modes

11. VGI Techniques At-a-Glance

12. VGI Init Sequence

13. Synchronous 3-Wire VGI

14. Asynchronous UART Mode
B
H/W Flow Control over Tx/Rx eliminates RTS/CTS physical pins

15. Asynchronous UART Mode
Variable-Frame Length
A

16. Asynch. VGI : Phase-Modulated PWM

17. VGI Protocol – 1 of 3
• Addresses P2P VGI link requirements only
• Only 2-bitsrequired as function bits. A 3rd function bit used during link length
programming.

18. VGI Protocol – 2 of 3
• Addresses P2P and P2MP links.
• No provision for error-detection and correction capability.

19. VGI Protocol – 3 of 3
• Uses 10-bits (maximum) in the Function-bit-field
• First two function bits are used for operation mode setting
• The remaining 8-bits (Mode “10” ) are Extended Hamming (8,4) coded 8-bit code words defining unique
functions
• Provides option for easy expansion to add new functions
Add clarity in terms of the
FuncWon header

20. 10-bit Function Header

21. VGI Network Illustration

22. VGI FSM Integration with MIPI I3C
• VGI FSM could be integrated
with a serial interface of
choice, such as MIPI I3C
• I3C supports MIPI VGI
integration through command
code support
• Helps reduce Hardware event
pins at system level

23. VGI FSM Integration with MIPI I3C
• HW Event sideband signals are
eliminated
• VGI-FSM (Finite State
Machine) performs I3C
message encoding/decoding
for HW events and thus frees
up the associated CPU on the
host-SoC for these tasks.
• Impact is reduced Latency and
Power consumption.

24. Comparing VGI
Courtesy: John Oakley

25. Comparing VGI with Low Speed I/F
• SPI
• Master-Slave approach
• Custom implementations, no common methods
• MIPI I3C
• Master-Multi Slave, Open-Drain approach
• In-band interrupts
• MIPI RFFE
• Master-Multi Slave approach
• UART
• Custom implementations, requires reference clocks
• MIPI VGI
• Symmetric control approach (No Master No Slave)
• Initialization from either side
Courtesy: John Oakley

26. VGI Clocking Comparison
• UART
• Requires Reference Clock with Agreed rates
• SPI, MIPI I3C, MIPI RFFE
• Clock is forwarded from Master to Slave
• MIPI VGI
• Using RO-PWM PHY option, the clocking is forwarded with data
• Only Transmitter requires clock to create telegrams
• Receiving side captures telegrams without internal clock
• Useful for devices which power down
• Useful for very simple write-only devices (LED bank)
Courtesy: John Oakley

27. Phased VGI Adoption – Leveraging Smaller
FPGAs

28. Summary
! Sideband GPIOs add to SoC and PCB level cost and complexity
! MIPI VGI Architecture consolidates sideband GPIOs and Low-
Speed serial interface in P2P configuration to reduce I/O pins
! Both 2 and 3-wire interface options are available
! Common start-up mode ensures interoperability
! The VGI FSM can be combined with any other interface bus of
choice, e.g. I3C_VGI
! The MIPI VGI Specification is to be released later this year