MICROPROCESSORS AND ITS APPLICATIONS UNIT-I.ppt

MC932-MICROPROCESSORS
AND ITS APPLICATIONS
Course teach by
P.Karthikeyan.,MTech
Asst Professor-3
VCET,Madurai
1
Dept of ECE,VCET Madurai

Objective of the course
• Understand the Microprocessor architecture
and assembly language programming flow for
the development and debugging in embedded
applications like mobile, set top box and
navigation in high level languages.
• Understand the basics for the hardware
protocols like UART,PCI and USB for the
application development in embedded systems.
2

UNIT-I
THE 8086 PROCESSOR -
SOFTWARE ASPECTS
3

Evolution of Microprocessors
4

8086 MP Overview
• Intel 8086 Microprocessors are the basis of all
IBM-PC compatible computers
(8086 introduced in 1978, first IBM-PC released in 1981)
• All Intel, AMD and other advanced
microprocessors are based on and are
compatible with the original 8086.
• At Power Up and Reset time, Pentiums,
Athlons etc all look like 8086 processors.
5

8086 Architecture Overview
• Intel 8086 is a 16b microprocessor:
– 16b data registers, 16b ALU
• Width of external data bus:
– 8086: 16b
• Width of external address bus: 16b+4b=20b
• Segment: Offset memory model
• Little-Endian Data Format
• The 8086 used an instruction queue to speed up
performance
• While the processor is decoding and executing an
instruction, its bus interface can be reading new
instructions, since at that time the bus is not actually in use
6

8086 Architecture
7

Basic Internal Architecture Of 8086
• The 8086 make use of this idle time by pre-fetching the
next instruction while the current instruction is being
executed.
• Here the bus is always busy.
• The 8086 contains two internal units; the execution unit
(EU) and the bus interface unit (BIU).
• The BIU is responsible for fetching an instruction or the
operand of an instruction from the memory.
• The EU is responsible for executing the instructions.
• The 8086 both are able to utilize the bus with maximum
efficiency because both contain internal memory in the form of
a queue.
• The 8086 queue is 2 bytes wide and three locations deep. It is
therefore able to hold three 16-bit numbers.
8

Bus Interface Unit (BIU)
• The BIU contains a prefetch queue, a bus controller,
segment registers and the instruction pointer.
• The main purposes of the BIU are:
1. To keep the prefetch queue filled with instructions.
2. To generate and accept the control signals.
3. To provide the system with a memory address or I/O port
number.
4. To act as a window between the EU and memory for
data.
9

Bus Interface Unit (BIU)
• Instruction Queue: the next instructions or data can be fetched from
memory while the processor is executing the current instruction
– The memory interface is slower than the processor execution
time so this speeds up overall performance
• Segment Registers:
– CS, DS, SS and ES are 16b registers
– Used with the 16b Base registers to generate the 20b address
– Allow the 8086 to address 1MB of memory
• Instruction Pointer (IP) contains the Offset Address of the next
instruction, the distance in bytes from the address given by the
current CS register
10

Execution Unit (EU)
• The purpose of the EU is to carry out instructions that are
fetched from the prefetch queue.
• It contains; an Arithmetic and Logic Unit(ALU), an
instruction register, and a register array.
• The ALU performs arithmetic and logic operations on
memory and or register data.
• The instruction register receives the instructions from the
prefetch queue. From here these instructions are decoded to
direct the operation of the execution unit.
• The register array holds information temporarily. It also
contains pointers or index registers used to address operand
data located in the memory.
11

System Architecture
• Three types of buses are
 Address Bus
 Data Bus
 Control Bus
• The address bus provides the memory address to the system memory
and also I/O addresses to the I/O devices. The 8086 has a 20-bit
address bus.
• The data bus transfers data between the microprocessor and the
memory and I/O attached to the system. The 8086 has a16-bit data
bus.
• The control bus provides control signals that cause the memory or
I/O to perform a READ or WRITE operation. It consists of three
signals RD, WR and IO/M.
• The 8086 having address of 1M bytes of memory because they both
contain a 20-bit address bus.
12

8086/8088 Register File
CS
DS
SS
ES
AH
BH
CH
DH
AL
BL
CL
DL
IP
SP
BP
SI
DI
0
7
0
15
0
7
0
15
Accumulator
Base
Counter
Data
Code Segment
Data Segment
Stack Segment
Extra Segment
Instruction Pointer
Stack Pointer
Base Pointer
Source Index
Destination Index
}
}
}
AX
BX
CX
DX
13

8086/8088 Register File (cont)
Flags Register
x x x x OF DF IF TF SF ZF x AF x PF x CF
0
15
Status and Control Bits Maintained in Flags Register
– Generally Set and Tested Individually
– Nine 1-bit flags in 8086; Seven are unused
14

Flags Register
• Carry Flag (CF) - this flag is set to 1 when there is an unsigned overflow.
When there is no overflow this flag is set to 0.
• Parity Flag (PF) - this flag is set to 1 when there is even number of one bits
in result, and 0 when there is odd number of one bits.
• Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow for low
nibble (4 bits).
• Zero Flag (ZF) - set to 1 when result is zero. For non-zero result this flag is
set to 0.
• Sign Flag (SF) - set to 1 when result is negative. When result is positive it
is set to 0. (This flag takes the value of the most significant bit.)
• Trap Flag (TF) - Used for on-chip debugging.
• Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to
interrupts from external devices.
• Direction Flag (DF) - this flag is used by some instructions to process data
chains, when this flag is set to 0 - the processing is done forward, when this
flag is set to 1 the processing is done backward.
• Overflow Flag (OF) - set to 1 when there is a signed overflow.
15

Status Flags
CF Carry Flag Arithmetic Carry/Borrow
OF Overflow Flag Arithmetic Overflow
ZF Zero Flag Zero Result; Equal Compare
SF Sign Flag Negative Result; Non-Equal Compare
PF Parity Flag Even Number of “1” bits
AF Auxiliary Carry Used with BCD Arithmetic
Indicate Current Processor Status
16

Control Flags
DF Direction Flag Auto-Increment/Decrement
– used for “string operations”
IF Interrupt Flag Enables Interrupts
– allows “fetch-execute” to be interrupted
TF Trap Flag Allows Single-Step
– for debugging; causes interrupt after each op
Influence the 8086 During Execution Phase
17

8086/8088 Register File (cont)
0
15
IP Contains Address of NEXT Instruction to be Fetched
– Automatically Incremented
– Programmer can control with jump and branch
Instruction Pointer Register
18

AX, BX, CX, DX
• Can Be Used Separately as 1-byte Registers
AX = AH:AL
• Temporary Storage to Avoid Memory Access
– Faster Execution
– Avoids Memory Access
• Some Special uses for Certain Instructions
AH
BH
CH
DH
AL
BL
CL
DL
0
7 0
7
Accumulator
Base
Counter
Data
General Purpose Registers
AX
BX
CX
DX
19

AX, BX, CX, DX - Some Specialized Uses
AX, Accumulator
Main Register for Performing Arithmetic
mult/div must use AH, AL
“accumulator” Means Register with Simple ALU
BX, Base
Point to Translation Table in Memory
Holds Memory Offsets; Function Calls
CX, Counter
Index Counter for Loop Control
DX, Data
After Integer Division Execution - Holds Remainder
AH
BH
CH
DH
AL
BL
CL
DL
0
7 0
7
Accumulator
Base
Counter
Data
AX
BX
CX
DX
20

CS, DS, ES, SS - Segment Registers
CS, Code Segment
Used to “point” to Instructions
Determines a Memory Address (along with IP)
Segmented Address written as CS:IP
DS, Data Segment
Used to “point” to Data
Determines Memory Address (along with other registers)
ES, Extra Segment allows to Data Address Registers
SS, Stack Segment
Used to “point” to Data in Stack Structure (LIFO)
Used with SP or BP
SS:SP or SS:BP are valid Segmented Addresses
Contains “Base Value” for Memory Address
21

IP, SP, BP, SI, DI - Offset Registers
IP, Instruction Pointer
Used to “point” to Instructions
Determines a Memory Address (along with CS)
Segmented Address written as CS:IP
SI, Source Index; DI, Destination Index
Used to “point” to Data
Determines Memory Address (along with other registers)
DS, ES commonly used
SP, Stack Pointer;BP, Base Pointer
Used to “point” to Data in Stack Structure (LIFO)
Used with SS
SS:SP or SS:BP are valid Segmented Addresses
These can also be used as General Registers !!!!!!
Contains “Index Value” for Memory Address
22

Memory Segmentation
• x86 Memory Partitioned into Segments
 8086: maximum size is 64K (16-bit index reg.)
 8086: can have 4 active segments (CS, SS, DS, ES)
 8086: 2-data; 1-code; 1-stack
• Why have segmented memory ?
– Other microprocessors could only address 64K since
they only had a single 16-bit MAR (or smaller).
Segments allowed computers to be built that could use
more than 64K memory (but not all at the same time).
23

ADD
Memory System
Address Lines
0000
Index Reg. Segment Reg.
Physical Address
0
0
0
15
15
19
Portion of BIU Circuitry
CS
ES
SS
DS
IP
Dedicated Segment Registers
Dedicated Index Registers
BP
DI
SI
SP
8086 Generating Physical Addresses
24

8086 20-bit Addresses
16-bit Segnment Base Address 0000
16-bit Offset Address
20-bit Physical Address
CS
IP
25

Segmented Addressing
CS
ES
SS
DS
IP
BP
DI
SI
SP
• Each Segment must begin at Paragraph Boundary
00000h
00010h
00020h
physical address memory
paragraph 1
paragraph 2
paragraph 3
• Each paragraph has phys. address that is multiple of 10h
• BIU is responsible for appending 0000 to Segment
– only need 16-bit segment registers
26

Segmented Memory (x86 Style)
CS
ES
SS
DS
Data
Segment
Stack
Segment
Extra
Segment
Code
Segment
Segment
Registers
System
Memory
• Segment Registers:
– Point to Base Address
• Index Registers:
– Contain Offset Value
• Notation (Segmented Address):
– CS:IP
– DS:SI
– ES:DI
– SS:BP
– SS:SP
00000h
FFFFFh
fragmentation
27

Segmented Memory Example
CS
ES
SS
DS
Data
Segment
Stack
Segment
Extra
Segment
Code
Segment
Segment
Registers
System
Memory
• Logical, Segmented Address:
0FE6:012Bh
• Offset, Index Address:
012Bh
• Physical Address:
0FE60h  65120
+ 012Bh  299
0FF8Bh  65149
00000h
FFFFFh
28

Segment Locations in Physical Memory
segment a segment b
segment c
segment d
segment e
0h 10000h 20000h 30000h
continuous
partially overlapped fully overlapped
Logical
Segments
Physical
Memory
Note that segments can overlap. This means that two different logical
addresses can refer to the same physical address (aliasing).
29

The offset is the distance in bytes from the start of the segment.
The offset is given by the IP for the Code Segment.
Instructions are always fetched with using the CS register.
The physical address is also called the absolute address
000000H
Memory
Segment Register
Offset
Physical or
Absolute Address
0
+
CS:
IP
0400H
0056H
4000H
4056H
0400
0056
04056H
CS:IP = 400:56
Logical Address
0FFFFFH
Left-shift 4 bits
The Code Segment
30

The Data Segment
Data is usually fetched with respect to the DS register.
The effective address (EA) is the offset.
The EA depends on the addressing mode.
Memory
Segment Register
Offset
Physical Address
+
DS:
EA
05C0
0050
05C00H
05C50H
05C0 0
0050
05C50H
DS:EA
000000
H
0FFFFFH
31

Addressing Modes
DATA1 DW 25H DATA1 is defined as a word (16-bit) variable, i.e., a
memory location that contains 25H.
DATA2 EQU 20H DATA2 is not a memory location but a constant.
Direct Addressing
MOV AX,DATA1 [DATA1]  AX, the contents of DATA1 is put into AX.
The CPU goes to memory to get data. 25H is put in AX.
Immediate Addressing
MOV AX,DATA2 DATA2 = 20H  AX, 20H is put in AX.
Does not go to memory to get data.
Data is in the instruction.
MOV AX, OFFSET DATA1
The assembler knows which mode to encode by the way the operands SAM and
FRED are defined.
Assembler directive, DW = Define Word
32

Addressing Modes
Register Addressing MOV AX,BX AX BX
Register Indirect Addressing MOV AX,[BX] AX DS:BX
Can use BX or BP -- Based Addressing (BP defaults to SS)
or DI or SI -- Indexed Addressing
The offset or effective address (EA) is in the base or index register.
Register Indirect with Displacement MOV AX,SAM[BX]
AX DS:BX + Offset SAM
Indexed with displacement
Based with displacement
Based-Indexed Addressing MOV AX,[BX][SI] EA = BX + SI
Based-Indexed w/Displacement MOV AX,SAM[BX][DI]
EA = BX + DI + offset SAM
AX DS:EA
where EA = BX + offset SAM
33

Addressing Modes
Branch Related Instructions
Intrasegment
(CS does not change)
Direct -- IP relative displacement
new IP = old IP + displacement
Allows program relocation with
no change in code.
Indirect -- new IP is in memory or a register.
All addressing modes apply.
Intersegment Direct -- new CS and IP are encoded in
(CS changes) the instruction.
Indirect -- new CS and IP are in memory.
All addressing modes apply
except immediate and register.
NEAR JUMPS and CALLS
FAR
34

Assembly Language
The Assembler is a program that reads the source program as
data and translates the instructions into binary machine code.
The assembler outputs a listing of the addresses and machine
code along with the
source code and a binary file (object file) with the machine code.
Most assemblers scan the source code twice -- called a two-pass
assembler.
• The first pass determines the locations of the labels or
identifiers.
• The second pass generates the code.
35

Assembly Language
To locate the labels, the assembler has a location counter.
This counts the number of bytes required by each instruction.
• When the program starts a segment, the location counter is
zero.
• If a previous segment is re-entered, the counter resumes the
count.
• The location counter can be set to any offset by the ORG
directive.
In the first pass, the assembler uses the location counter to
construct a symbol table which contains the offsets or values of the
various labels.
The offsets are used in the second pass to generate operand
addresses.
36

INSTRUCTION SET OF 8086
8086 instructions are categorized as
1)Data Copy/Transfer Instructions
2)Arithmetic and Logical Instructions
3)Branch Instructions
4)Loop Instructions
5)Machine Control Instructions
6)Flag Manipulation Instructions
7)Shift and Rotate Instructions
8)String Instructions
37

PUSH,POP,IN,OUT,XLAT,LAHF,SAHF
• PUSH -Push to Stack(Push operation decrements SP by
two and then stores the two byte contents of the operand on to
the stack)
• POP -Pop from Stack(The stack pointer incremented by
two. Popping register contents from stack memory)
• PUSHF -Push Flags
• POPF -Pop Flags
• IN -Input from Fixed Port/Variable port
• OUT -Output to Fixed Port/Variable port
• XLAT -Translate Byte to AL
• LAHF -Load AH with Flags
• SAHF -Store AH with Flags
41

Compare
• Compares the source operand(reg,imme data,mem loc)
with a destination operand(reg or mem loc).
• Comparison, it subtracts the source operand from the
destination operand.
• Both operands are equal zero flag is set. If the source
operand is greater than the destination operand, carry flag
is set or else carry flag is reset.
Examble
CMP BX,0100H Immediate
CMP [5000H],0100H Direct
CMP BX,[SI] Register indirect
CMP BX,CX Register
49

STRING MANIPULATION INSTRUCTIONS
• REP Repeat Instruction Prefix
• MOVSB/MOVSW Move String Byte or String Word
• CMPS Compare String Byte or String Word
• SCAS Scan String Byte or String Word
• LODS Load String Byte or String Word
• STOS Store String Byte or String Word
60

Unconditional Branch Instructions
• CALL Unconditional Call
• RET Return from the Procedure
• INT N Interrupt Type N
• INTO Interrupt on Overflow
• JMP Unconditional Jump
• IRET Return from ISR
• LOOP Loop Unconditionally
61

Conditional Jumps
Name/Alt Meaning Flag setting
JE/JZ Jump equal/zero ZF = 1
JNE/JNZ Jump not equal/zero ZF = 0
JL/JNGE Jump less than/not greater than or = (SF xor OF) = 1
JNL/JGE Jump not less than/greater than or = (SF xor OF) = 0
JG/JNLE Jump greater than/not less than or = ((SF xor OF) or ZF) = 0
JNG/JLE Jump not greater than/ less than or = ((SF xor OF) or ZF) = 1
JB/JNAE Jump below/not above or equal CF = 1
JNB/JAE Jump not below/above or equal CF = 0
JA/JNBE Jump above/not below or equal (CF or ZF) = 0
JNA/JBE Jump not above/ below or equal (CF or ZF) = 1
JS Jump on sign (jump negative) SF = 1
JNS Jump on not sign (jump positive) SF = 0
JO Jump on overflow OF = 1
JNO Jump on no overflow OF = 0
JP/JPE Jump parity/parity even PF = 1
JNP/JPO Jump no parity/parity odd PF = 0
JCXZ Jump on CX = 0 ---
62

Flag Manipulation
CLC - Clear carry flag
CMC - Complement carry flag
STC - Set carry flag
CLD - Clear direction flag
STD - Set direction flag
CLI - Clear interrupt flag
STI - Set interrupt flag
Processor Control Instructions
WAIT - Wait for Test input pin to go low
HLT - Halt the Processor
NOP - No operation
ESC - Escape to external device like
NDP(numeric co-processor)
LOCK - Bus lock instruction prefix
63

Assembler Directives
ASSUME Tells the assembler what segments to use.
SEGMENT Defines the segment name and specifies that the
code that follows is in that segment
ORG Originate or Origin: sets the location counter
END End of source code
ENDS End of segment
ENDP End of Procedure
NAME Give source module a name
OFFSET Offset of a label
DW Define word
DB Define byte
DQ Define Quad word
DT Define Ten Bytes
64

Assembler Directives
EQU Equate or equivalence
EVEN Align or Even memory address
EXTRN External
PUBLIC Public
GROUP Group the related segments
LABEL Assign current location count to a symbol
LENGTH Byte Length of a Label
LOCAL Lables,variables,constants or procedures declared
LOCAL in module
$ Current location count
PROC Procedure
PTR Pointer(FAR PTR,NEAR PTR)
SEG Segment of a Label
SHORT,TYPE,GLOBAL, “+&-”Operators
65

66
Interrupts
• Interrupt Types
– Hardware Interrupts: External event
– Software Interrupts: Internal event (Software
generated)
– Maskable and non-maskable interrupts
– Interrupt priority
• Interrupt Vectors and Interrupt Handlers
• Interrupt Controllers

67
The Purpose of Interrupts
• Interrupts are useful when interfacing I/O devices with low data-
transfer rates, like a keyboard or a mouse, in which case polling the
device wastes valuable processing time
• The peripheral interrupts the normal application execution,
requesting to send or receive data.
• The processor jumps to a special program called Interrupt Service
Routine to service the peripheral
• After the processor services the peripheral, the execution of the
interrupted program continues.
Printer Interrupt Modem Interrupt Modem Interrupt
Main Program
Main Program
Main Program
Main Program

BASIC INTERRUPT TERMINOLOGY
• Interrupt pins: Set of pins used in hardware interrupts
• Interrupt Service Routine (ISR) or Interrupt handler: code used
for handling a specific interrupt
• Interrupt priority: In systems with more than one interrupt
inputs, some interrupts have a higher priority than other
– They are serviced first if multiple interrupts are triggered
simultaneously
• Interrupt vector: Code loaded on the bus by the interrupting
device that contains the Address (segment and offset) of specific
interrupt service routine
• Interrupt Masking: Ignoring (disabling) an interrupt
• Non-Maskable Interrupt: Interrupt that cannot be ignored
(power-down)

Hardware Interrupts – Interrupt pins and timing
• x86 Interrupt Pins
– INTR: Interrupt Request. Activated by a peripheral device to interrupt the processor.
• Level triggered. Activated with a logic 1.
– /INTA: Interrupt Acknowledge. Activated by the processor to inform the interrupting
device the the interrupt request (INTR) is accepted.
• Level triggered. Activated with a logic 0.
– NMI: Non-Maskable Interrupt. Used for major system faults such as parity errors and
power failures.
• Edge triggered. Activated with a positive edge (0 to 1) transition.
• Must remain at logic 1, until it is accepted by the processor.
• Before the 0 to 1 transition, NMI must be at logic 0 for at least 2 clock cycles.
• No need for interrupt acknowledgement.
Vector
INTR
INTA΄
D7-D0

Software Interrupts
• Traps: (self-interrupt!)
– Single step mode
– Calls to Operating System (INT 21H - x86, SC –
PPC)
• Exceptions:
– Divide by zero
– Memory protection fault

Identifying Interrupt Source
• Software Polling,
– Checking each device
• Hardware Polling, (Daisy Chain),
• Hardware Identification (Vectored Interrupts).

Interrupt Processing
• Save state
– Disable interrupts for the duration of the ISR or allow it
to be interrupted too?
– Save program counter
– Save flags
– Save register values?
• Jump to interrupt service routine
– Location obtained by interrupt vector
• Process interrupt
• Restore state
– Load PC, flags, registers etc.

Interrupt Processing on the 8086
Microprocessor
• External interface sends an interrupt signal, to the Interrupt
Request (INTR) pin, (or an internal interrupt occurs.)
• The CPU finishes the present instruction (for a hardware
interrupt) and checks the INTR pin.
• If IF=0 the processor ignores the interrupt, else sends
Interrupt Acknowledge (INTA) to hardware interface.
• The interrupt type N is sent to the Central Processor Unit
(CPU) via the Data bus from the hardware interface.
• The contents of the flag registers are pushed onto the stack.

• Both the interrupt (IF – FR bit 9) and (TF – FR bit 8) flags are
cleared. This disables the INTR pin and the trap or single-step
feature.
• The contents of the code segment register (CS) are pushed onto the
Stack.
• The contents of the instruction pointer (IP) are pushed onto the
Stack.
• The interrupt vector contents are fetched, from (4 x N) and then
placed into the IP and from (4 x N +2) into the CS so that the next
instruction executes at the interrupt service procedure addressed by
the interrupt vector.
• While returning from the interrupt-service routine by the Interrupt
Return (IRET) instruction, the IP, CS and Flag registers are popped
from the Stack and return to their state prior to the interrupt.
Interrupt Processing on the 8086
Microprocessor
74

Interrupt Vectors
• The processor uses the interrupt vector to determine the address of
the ISR of the interrupting device.
• In the 8088/8086 processor as well as in the 80386/80486/Pentium
processors operating in Real Mode (16-bit operation), the interrupt
vector is a pointer to the Interrupt Vector Table.
– The Interrupt Vector Table occupies the address range from
00000H to 003FFH (the first 1024 bytes in the memory map).
– Each entry in the Interrupt Vector Table is 4 bytes long:
• The first two represent the offset address and the last two the
segment address of the ISR.
– The first 5 vectors are reserved by Intel to be used by the
processor.
• The vectors 5 to 255 are free to be used by the user.

Dept of ECE,VCET Madurai 76
Interrupt Vector Table
Type 0 POINTER
(DIVIDE ERROR)
Type 1 POINTER
(SINGLE STEP)
Type 2 POINTER
(NON-MASKABLE)
Type 3 POINTER
(BREAK POINT)
Type 4 POINTER
(OVERFLOW)
010H
00CH
008H
004H
000H
16 bits
CS base address
IP offset

03FFH
Type 5
Reserved
Type 31 (Reserved)
Type 32 (Available)
03FCH
080H
07FH
0014H
Reserved
Interrupts
(27)
Type 255 (Available)
Available
Interrupts
(224)

Setting up an Interrupt-Pointer Table
• The first 1 KB of memory is set aside as a table
for storing the starting addresses of ISRs
– these are addresses 00000H to 003FFH
– you need 4 bytes to store the CS and IP values for each
ISR
– thus the table can hold the addresses for 256 ISRs
• Terms
– Interrupt vector/pointer - the starting address of an ISR
– Interrupt vector/pointer table - the table containing the
starting addresses of the ISRs
78

Interrupt Vector Table
INT Number Physical Address
INT 00 00000
INT 01 00004
INT 02 00008
: :
: :
INT FF 003FC

Dedicated Interrupts
• Type 0 to Type 4 interrupts are dedicated to
specific interrupts
• Type 5 to Type 31 interrupts are reserved by
Intel for more complex microprocessors
• Type 32 to Type 255 interrupts can be user
specified for dealing with hardware or software
interrupts

Type 0 Interrupt Example
• Type 0 specifies a divide by zero interrupt
– Recall DIV instruction
• whenever a quotient from DIV or IDIV
operation is too large to fit in the result
register, a type 0 interrupt happens
automatically
• It’s up to the programmer to handle this interrupt
– one possible is to set a programmer-defined
error flag…BAD_DIV_FLAG

Initialization List
• Initialize the interrupt-vector table
– use the ES register
– the starting address of our type 0 ISR needs to
be in locations 00000H and 00002H
• Set up the data segment
– include a declaration for the BAD_DIV_FLAG
– Initialize DS
• Set up a stack
– Initialize SS and SP

Single-Step Interrupt - Type 1
• If the TF (trap flag) is set, a type 1 interrupt will
automatically occur
• To implement single-stepping, such as in a
debugger:
– set the trap flag
– write an ISR that saves all registers on the
stack, so they can be examined
– load the address of the ISR into the addresses
00004H and 00006H

Nonmaskable Interrupt - Type 2
• Type 2 interrupt automatically occurs when the
CPU receives a low-to-high transition on its NMI
pin
• this type of interrupt cannot be masked by any
program instructions
• normally used to signal that some external
system/device must be taken care of
– pressure sensor on a large steam boiler
– save data in case of a power failure

Breakpoint Interrupt -Type 3
• This type of interrupt is produced by executing an
INT 3 instruction
– no automatic triggers
• Useful for debugging
– many debuggers implement breakpoints by
inserting an INT 3 instruction before the
specified instruction
– the Type 3 ISR may then store all the registers
so that they can be examined by the user

Overflow Interrupt - Type 4
• This type of interrupt may be produced if
the OF (Overflow flag) is set… but not
automatically triggered
• OF will be set if the signed result of an
arithmetic operation on 2 signed numbers is
too large to be represented in the destination
– 01101100 (108 decimal) + 01010001 (81 decimal),
remember that these are signed!

Overflow Interrupt (cont.)
• Can handle OF error using a JO instruction
following arithmetic operation
• Can also use the INTO instruction
– this specifies to Interrupt on Overflow
– if OF is set (1), will execute ISR contained in
the type 4 addresses in the vector table
• INTO is advantageous because you can use the
same ISR for many programs

Software Interrupts
• How do I test out my ISR that handles a
type 2 interrupt without directly signaling
the NMI pin?
– Use a software interrupt
INT 2 ; test out NMI ISR
• You can specify values 0 - 255 (decimal) as
operands to the INT instruction

INTR Interrupts
• These are hardware interrupts
• can be disabled by clearing IF
CLI ; disable interrupts
• can be enabled by setting IF
STI ; enable interrupts
• The interrupt type is sent to the 8086 from an
external hardware device
– could be an 8259A priority interrupt controller
• Remember, IF is automatically cleared in response
to any type of 8086 interrupt

Why Disable INTR Interrupts?
Reason #1
– To prevent an INTR
interrupt from interrupting
a higher priority interrupt
– Interrupt priorities
• Highest - Divide
Error, INT n, INTO
• Lower - NMI
• Still Lower - INTR
• Lowest - Single-Step
Reason #2
-To prevent an interrupt from
continuously interrupting itself
The INTR input is active
high…whenever INTR input is high
and IF is set, the 8086 will be
interrupted
-After IRET, flag is popped
INTR could still possibly be
receiving the same high signal and
cause another interrupt
it is the responsibility of the
external hardware sending the
INTR signal to avoid this
problem

MICROPROCESSORS AND ITS APPLICATIONS UNIT-I.ppt

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