The document provides an overview of microprocessors and microcontrollers. It discusses why they are needed in modern devices and some key components like the CPU, memory, I/O ports, and timers. The document then compares microprocessors and microcontrollers, noting that microcontrollers have these components integrated onto a single chip, making them well-suited for applications where cost, power and space are priorities. It also provides details on the 8051 microcontroller, including its memory architecture, I/O ports, and special function registers.

1. By
Vijay Kumar K
Assistant Professor
Dept. of ECE
8051 by Vijay Kumar K5/20/2014
1

2. Why do we need to learn
Microprocessors/Microcontrollers?
 The microprocessor is the core of computer
systems.
 Nowadays many communication, digital
entertainment, portable devices, are controlled
by them.
 A designer should know what types of
components he needs, ways to reduce
production costs and product reliable.
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3. The necessary tools for a Microprocessor/controller
1. CPU: Central Processing Unit
2. I/O: Input /Output
3. Bus: Address bus & Data bus
4. Memory: RAM & ROM
5. Timer
6. Interrupt
7. Serial Port
8. Parallel Port
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4. Microprocessors
CPU for Computers
No RAM, ROM, I/O on CPU chip itself
Example: Intel's x86, Motorola’s 680x0
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5. What is Microcontroller?
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Micro Controller
Very Small A mechanism that controls
the operation of a machine

6. Microcontroller
 A smaller computer
 On-chip RAM, ROM, I/O ports...
 Example: Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC
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9. Microprocessor vs. Microcontroller
Microprocessor
 CPU is stand-alone, RAM,
ROM, I/O, timer are separate
 Designer can decide on the
amount of ROM, RAM and I/O
ports.
 Expansive
 Versatility
 General-purpose
Microcontroller
 CPU, RAM, ROM, I/O and
timer are all on a single chip
 Fix amount of on-chip ROM,
RAM, I/O ports
 For applications in which cost,
power and space are critical
 Not Expansive
 Single-purpose

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11. Microcontrollers for Embedded Systems
 Home
Appliances, intercom, telephones, security systems, garage
door openers, answering machines, fax machines, home
computers, TVs, cable TV tuner, VCR, camcorder, remote controls,
video games, cellular phones, musical instruments, sewing
machines, lighting control, paging, camera, pinball machines, toys,
exercise equipment etc.
 Office
Telephones, computers, security systems, fax machines, microwave,
copier, laser printer, color printer, paging etc.
 Auto
Trip computer, engine control, air bag, ABS, instrumentation,
security system, transmission control, entertainment, climate
control, cellular phone, keyless entry

12. Choosing a Microcontroller
 8-bit microcontrollers
 Motorola’s 6811
 Intel’s 8051
 Zilog’s Z8
 Microchip’s PIC
 There are also 16-bit and 32-bit microcontrollers
made by various chip makers

13. Criteria for Choosing a Microcontroller
1.Meeting the computing needs of the task at hand
efficiently and cost effectively
Speed
Packaging
Power consumption
The amount of RAM and ROM on chip
The number of I/O pins and the timer on chip
How easy to upgrade to higher performance or lower
power-consumption versions
Cost per unit

14. 2. Availability of software development tools, such as compilers,
assemblers, and debuggers
3. Wide availability and reliable sources of the microcontroller
The 8051 family has the largest number of diversified (multiple
source) suppliers
 Intel (original)
 Atmel
 Philips/Signetics
 AMD
 Infineon (formerly Siemens)
 Dallas Semiconductor/Maxim
Criteria for Choosing a Microcontroller

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Salient Features
1. 8 bit microcontroller originally developed by Intel in 1980.
2. High-performance CMOS Technology.
3. 40 pin DIP IC
4. Address bus is of 16 bit & data bus is of 8 bit.
5. 4K bytes internal ROM (Program memory).
6. 128 bytes internal RAM (Data memory).
7. It has four 8 bit ports, total 32 I/O lines.
8. Two 16-bit timers (T0 & T1).
9. Serial interface Communication.
10. 64K external code & data memory space.

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11. 210 bit-addressable locations.
12. Internal memory consists of on-chip ROM and on-chip data RAM.
13. 8051 implements a separate memory space for programs (code) and data.
14. Operating frequency is 24MHz-33MHz and it contains On-chip clock oscillator
15. +5V Regulated DC power supply is required to operate .
16. RAM, ROM, I/O ports, one serial port and timers are all on-chip.
17. 6-interrupts (2 are external with 2 priority levels).
18. Low-power Idle and Power-down Modes.
19. Full duplex UART.
20. 8051 has 21 special function registers (SFRs).

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8051 Family
The 8051 is a subset of the 8052
The 8031 is a ROM-less 8051
 Add external ROM to it
 You lose two ports, and leave only 2 ports for I/O operations

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8051
Pin diagram:-

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XTAL2 and XTAL1 (18 and 19 pins)
The 8051 has an on-chip oscillator but requires an
external clock to run it
A quartz crystal oscillator is connected to inputs
XTAL1 (pin19) and XTAL2 (pin18)
The quartz crystal oscillator also needs two capacitors
of 30 pF value

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XTAL1 and XTAL2 …..
 If you use a frequency source other than a crystal oscillator,
such as a TTL oscillator:
 It will be connected to XTAL1
 XTAL2 is left unconnected

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XTAL1 and XTAL2 …..
 The speed of 8051 refers to the maximum oscillator
frequency connected to XTAL.
 We can observe the frequency on the XTAL2 pin using the
oscilloscope.

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RST (Pin 9)
 RESET pin is an input and is active high (normally low)
 Upon applying a high pulse to this pin, the microcontroller will
reset and terminate all activities
 This is often referred to as a power-on reset
 Activating a power-on reset will cause all values in the registers
to be lost

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 There is no on-chip ROM in 8031 and 8032 .
 The EA pin is connected to GND to indicate the
code is stored externally.
 PSEN ＆ ALE are used for external ROM.
 For 8051, EA pin is connected to Vcc.
 “ ” means active low.
EA（pin 31）：external access

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EA
EA “external access’’, is an input pin and must be connected
to Vcc or GND
The 8051 family members all come with on-chip ROM to
store programs and also have an external code and data
memory.
Normally EA pin is connected to Vcc
EA pin must be connected to GND to indicate that the code or
data is stored externally.

27. PSEN (Pin 29)
 PSEN, “program store enable’’, is an output pin
 This pin is connected to the OE pin of the external memory.
 For External Code Memory, PSEN = 0
 For External Data Memory, PSEN = 1
 Address Latch Enable
 It is an output pin and is active high.
 8051 port 0 provides both address and data.
 The ALE pin is used for de-multiplexing the address and data by
connecting to the G pin of the 74LS373 latch.
ALE（pin 30）：

28. I/O Port Pins
 The four 8-bit I/O ports P0, P1, P2 and P3 each
uses 8 pins.
 All the ports upon RESET are configured as
output, ready to be used as input ports by the
external device.

29. Port 0 Port 0 is also designated as AD0-AD7.
When connecting an 8051 to an external
memory, port 0 provides both address and
data.
The 8051 multiplexes address and data
through port 0 to save pins.
 ALE indicates if P0 has address or data.
 When ALE=0, it provides data D0-D7
 When ALE=1, it has address A0-A7

30. Port 1 and Port 2
In 8051-based systems with no external
memory connection:
 Both P1 and P2 are used as simple I/O.
In 8051-based systems with external memory
connections:
 Port 2 must be used along with P0 to provide
the 16-bit address for the external memory.
 P0 provides the lower 8 bits via A0 – A7.
 P2 is used for the upper 8 bits of the 16-bit
address, designated as A8 – A15, and it cannot
be used for I/O.

31. Port 3
 Port 3 can be used as input or output.
 Port 3 has the additional function of
providing some extremely important
signals

32. Pin Description Summary
PIN TYPE NAME AND FUNCTION
Vss I Ground: 0 V reference.
Vcc I Power Supply: This is the power supply voltage for normal,
idle, and power-down operation.
P0.0 - P0.7 I/O Port 0: Port 0 is an open-drain, bi-directional I/O port. Port
0 is also the multiplexed low-order address and data bus
during accesses to external program and data memory.
P1.0 - P1.7 I/O Port 1: Port I is an 8-bit bi-directional I/O port.
P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the
high order address byte during fetches from external
program memory and during accesses to external data
memory that use 16 bit addresses.
P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also
serves special features as explained.

33. Pin Description Summary
PIN TYPE NAME AND FUNCTION
RST I Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device.
ALE O Address Latch Enable: Output pulse for latching the low byte
of the address during an access to external memory.
PSEN O Program Store Enable: The read strobe to external program
memory. When executing code from the external program
memory, PSEN* is activated twice each machine cycle,
except that two PSEN* activations are skipped during each
access to external data memory.
EA/VPP I External Access Enable/Programming Supply Voltage: EA
must be externally held low to enable the device to fetch
code from external program memory locations. If EA* Is
held high, the device executes from internal program
memory. This pin also receives the programming supply
voltage Vpp during Flash programming. (applies for 89c5x
MCU's)

35. Detailed Block Diagram

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37. Memory Space
8051

38. 8051 Memory Structure
External
EXT INT
128
SFR
External
Program Memory Data Memory
64K 64K
EA = 0 EA = 1
4K
60K

39. Internal RAM Structure
Direct &
Indirect
Addressing
Direct
Addressing
Only
SFR [ Special Function
Registers]
128 Byte Internal RAM

40. Special Function Registers [SFR]

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A Register (Accumulator)
 Multiplication and division can be performed only upon numbers stored in the
A and B registers. All other instructions in the program can use this register as
a spare accumulator (A).
 A register is a general-purpose register used for storing
intermediate results obtained during operation
B Register

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R Registers (R0-R7)
 They occupy 4 banks within
RAM. Similar to the
accumulator, they are used for
temporary storing variables
and intermediate results
during operation. Which one
of these banks is to be active
depends on two bits of the
PSW Register. Active bank is a
bank the registers of which
are currently used.
 This is a common name for 8 general-purpose registers (R0, R1,
R2 ...R7). Even though they are not true SFRs, they deserve to be
discussed here because of their purpose.

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 Suppose it is necessary to perform some arithmetical operations
upon numbers previously stored in the R registers: (R1+R2) -
(R3+R4). Obviously, a register for temporary storing results of
addition is needed. This is how it looks in the program:
MOV A,R3; move number from R3 into accumulator
ADD A,R4; add number from R4 to accumulator (result remains in accumulator)
MOV R5,A; temporarily move the result from accumulator into R5
MOV A,R1; move number from R1 to accumulator
ADD A,R2; add number from R2 to accumulator
SUBB A,R5; subtract number from R5 (there are R3+R4)
Example:-

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DPTR register is not a true one because it doesn't physically exist. It consists of
two separate registers: DPH (Data Pointer High) and (Data Pointer Low).
For this reason it may be treated as a 16-bit register or as two independent 8-bit
registers. Their 16 bits are primarily used for external memory addressing.
Besides, the DPTR Register is usually used for storing data and intermediate
results.
Data Pointer Register (DPTR)

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Stack Pointer (SP) Register
 A value stored in the Stack Pointer points to the first
free stack address and permits stack availability.
 Stack pushes increment the value in the Stack Pointer
by 1. Likewise, stack pops decrement its value by 1.
Upon any reset and power-on, the value 7 is stored in
the Stack Pointer, which means that the space of RAM
reserved for the stack starts at this location. If another
value is written to this register, the entire Stack is
moved to the new memory location.

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P0, P1, P2, P3 - Input/output Registers
 If neither external memory nor serial communication system
are used then 4 ports with in total of 32 input/output pins are
available for connection to peripheral environment.
 Each bit within these ports affects the state and performance of
appropriate pin of the microcontroller. Thus, bit logic state is
reflected on appropriate pin as a voltage (0 or 5 V) and vice
versa, voltage on a pin reflects the state of appropriate port bit.

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As mentioned, port bit state affects performance of port
pins, i.e. whether they will be configured as inputs or
outputs.
If a bit is cleared (0), the appropriate pin will be
configured as an output, while if it is set (1), the
appropriate pin will be configured as an input.
Upon reset and power-on, all port bits are set (1), which
means that all appropriate pins will be configured as
inputs.

48. RS1 RS0 Space in RAM
0 0 Bank0 00h-07h
0 1 Bank1 08h-0Fh
1 0 Bank2 10h-17h
1 1 Bank3 18h-1Fh
Program Status Word [PSW]
C AC F0 RS1 RS0 OV F1 P
Register Bank Select
Carry
Auxiliary Carry
User Flag 0
Parity
User Flag 1
Overflow

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50. 8051 instructions that affects flag

51. 128 Byte RAM
 There are 128 bytes of RAM in the 8051.
 Assigned addresses 00 to 7FH
 The 128 bytes are divided into 3 different
groups as follows:
1. A total of 32 bytes from locations 00 to 1F
hex are set aside for register banks and
the stack.
2. A total of 16 bytes from locations 20H to
2FH are set aside for bit-addressable
read/write memory.
3. A total of 80 bytes from locations 30H to
7FH are used for read and write storage,
called scratch pad.
128 BYTE
INTERNAL RAM
Register Banks
Reg Bank 0
Reg Bank 1
Reg Bank 2
Reg Bank 3
BIT Addressable
Area
General Purpose
Area

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53. 8051 RAM with
addresses

54. 8051 Register Bank Structure
Bank 0
R0 R1 R2 R3 R4 R5 R6 R7Bank 3
R0 R1 R2 R3 R4 R5 R6 R7Bank 2
R0 R1 R2 R3 R4 R5 R6 R7Bank 1
R0 R1 R2 R3 R4 R5 R6 R7

55. 8051 Register Banks with address

56. 8051 Programming Model

57. 8051 Stack
 The stack is a section of RAM used by the CPU to store
information temporarily.
 This information could be data or an address
 The register used to access the stack is called the SP (stack
pointer) register
 The stack pointer in the 8051 is only 8 bit wide, which means
that it can take value of 00 to FFH
 When the 8051 is powered up, the SP register contains value
07
 RAM location 08 is the first location begin used for the stack
by the 8051

58. 8051 Stack
 The storing of a CPU register in the stack is called a PUSH
 SP is pointing to the last used location of the stack
 As we push data onto the stack, the SP is incremented by one
 This is different from many microprocessors
 Loading the contents of the stack back into a CPU register
is called a POP
 With every pop, the top byte of the stack is copied to the
register specified by the instruction and the stack pointer is
decremented once

59. Bit Addressable & Byte Addressable

60. Single bit Instructions

61. Bit Addressable Programming
 Example: Find out to which by each of the following bits belongs. Give
the address of the RAM byte in hex
(a) SETB 42H, (b) CLR 67H, (c) CLR 0FH (d) SETB 28H, (e) CLR 12, (f) SETB 05

62. 8051 Peripheral Overview
1. Timers
2.Serial Port
3.Interrupts

63. 8051
TIMERS

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OSC ÷12
TLx
(8 Bit)
/ 0C T 
/ 1C T 
INT PIN
Gate
TR
T PIN
THx
(8 Bit)
TFx
(1 Bit)
INTERRUPT

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GATE:
When set, timer/counter x is enabled, if INTx pin is high and TRx
is set.
When cleared, timer/counter x is enabled, if TRx bit set.
C/T:
When set, counter operation (input from Tx input pin).
When cleared, timer operation (input from internal clock).

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The TMOD byte is not bit addressable.

67. TMOD Register
The TMOD byte is not bit addressable.

68. TCON Register

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Timer 0
Mode 3
Mode 2
Mode 1
Mode 0
Mode 2
Mode 1
Mode 0
Timer 1
8051 TIMERS

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OSC ÷12
TL0
/ 0C T 
/ 1C T 
0INT PIN
Gate
0TR
0T PIN
TH0
INTERRUPT
TIMER 0
TF0

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TL0
(5 Bit)
INTERRUPT
TIMER 0 – Mode 0
OSC ÷12
/ 0C T 
/ 1C T 
0INT PIN
Gate
0TR
0T PIN
TH0
(8 Bit)
TF0
13 Bit Timer / Counter
Maximum Count = 1FFFh (0001111111111111)

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TL0
(8 Bit)
INTERRUPT
TIMER 0 – Mode 1
OSC ÷12
/ 0C T 
/ 1C T 
0INT PIN
Gate
0TR
0T PIN
TH0
(8 Bit)
TF0
16 Bit Timer / Counter
Maximum Count = FFFFh (1111111111111111)

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TH0
(8 Bit)
Reload
TIMER 0 – Mode 2
8 Bit Timer / Counter with AUTORELOAD
TL0
(8 Bit)
OSC ÷12
/ 0C T 
/ 1C T 
0INT PIN
Gate
0TR
0T PIN
TH0
(8 Bit)
TF0 INTERRUPT
Maximum Count = FFh (11111111)

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TL0
(8 Bit)
INTERRUPT
TIMER 0 – Mode 3
OSC ÷12
/ 0C T 
/ 1C T 
0INT PIN
Gate
0TR
0T PIN
TF0
Two - 8 Bit Timer / Counter
OSC ÷12
1TR
TH0
(8 Bit)
INTERRUPTTF1

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OSC ÷12
TL1
/ 0C T 
/ 1C T 
Gate
TH1
INTERRUPT
TIMER 1
TF1
1INT PIN
1TR
1T PIN

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TL1
(5 Bit)
INTERRUPT
TIMER 1 – Mode 0
OSC ÷12
/ 0C T 
/ 1C T 
Gate
TH1
(8 Bit)
TF1
13 Bit Timer / Counter
Maximum Count = 1FFFh (0001111111111111)
1INT PIN
1TR
1T PIN

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TL1
(8 Bit)
INTERRUPT
TIMER 1 – Mode 1
OSC ÷12
/ 0C T 
/ 1C T 
Gate
TH1
(8 Bit)
TF1
16 Bit Timer / Counter
Maximum Count = FFFFh (1111111111111111)
1INT PIN
1TR
1T PIN

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TH1
(8 Bit)
Reload
TIMER 1 – Mode 2
8 Bit Timer / Counter with AUTORELOAD
TL1
(8 Bit)
OSC ÷12
/ 0C T 
/ 1C T 
Gate
TH1
(8 Bit)
TF1 INTERRUPT
Maximum Count = FFh (11111111)
1INT PIN
1TR
1T PIN

79. Programming Timers
 Example: Indicate which mode and which timer are
selected for each of the following.
(a) MOV TMOD, #01H (b) MOV TMOD, #20H (c) MOV
TMOD, #12H
 Solution: We convert the value from hex to binary.
 (a) TMOD = 00000001, mode 1 of timer 0 is selected.
 (b) TMOD = 00100000, mode 2 of timer 1 is selected.
 (c) TMOD = 00010010, mode 2 of timer 0, and mode 1 of
timer 1 are selected.

80. Programming Timers
Find the timer’s clock frequency and its period for various
8051-based system, with the crystal frequency 11.0592 MHz
when C/T bit of TMOD is 0.
Solution:
1/12 × 11.0529 MHz = 921.6 MHz;
T = 1/921.6 kHz = 1.085 us

81. 8051
Serial Port

82. Basics of Serial Communication
Computers transfer data in two ways:
 Parallel: Often 8 or more lines (wire conductors) are used to
transfer data to a device that is only a few feet away.
 Serial: To transfer to a device located many meters away, the
serial method is used. The data is sent one bit at a time.

83. Basics of Serial Communication
 Serial data communication uses two methods
 Synchronous method transfers a block of data at a time
 Asynchronous method transfers a single byte at a time
 There are special IC’s made by many manufacturers for
serial communications.
 UART (universal asynchronous Receiver transmitter)
 USART (universal synchronous-asynchronous
Receiver-transmitter)

84. Asynchronous – Start & Stop Bit
 Asynchronous serial data communication is widely used
for character-oriented transmissions
 Each character is placed in between start and stop bits, this is
called framing.
 Block-oriented data transfers use the synchronous method.
 The start bit is always one bit, but the stop bit can be one or
two bits
 The start bit is always a 0 (low) and the stop bit(s) is 1
(high)

85. Asynchronous – Start & Stop Bit

86. Data Transfer Rate
The rate of data transfer in serial data communication is
stated in bps (bits per second).
Another widely used terminology for bps is baud rate.
It is modem terminology and is defined as the number of signal
changes per second
In modems, there are occasions when a single change of signal
transfers several bits of data
As far as the conductor wire is concerned, the baud rate and
bps are the same.

87. 8051 Serial Port
 Synchronous and Asynchronous
 SCON Register is used to Control
 Data Transfer through TXd & RXd pins
 Some time - Clock through TXd Pin
 Four Modes of Operation:
Mode 0 :Synchronous Serial Communication
Mode 1 :8-Bit UART with Timer Data Rate
Mode 2 :9-Bit UART with Set Data Rate
Mode 3 :9-Bit UART with Timer Data Rate

88. Registers related to Serial
Communication
1. SBUF Register
2. SCON Register
3. PCON Register

89. SBUF Register
 SBUF is an 8-bit register used solely for serial communication.
 For a byte data to be transferred via the TxD line, it must be
placed in the SBUF register.
 The moment a byte is written into SBUF, it is framed with the
start and stop bits and transferred serially via the TxD line.
 SBUF holds the byte of data when it is received by 8051 RxD
line.
 When the bits are received serially via RxD, the 8051
deframes it by eliminating the stop and start bits, making a
byte out of the data received, and then placing it in SBUF.

90. SBUF Register
 Sample Program:

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SCON Register
Set to Enable
Serial Data
reception
Enable Multiprocessor
Communication Mode
9th Data Bit
Sent in Mode 2,3
9th Data Bit
Received in Mode 2,3
Set when a
Character received
Set when Stop
bit Txed
SM0 SM1 Mode Description
0 0 0
8-bit Shift
Register
0 1 1 8-bit UART
1 0 2 9-bit UART
1 1 3 9-bit UART

92. 8051 Serial Port – Mode 0
The Serial Port in Mode-0 has the following features:
1. Serial data enters and exits through RXD
2. TXD outputs the clock
3. 8 bits are transmitted / received
4. The baud rate is fixed at (1/12) of the oscillator frequency

93. 8051 Serial Port – Mode 1
The Serial Port in Mode-1 has the following features:
1. Serial data enters through RXD
2. Serial data exits through TXD
3. On receive, the stop bit goes into RB8 in SCON
4. 10 bits are transmitted / received
1. Start bit (0)
2. Data bits (8)
3. Stop Bit (1)
5. Baud rate is determined by the Timer 1 over flow rate.

94. 8051 Serial Port – Mode 2
The Serial Port in Mode-2 has the following features:
1. Serial data enters through RXD
2. Serial data exits through TXD
3. 9th data bit (TB8) can be assign value 0 or 1
4. On receive, the 9th data bit goes into RB8 in SCON
5. 11 bits are transmitted / received
1.Start bit (0)
2.Data bits (9)
3.Stop Bit (1)
6. Baud rate is programmable

95. 8051 Serial Port – Mode 3
The Serial Port in Mode-3 has the following features:
1. Serial data enters through RXD
2. Serial data exits through TXD
3. 9th data bit (TB8) can be assign value 0 or 1
4. On receive, the 9th data bit goes into RB8 in SCON
5. 11 bits are transmitted / received
1.Start bit (0)
2.Data bits (9)
3.Stop Bit (1)
6. Baud rate is determined by Timer 1 overflow rate.

96. Programming Serial Data
Transmission1. TMOD register is loaded with the value 20H, indicating the use of
timer 1 in mode 2 (8-bit auto-reload) to set baud rate.
2. The TH1 is loaded with one of the values to set baud rate for serial
data transfer.
3. The SCON register is loaded with the value 50H, indicating serial
mode 1, where an 8- bit data is framed with start and stop bits.
4. TR1 is set to 1 to start timer 1
5. TI is cleared by CLR TI instruction
6. The character byte to be transferred serially is written into SBUF
register.
7. The TI flag bit is monitored with the use of instruction JNB TI, xx to
see if the character has been transferred completely.
8. To transfer the next byte, go to step 5

97. Programming Serial Data Reception
1. TMOD register is loaded with the value 20H, indicating the use of
timer 1 in mode 2 (8-bit auto-reload) to set baud rate.
2. TH1 is loaded to set baud rate
3. The SCON register is loaded with the value 50H, indicating serial
mode 1, where an 8- bit data is framed with start and stop bits.
4. TR1 is set to 1 to start timer 1
5. RI is cleared by CLR RI instruction
6. The RI flag bit is monitored with the use of instruction JNB RI, xx to
see if an entire character has been received yet
7. When RI is raised, SBUF has the byte, its contents are moved into a
safe place.
8. To receive the next character, go to step 5.

98. Doubling Baud Rate
 There are two ways to increase the baud rate of data
transfer
1. By using a higher frequency crystal
2. By changing a bit in the PCON register

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PCON register
PCON register is an 8-bit register.
 When 8051 is powered up, SMOD is zero
 We can set it to high by software and thereby double the baud rate.
 SMOD Baud rate is twice as much higher by setting this bit.
 GF1 General-purpose bit (available for use).
 GF0 General-purpose bit (available for use).
 PD By setting this bit the microcontroller enters the Power Down mode.
 IDL By setting this bit the microcontroller enters the Idle mode.

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101. Doubling Baud Rate (cont…)

102. 8051
Interrupts

103. INTERRUPTS
 An interrupt is an external or internal event that interrupts
the microcontroller to inform it that a device needs its service
 A single microcontroller can serve several devices by two
ways:
1. Interrupt
2. Polling

104. Interrupt Vs Polling
1. Interrupts
 Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal.
 Upon receiving an interrupt signal, the microcontroller
interrupts whatever it is doing and serves the device.
 The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.
2. Polling
 The microcontroller continuously monitors the status of a given
device.
 When the conditions met, it performs the service.
 After that, it moves on to monitor the next device until every
one is serviced.

105. Interrupt Vs Polling
 The polling method is not efficient, since it wastes much of the
microcontroller’s time by polling devices that do not need
service.
 The advantage of interrupts is that the microcontroller can
serve many devices (not all at the same time).
 Each devices can get the attention of the microcontroller
based on the assigned priority.
 For the polling method, it is not possible to assign priority
since it checks all devices in a round-robin fashion.
 The microcontroller can also ignore (mask) a device request
for service in Interrupt.

106. Steps in Executing an Interrupt
1. It finishes the instruction it is executing and saves the address of
the next instruction (PC) on the stack.
2. It also saves the current status of all the interrupts internally (i.e:
not on the stack).
3. It jumps to a fixed location in memory, called the interrupt vector
table, that holds the address of the ISR.
4. The microcontroller gets the address of the ISR from the
interrupt vector table and jumps to it.
5. It starts to execute the interrupt service subroutine until it
reaches the last instruction of the subroutine which is RETI
(return from interrupt).
6. Upon executing the RETI instruction, the microcontroller returns
to the place where it was interrupted.

107. Six Interrupts in 8051
Six interrupts are allocated as follows:
1. Reset – power-up reset.
2. Two interrupts are set aside for the timers.
 one for Timer 0 (T0) and one for Timer 1 (T1)
3. Two interrupts are set aside for hardware external
interrupts.
 P3.2 and P3.3 are for the external hardware interrupts INT0
(or EX1), and INT1 (or EX2)
4. Serial communication has a single interrupt that belongs to
both receive and transfer.

108. What events can trigger Interrupts?
 We can configure the 8051 so that any of the following events will
cause an interrupt:
 Timer 0 Overflow.
 Timer 1 Overflow.
 Reception/Transmission of Serial Character.
 External Event 0.
 External Event 1.
 We can configure the 8051 so that when Timer 0 Overflows or
when a character is sent/received, the appropriate interrupt
handler routines are called.

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110. 8051 Interrupt Vectors

111. 8051 Interrupt related Registers
 The various registers associated with the use of interrupts are:
TCON - Edge and Type bits for External Interrupts 0/1
SCON - RI and TI interrupt flags for RS232
IE - Enable interrupt sources
IP - Specify priority of interrupts

112. Enabling and Disabling an Interrupt
 Upon reset, all interrupts are disabled (masked), meaning
that none will be responded to by the microcontroller if they
are activated.
 The interrupts must be enabled by software in order for the
microcontroller to respond to them.
 There is a register called IE (interrupt enable) that is
responsible for enabling (unmasking) and disabling
(masking) the interrupts.

113. Interrupt Enable (IE) Register
EA - global interrupt enable/disable:
0 - disables all interrupt requests. 1 - enables all individual interrupt requests.
ES - enables or disables serial interrupt:
0 - UART system cannot generate an interrupt. 1 - UART system enables an interrupt.
ET1 - bit enables or disables Timer 1 interrupt:
0 - Timer 1 cannot generate an interrupt. 1 - Timer 1 enables an interrupt.
EX1 - bit enables or disables external 1 interrupt:
0 - change of the pin INT0 logic state cannot generate an interrupt.
1 - enables an external interrupt on the pin INT0 state change.
ET0 - bit enables or disables timer 0 interrupt:
0 - Timer 0 cannot generate an interrupt. 1 - enables timer 0 interrupt.
EX0 - bit enables or disables external 0 interrupt:
0 - change of the INT1 pin logic state cannot generate an interrupt.
1 - enables an external interrupt on the pin INT1 state change.

114. Enabling and Disabling an Interrupt
 Example: Show the instructions to
(a) enable the serial interrupt, timer 0 interrupt, and external hardware
interrupt 1 and
(b) disable (mask) the timer 0 interrupt, then
(c) show how to disable all the interrupts with a single instruction.
 Solution:
 (a) MOV IE,#10010110B ;enable serial, timer 0, EX1
 Another way to perform the same manipulation is:
 SETB IE.7 ;EA=1, global enable
 SETB IE.4 ;enable serial interrupt
 SETB IE.1 ;enable Timer 0 interrupt
 SETB IE.2 ;enable EX1
 (b) CLR IE.1 ;mask (disable) timer 0 interrupt only
 (c) CLR IE.7 ;disable all interrupts

115. Interrupt Priority
When the 8051 is powered up, the priorities are assigned
according to the following.
In reality, the priority scheme is nothing but an internal polling
sequence in which the 8051 polls the interrupts in the sequence
listed and responds accordingly.

116. Interrupt Priority
 We can alter the sequence of interrupt priority by
assigning a higher priority to any one of the interrupts
by programming a register called IP (interrupt
priority).
 To give a higher priority to any of the interrupts, we
make the corresponding bit in the IP register high.

117. Interrupt Priority (IP) Register
PS PT1 PX1 PT0 PX0Reserved
Serial Port
Timer 1 Pin
INT 1 Pin Timer 0 Pin
INT 0 Pin
Priority bit=1 assigns high priority
Priority bit=0 assigns low priority

118. 8051 Software Overview
1. Addressing
Modes
2.Instruction Set
3.Programming

119. 8051 Addressing Modes
The CPU can access data in various ways, which are
called addressing modes
1. Immediate Addressing Modes
2. Register Addressing Modes
3. Direct Addressing Modes
4. Register Indirect Addressing Modes
5. External Indirect Addressing Modes

120. Immediate Addressing Mode
 The source operand is a constant.
 The immediate data must be preceded by the pound sign, “#”
 Can load information into any registers, including 16-bit
DPTR register
 DPTR can also be accessed as two 8-bit registers, the high byte DPH
and low byte DPL

121. Register Addressing Mode
 Use registers to hold the data to be manipulated.
• The source and destination registers must match in size.
MOV DPTR,A will give an error
• The movement of data between Rn registers is not allowed
MOV R4,R7 is invalid

122. Direct Addressing Mode
 It is most often used the direct addressing mode to access
RAM locations 30 – 7FH.
 The entire 128 bytes of RAM can be accessed.
 Contrast this with immediate addressing mode, there is no
“#” sign in the operand.

123. SFR Registers & their Addresses
MOV 0E0H,#55H ;is the same as
MOV A,#55H ;which means load 55H into A (A=55H)
MOV 0F0H,#25H ;is the same as
MOV B,#25H ;which means load 25H into B (B=25H)
MOV 0E0H,R2 ;is the same as
MOV A,R2 ;which means copy R2 into A
MOV 0F0H,R0 ;is the same as
MOV B,R0 ;which means copy R0 into B

124. SFR Addresses ( 1 of 2 )

125. SFR Addresses ( 2 of 2 )

126. Example

127. Stack and Direct Addressing Mode
 Only direct addressing mode is allowed for pushing or popping
the stack.
 PUSH A is invalid.
 Pushing the accumulator onto the stack must be coded as PUSH
0E0H.

128. Register Indirect Addressing Mode
 A register is used as a pointer to the data.
 Only register R0 and R1 are used for this purpose.
 R2 – R7 cannot be used to hold the address of an operand
located in RAM.
 When R0 and R1 hold the addresses of RAM locations, they
must be preceded by the “@” sign.

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Write a program to copy the value 55H into RAM memory locations 40H to
41H using (a) direct addressing mode,
(b) register indirect addressing mode without a loop, and
(c) with a loop.

130. Register Indirect Addressing Mode
The advantage is that it makes accessing data dynamic rather
than static as in direct addressing mode.
Looping is not possible in direct addressing mode.
Write a program to clear 16 RAM locations starting at RAM
address 60H.

131. External Direct
 External Memory is accessed.
 There are only two commands that use External Direct
addressing mode:
 MOVX A, @DPTR
MOVX @DPTR, A
 DPTR must first be loaded with the address of external
memory.

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8051
Instruction
Set

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1. Data Transfer Instructions
2. Arithmetic Instructions
3. Branch Instructions
4. Logic Instructions
5. Bit-oriented Instructions
 Depending on operation they perform, all instructions
are divided in several groups:

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Data Transfer Instructions
Mnemonic Description
MOV A,Rn Moves the register to the accumulator
MOV A,direct Moves the direct byte to the accumulator
MOV A,@Ri Moves the indirect RAM to the accumulator
MOV A,#data Moves the immediate data to the accumulator
MOV Rn,A Moves the accumulator to the register
MOV Rn,direct Moves the direct byte to the register
MOV Rn,#data Moves the immediate data to the register
MOV direct,A Moves the accumulator to the direct byte
MOV direct,Rn Moves the register to the direct byte
MOV direct,direct Moves the direct byte to the direct byte
MOV direct,@Ri Moves the indirect RAM to the direct byte
MOV direct,#data Moves the immediate data to the direct byte
MOV @Ri,A Moves the accumulator to the indirect RAM

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135
Mnemonic Description
MOV @Ri,direct Moves the direct byte to the indirect RAM
MOV @Ri,#data Moves the immediate data to the indirect RAM
MOV DPTR,#data Moves a 16-bit data to the data pointer
MOVC A,@A+DPTR
Moves the code byte relative to the DPTR to the accumulator
(address=A+DPTR)
MOVC A,@A+PC Moves the code byte relative to the PC to the accumulator (address=A+PC)
MOVX A,@Ri Moves the external RAM (8-bit address) to the accumulator
MOVX A,@DPTR Moves the external RAM (16-bit address) to the accumulator
MOVX @Ri,A Moves the accumulator to the external RAM (8-bit address)
MOVX @DPTR,A Moves the accumulator to the external RAM (16-bit address)
PUSH direct Pushes the direct byte onto the stack
POP direct Pops the direct byte from the stack/td>
XCH A,Rn Exchanges the register with the accumulator
XCH A,direct Exchanges the direct byte with the accumulator
XCH A,@Ri Exchanges the indirect RAM with the accumulator
XCHD A,@Ri Exchanges the low-order nibble indirect RAM with the accumulator

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Mnemonic Description
ADD A,Rn Adds the register to the accumulator
ADD A,direct Adds the direct byte to the accumulator
ADD A,@Ri Adds the indirect RAM to the accumulator
ADD A,#data Adds the immediate data to the accumulator
ADDC A,Rn Adds the register to the accumulator with a carry flag
ADDC A,direct Adds the direct byte to the accumulator with a carry flag
ADDC A,@Ri Adds the indirect RAM to the accumulator with a carry flag
ADDC A,#data Adds the immediate data to the accumulator with a carry flag
SUBB A,Rn Subtracts the register from the accumulator with a borrow
SUBB A,direct Subtracts the direct byte from the accumulator with a borrow
Arithmetic Instructions

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Mnemonic Description
SUBB A,@Ri Subtracts the indirect RAM from the accumulator with a borrow
SUBB A,#data Subtracts the immediate data from the accumulator with a borrow
INC A Increments the accumulator by 1
INC Rn Increments the register by 1
INC Rx Increments the direct byte by 1
INC @Ri Increments the indirect RAM by 1
DEC A Decrements the accumulator by 1
DEC Rn Decrements the register by 1
DEC Rx Decrements the direct byte by 1
DEC @Ri Decrements the indirect RAM by 1
INC DPTR Increments the Data Pointer by 1
MUL AB Multiplies A and B
DIV AB Divides A by B
DA A Decimal adjustment of the accumulator according to BCD code

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Mnemonic Description
ACALL addr11 Absolute subroutine call
LCALL addr16 Long subroutine call
RET Returns from subroutine
RETI Returns from interrupt subroutine
AJMP addr11 Absolute jump
LJMP addr16 Long jump
SJMP rel
Short jump (from –128 to +127 locations relative to the following
instruction)
JC rel Jump if carry flag is set. Short jump.
JNC rel Jump if carry flag is not set. Short jump.
JB bit,rel Jump if direct bit is set. Short jump.
Branch Instructions

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Mnemonic Description
JBC bit,rel Jump if direct bit is set and clears bit. Short jump.
JMP @A+DPTR Jump indirect relative to the DPTR
JZ rel Jump if the accumulator is zero. Short jump.
JNZ rel Jump if the accumulator is not zero. Short jump.
CJNE A,direct,rel
Compares direct byte to the accumulator and jumps if
not equal. Short jump.
CJNE A,#data,rel
Compares immediate data to the accumulator and
jumps if not equal. Short jump.
CJNE Rn,#data,rel
Compares immediate data to the register and jumps if
not equal. Short jump.
CJNE @Ri,#data,rel
Compares immediate data to indirect register and
jumps if not equal. Short jump.
DJNZ Rn,rel Decrements register and jumps if not 0. Short jump.
DJNZ Rx,rel Decrements direct byte and jump if not 0. Short jump.
NOP No operation

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Mnemonic Description
ANL A,Rn AND register to accumulator
ANL A,direct AND direct byte to accumulator
ANL A,@Ri AND indirect RAM to accumulator
ANL A,#data AND immediate data to accumulator
ANL direct,A AND accumulator to direct byte
ANL direct,#data AND immediae data to direct register
ORL A,Rn OR register to accumulator
ORL A,direct OR direct byte to accumulator
ORL A,@Ri OR indirect RAM to accumulator
ORL direct,A OR accumulator to direct byte
ORL direct,#data OR immediate data to direct byte
Logic Instructions

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XRL A,Rn Exclusive OR register to accumulator
XRL A,direct Exclusive OR direct byte to accumulator
XRL A,@Ri Exclusive OR indirect RAM to accumulator
XRL A,#data Exclusive OR immediate data to accumulator
XRL direct,A Exclusive OR accumulator to direct byte
XORL direct,#data Exclusive OR immediate data to direct byte
CLR A Clears the accumulator
CPL A Complements the accumulator (1=0, 0=1)
SWAP A Swaps nibbles within the accumulator
RL A Rotates bits in the accumulator left
RLC A
Rotates bits in the accumulator left through
carry
RR A Rotates bits in the accumulator right
RRC A Rotates bits in the accumulator right through carry

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Mnemonic Description
CLR C Clears the carry flag
CLR bit Clears the direct bit
SETB C Sets the carry flag
SETB bit Sets the direct bit
CPL C Complements the carry flag
CPL bit Complements the direct bit
ANL C,bit AND direct bit to the carry flag
ANL C,/bit AND complements of direct bit to the carry flag
ORL C,bit OR direct bit to the carry flag
ORL C,/bit OR complements of direct bit to the carry flag
MOV C,bit Moves the direct bit to the carry flag
MOV bit,C Moves the carry flag to the direct bit
Bit-oriented Instructions

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Here is a list of the operands and their meanings:
 A - accumulator;
Rn - is one of working registers (R0-R7) in the currently active RAM memory bank;
 Direct - is any 8-bit address register of RAM. It can be any general-purpose register or a SFR (I/O
port, control register etc.);
 @Ri - is indirect internal or external RAM location addressed by register R0 or R1;
 #data - is an 8-bit constant included in instruction (0-255);
 #data16 - is a 16-bit constant included as bytes 2 and 3 in instruction (0-65535);
 addr16 - is a 16-bit address. May be anywhere within 64KB of program memory;
 addr11 - is an 11-bit address. May be within the same 2KB page of program memory as the first
byte of the following instruction;
 rel - is the address of a close memory location (from -128 to +127 relative to the first byte of the
following instruction). On the basis of it, assembler computes the value to add or subtract from the
number currently stored in the program counter;
 bit - is any bit-addressable I/O pin, control or status bit; and
 C - is carry flag of the status register (register PSW).
Description of all 8051 instructions