Synopsys Design Compiler Documents
Documents (pdf) located on Linux server in
/class/ELEC6250/Synopsys_Docs/
DC User Guide
DC Command Line
DC Synthesis Quickref
DC Ref Constraints and Timing
DC Ref Timing Optimization
DesignVisionTutorial
DesignVision User Guide
Project directory structure
/CADProjects
/MyHomeDirectory
/Project1 /Project2 /work /adk*
/src /syn /sim /schematic /layout
VHDL/Verilog
library
std cell
library
.vhd
.v
Synthesis scripts,
logs, reports,
design database,
netlists (.v, .vhd)
sdf, sdc, pow files
.do files,
simulation
results
Physical
layout files
Invoking Design Compiler
Interactive shell version:
dc_shell –f scriptFile
Most efficient and common usage is to put TCL
commands into scriptFile, including “quit” at the end
TCL = Tool Command Language
Edit and rerun scriptFile as needed
GUI version (Design Vision)
design_vision
From dc_shell: gui_start
Main advantage over dc_shell is to view the synthesized
schematic
So, you know how to deploy your code, what about your database? This talk will go through deploying your database with LiquiBase and DBDeploy a non-framework based approach to handling migrations of DDL and DML.
So, you know how to deploy your code, what about your database? This talk will go through deploying your database with LiquiBase and DBDeploy a non-framework based approach to handling migrations of DDL and DML.
sigrok: Adventures in Integrating a Power-Measurement DeviceBayLibre
Sigrok is a young and dynamically developing project aiming at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types (e.g. logic analyzers, oscilloscopes, and many more). ACME (Another Cute Measurement Equipment) by BayLibre is an initiave for an Open-Source Power Measurement Standard Solution. Sigrok has been chosen as ACME's user-space interface and has been since integrated with the project. After a brief introduction to ACME, this presentation will focus on the practical approach we took when implementing the libsigrok driver for ACME. We'll cover Sigrok's general architecture, usage of the API and its features and pitfalls, and some advices on how other companies can easily integrate their own products with sigrok - all this from a sigrok-newcomer's point-of-view.
A presentation to introduce the Lobos project made at the Bonjure group meeing on 2011/01/21. For more information on Lobos, visit the website: http://budu.github.com/lobos/
Leveraging Open Source to Manage SAN Performancebrettallison
Scope - The primary focus of this presentation is how to leverage open source software to help in managing Shared Storage performance. The storage server will be the focus with particular emphasis on ESS. This solution is a small one-off solution.
This presentation was hold at APEXConnect in Berlin 28th of April 2016.
The presentition describes how to user a source control / versioning system in combination with database oriented projects. You can see how to manage the folder structure and what types of files are versioned, including an Oracle Application Express Application.
Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL with a user community of more than 50,000 active designers.
A brief history
Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989.
Verilog was invented as simulation language. Use of Verilog for synthesis was a complete afterthought. Rumors abound that there were merger discussions between Gateway and Synopsys in the early days, where neither gave the other much chance of success..
In the late 1980's it seemed evident that designers were going to be moving away from proprietary languages like n dot, HiLo and Verilog towards the US Depatment of Defense standard H.D.L., known as the VHSIC Hardware Description Language. VHSIC it self stands for "Very High Speen Intergrated Circuit" BTW).
Perhaps due to such market pressure, Cadence Design Systems decided to open the Verilog language to the public in 1990, and thus OVI (Open Verilog International) was born. Until that time, Verilog HDL was a proprietary language, being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on Verilog simulators, including Chronologic Simulation, Frontline Design Automation, and others. The first of these came to market in 1992, and now there are mature Verilog simulators available from many sources.
As a result, the Verilog market has grown substantially. The market for Verilog related tools in 1994 was well over $75,000,000, making it the most commercially significant hardware description language on the market.
An IEEE working group was established in 1993 under the Design Automation Sub-Committee to produce the IEEE Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.
As an international standard, the Verilog market continued to grow. In 1998 the market for Verilog simulators alone was well over $150,000,000; continuing its dominance.
The IEEE working group released a revised standard in March of 2002, known as IEEE 1364-2001. Significant publication errors marred this release, and a revised version was released in 2003, known as IEEE 1364-2001 Revision C.
Tempto is a product test framework that allows developers to write and execute tests for SQL databases running on Hadoop. Individual test requirements such as data generation, HDFS file copy/storage of generated data and schema creation are expressed declaratively and are automatically fulfilled by the framework. Developers can write tests using Java (using a TestNG like paradigm and AssertJ style assertion) or by providing query files with expected results. We will show how we use it for presto product tests.
Benchto is a benchmark framework that provides an easy and manageable way to define, run and analyze macro benchmarks in clustered environment. Understanding behavior of distributed systems is hard and requires good visibility intostate of the cluster and internals of tested system. This project was developed for repeatable benchmarking ofHadoop SQL engines, most importantly Presto.
sigrok: Adventures in Integrating a Power-Measurement DeviceBayLibre
Sigrok is a young and dynamically developing project aiming at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types (e.g. logic analyzers, oscilloscopes, and many more). ACME (Another Cute Measurement Equipment) by BayLibre is an initiave for an Open-Source Power Measurement Standard Solution. Sigrok has been chosen as ACME's user-space interface and has been since integrated with the project. After a brief introduction to ACME, this presentation will focus on the practical approach we took when implementing the libsigrok driver for ACME. We'll cover Sigrok's general architecture, usage of the API and its features and pitfalls, and some advices on how other companies can easily integrate their own products with sigrok - all this from a sigrok-newcomer's point-of-view.
A presentation to introduce the Lobos project made at the Bonjure group meeing on 2011/01/21. For more information on Lobos, visit the website: http://budu.github.com/lobos/
Leveraging Open Source to Manage SAN Performancebrettallison
Scope - The primary focus of this presentation is how to leverage open source software to help in managing Shared Storage performance. The storage server will be the focus with particular emphasis on ESS. This solution is a small one-off solution.
This presentation was hold at APEXConnect in Berlin 28th of April 2016.
The presentition describes how to user a source control / versioning system in combination with database oriented projects. You can see how to manage the folder structure and what types of files are versioned, including an Oracle Application Express Application.
Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL with a user community of more than 50,000 active designers.
A brief history
Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989.
Verilog was invented as simulation language. Use of Verilog for synthesis was a complete afterthought. Rumors abound that there were merger discussions between Gateway and Synopsys in the early days, where neither gave the other much chance of success..
In the late 1980's it seemed evident that designers were going to be moving away from proprietary languages like n dot, HiLo and Verilog towards the US Depatment of Defense standard H.D.L., known as the VHSIC Hardware Description Language. VHSIC it self stands for "Very High Speen Intergrated Circuit" BTW).
Perhaps due to such market pressure, Cadence Design Systems decided to open the Verilog language to the public in 1990, and thus OVI (Open Verilog International) was born. Until that time, Verilog HDL was a proprietary language, being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on Verilog simulators, including Chronologic Simulation, Frontline Design Automation, and others. The first of these came to market in 1992, and now there are mature Verilog simulators available from many sources.
As a result, the Verilog market has grown substantially. The market for Verilog related tools in 1994 was well over $75,000,000, making it the most commercially significant hardware description language on the market.
An IEEE working group was established in 1993 under the Design Automation Sub-Committee to produce the IEEE Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.
As an international standard, the Verilog market continued to grow. In 1998 the market for Verilog simulators alone was well over $150,000,000; continuing its dominance.
The IEEE working group released a revised standard in March of 2002, known as IEEE 1364-2001. Significant publication errors marred this release, and a revised version was released in 2003, known as IEEE 1364-2001 Revision C.
Tempto is a product test framework that allows developers to write and execute tests for SQL databases running on Hadoop. Individual test requirements such as data generation, HDFS file copy/storage of generated data and schema creation are expressed declaratively and are automatically fulfilled by the framework. Developers can write tests using Java (using a TestNG like paradigm and AssertJ style assertion) or by providing query files with expected results. We will show how we use it for presto product tests.
Benchto is a benchmark framework that provides an easy and manageable way to define, run and analyze macro benchmarks in clustered environment. Understanding behavior of distributed systems is hard and requires good visibility intostate of the cluster and internals of tested system. This project was developed for repeatable benchmarking ofHadoop SQL engines, most importantly Presto.
Online aptitude test management system project report.pdfKamal Acharya
The purpose of on-line aptitude test system is to take online test in an efficient manner and no time wasting for checking the paper. The main objective of on-line aptitude test system is to efficiently evaluate the candidate thoroughly through a fully automated system that not only saves lot of time but also gives fast results. For students they give papers according to their convenience and time and there is no need of using extra thing like paper, pen etc. This can be used in educational institutions as well as in corporate world. Can be used anywhere any time as it is a web based application (user Location doesn’t matter). No restriction that examiner has to be present when the candidate takes the test.
Every time when lecturers/professors need to conduct examinations they have to sit down think about the questions and then create a whole new set of questions for each and every exam. In some cases the professor may want to give an open book online exam that is the student can take the exam any time anywhere, but the student might have to answer the questions in a limited time period. The professor may want to change the sequence of questions for every student. The problem that a student has is whenever a date for the exam is declared the student has to take it and there is no way he can take it at some other time. This project will create an interface for the examiner to create and store questions in a repository. It will also create an interface for the student to take examinations at his convenience and the questions and/or exams may be timed. Thereby creating an application which can be used by examiners and examinee’s simultaneously.
Examination System is very useful for Teachers/Professors. As in the teaching profession, you are responsible for writing question papers. In the conventional method, you write the question paper on paper, keep question papers separate from answers and all this information you have to keep in a locker to avoid unauthorized access. Using the Examination System you can create a question paper and everything will be written to a single exam file in encrypted format. You can set the General and Administrator password to avoid unauthorized access to your question paper. Every time you start the examination, the program shuffles all the questions and selects them randomly from the database, which reduces the chances of memorizing the questions.
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon
reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been
referred to as the "New Great Game." This research centres on the power struggle, considering
geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil
politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade,
pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
China is seeing significant success in commerce, pipeline politics, and gaining influence on other
governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai
Cooperation Organisation and the Belt and Road Economic Initiative.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
4. Synopsys Design Compiler Documents
Documents (pdf) located on Linux server in
/class/ELEC6250/Synopsys_Docs/
DC User Guide
DC Command Line
DC Synthesis Quickref
DC Ref Constraints and Timing
DC RefTiming Optimization
DesignVisionTutorial
DesignVision User Guide
6. Invoking Design Compiler
Interactive shell version:
dc_shell –f scriptFile
Most efficient and common usage is to put TCL
commands into scriptFile, including “quit” at the end
TCL =Tool Command Language
Edit and rerun scriptFile as needed
GUI version (DesignVision)
design_vision
From dc_shell: gui_start
Main advantage over dc_shell is to view the synthesized
schematic
7. Synthesis stages
and commands
Load tech libraries
into database
Read, analyze &
elaborate design
Define design
environment
parameters
Specify design
rules/contraints
Compile &
optimize design
(repeat as
necessary)
Generate netlist
and reports
10. Design Compiler library files
target_library : standard cell database (binary)
cell area/pins/timing data (for synthesis decisions)
synthetic_library: Synopsys DesignWare components
link_library : use during linking
Includes target and link library plus internal data (*)
symbol_library : schematic symbols
Synopsys installation includes a generic symbol
library
Define in file .synopsys_dc.setup
DC User Guide
Chapter 4
11. Setup file (8HP): .synopsys_dc.setup
set MyHome [getenv "HOME"]
set SynopsysInstall [getenv "STROOT"]
set CMOS8HP "/class/ELEC6250/cmos8hp/std_cell/v.20130404“
set search_path [list
[format "%s%s" $CMOS8HP /synopsys/typ_v150_t025]
[format "%s%s" $CMOS8HP /symbols/synopsys]
[format "%s%s" $SynopsysInstall /libraries/syn]
[format "%s%s" $SynopsysInstall /dw/sim_ver]
[format "%s%s" $SynopsysInstall /dw]]
set target_library [list PnomV1p50T025_STD_CELL_8HP_12T.db]
set synthetic_library [list dw_foundation.sldb]
set link_library [list "*" $target_library $synthetic_library]
set symbol_library [list generic.sdb]
DC reads .synopsys_dc.setup files in order:
1. Synopsys installation directory (all user projects)
2. User home directory (all projects for this user)
3. Current project directory (this project only)
12. Synopsys DesignWare Package
Predesigned components (tech-independent)
arithmetic, filters, CRC gen’s, counters, decoders, FIFOs, flip-
flop RAMs, etc.
Let DC choose a component, or instantiate directly
components chosen to implement arithmetic operators
Example DW decrementer:
module decrementer (in_A, SUM_out);
parameter width = 8;
input [width-1 : 0] in_A;
output [width-1 : 0] SUM_out;
DW01_dec #(width) U1( .A(in_A), .SUM(SUM_out));
endmodule;
13. Load design into the database
Analyze – syntax check and build database
inputVHDL and/or Verilog models
check dependencies & resolve generics/parameters
Elaborate – synthesize to generic gates and black boxes
technology-independent gates
operators (arithmetic, relational, etc.) recognized and
implemented with “black boxes” (no logic in them yet)
Read command does analyze + elaborate + pre-optimize
DC User Guide
Chapter 5
14. Analyze Command
analyze {f1.v src/f2.v “top file.v”}
Read and analyze into default memory database library “work”
List HDL files in bottom-up order – top level last
Use quotes if embedded spaces in file name: “top file.v”
Include directory if necessary: src/f2.v
Analyze command switches:
-format verilog (or vhdl) [defaultVHDL if file ext = .vhd/.vhdl or
Verilog if file ext = .v/.verilog]
-work lib_name [lib where design to be stored (default = “work”.)
Different libraries might be used for comparing designs]
Examples:
analyze {src/f1.v src/f2.vhd} (store in “work”)
analyze {src/f1.v src/f2.vhd} –work lib_version2
15. Elaborate Command
“Elaborate” a design currently in the memory database –
producing tech-independent circuit
elaborate divider [“divider” =VHDL entity/Verilog module]
Switches
-single_level [only do top level – for bottom-up design]
-architecture a1 [if other than most recently analyzed]
-work lib_name [if name other than work]
-generics { size=9 use_this=TRUE initval=“10011” }
List format is { generic=value generic=value …. }
-parameters [format same as generics]
16. Example script
#Design-specific information – create variables for use in commands
set myFiles [list ./src/top.v ./src/Muxbig.v ]
set basenameTOP
set fileFormat verilog
define_design_libWORK –path ./syn
#Design-independent: these commands need not be changed
analyze –format $fileFormat -libWORK $myFiles
elaborate $basename –libWORK –update
current_design $basename
link (link all design parts)
uniquify (make unique copies of replicated modules)
Unique for each
design -
not necessary,
but convenient
for multiple projects
Commands
using above
design
information
17. Read command
Performs both analyze and elaborate steps
Useful for single HDL file:
read_file –f verilog filename.v
Same switches as analyze and elaborate commands,
plus (optional):
-dont_elaborate {f1.vhd} – do analysis but not elaborate
18. Design environment
Technology variables affect delay calculations
Manufacturing process, temperature, voltage, fanouts, loads,
drives, wireload models
Defaults specified in the technology library
8HP technology libraries on next slide
Design environment variables can be set
Use tech library defaults if variables not set
set voltage 2.5 (volts)
set temp 40 (degrees celsius/centigrade)
set process 1 (process variation # – if available)
DC User Guide
Chapter 6
19. Available 8HP technology files
Located in: $CMOS8HP/synopsys/
Each file contains data for each library cell for a specific
operating voltage and temperature
Directory /Technology File
typ_v120_t025 / PnomV1p20T025_STD_CELL_8HP_12T.db
typ_v150_t025 / PnomV1p50T025_STD_CELL_8HP_12T.db
fast_v132_tm40 / PbcV1p32Tm40_STD_CELL_8HP_12T.db
fast_v132_tm55 / PbcV1p32Tm55_STD_CELL_8HP_12T.db
fast_v160_tm40 / PbcV1p60Tm40_STD_CELL_8HP_12T.db
fast_v160_tm55 / PbcV1p60Tm55_STD_CELL_8HP_12T.db
slow_v108_t125 / PwcV1p08T125_STD_CELL_8HP_12T.db
slow_v140_t125 / PwcV1p40T125_STD_CELL_8HP_12T.db
21. Example: define drive characteristics
• current_design top_level_design (define external input drives)
• set_drive 1.5 {I1 I2} (resistance units from library)
• current_cell sub_design2 (define input drivers for U2)
• set_driving_cell –lib_cell IV {I3} (default pin = IV output)
• set_driving_cell –lib_cell AN2 –pin Z –from_pin B {I4}
(arc from AN2 gate input B to output Z)
• set_fanout_load 4 {out1 out2} (#fanout units for output pins)
22. Wire Load Table (not available for 8HP)
Estimate effects of wire length & fanout on resistance,
capacitance and area of net
Affects switching times/delays
Precise delays known only after place and route
Function of cell sizes, fanouts, wire characteristics
Wire Load Table may be provided by vendor
Determined from analysis of previous process runs
Variables:
wire_load_library name
(lib to which designed mapped - or NIL)
wire_table name (if named table loaded)
wire_tree (best,balanced,worst, or not set)
wire_load_mode (top, segmented)
23. Setting design constraints
Design rule constraints: rules from library vendor for
proper functioning of the fabricated circuit
Must not be violated
Common constraints: transition time, fanout load, capacitance
Design optimization constraints: user-specified timing
and area optimization goals
DC tries to optimize these without violating design rules
Common constraints: timing and area
DC User Guide
Chapter 7
24. Design rule constraints
max_fanout = max #loads a net can drive
Input pins have fanout_load attribute.
(load they place on driving nets)
Output pins have max_fanout attribute.
(max load they can drive)
Example: Pin N drives loads A and B
• Pin A has fanout_load value 2.0
• Pin B has fanout_load value 3.0
• Pin N requires max_fanout ≥ 5.0 to drive A and B
Otherwise, use different cell or insert a buffer to drive the net.
Change max_fanout attribute to restrict it more than its default value
set_max_fanout 5 [object_list] (object_list is list of ports)
Other design rule constraints:
• max_transition (output pins): transition time to change logic values
• max_capacitance (output pins): sum of net and pin capacitances driven by output
N
A
B
25. Design optimization constraints
Speed
path delays (min,max)
clock specifications (period/frequency/duty)
Area
speed is primary goal
optimize area if timing constraints met
target area 0 forces small as possible
set_max_area 2000
Choose realistic constraints (within 1-10%)
avoid extra buffers/gates on loaded nets
26. Timing path types
Path delays of interest
1. Combinational: primary input to primary output (in2 -> out2)
2. Primary input to register input (in1 -> FF1/D1)
3. Clock/register output to primary output (clk -> Q2 -> out1)
4. Clock/register output to register input (clk -> Q1 -> D2)
27. Timing Constraints
Simple: specify target clock frequency
Advanced: specify globally or on specific blocks
Clock: period/frequency, pulse width, duty cycle
Input: arrival time, transition times, driver strength
Output: required time, transition times
required time – arrival time = “slack”
28. Clock specifications
Define required period/waveform for each clock
create_clock ckname –period 5
create_clock ckname –period 5 –waveform {2 4}
period=5, rise at 2, fall at 4
DC does not automatically imply clock signals
create_clock –name ckname –period 5
creates a “virtual clock” associated with a port/pin
Clock latency = delay through clock network
set_clock_latency 2.1 –rise CLK1
set_clock_latency 0.7 –source CLK1
from clock origin to clock pin
Clock uncertainty = margin of error to allow variances
set_clock_uncertainty –setup 0.2 CLK1
set_clock_uncertainty –hold 0.2 CLK1
Add 0.2 margin on either side
of clock edge to account for
variances in clock network
30. Input and output delays
Delay from clock edge through “external” logic to an
input port or internal pin.
set_input_delay 2.3 {in1 in2}
default input delay = 0
Time a signal is required at output port by external
destination before a clock edge
external circuit logic delay + external ff setup time
set_output_delay 7 –clock CLK1 [all_outputs]
default output delay = 0
31. • Arrival time from previous ckt to input pin, relative to clock.
- attribute: input_delay (default is 0)
- command: set_input_delay 3 –clock clk dpin
Input_delay 3 { data}
Input constraints
Block A input available
3 time units after clock
transition
Need Logic Cloud A delay +
FF2 setup time ≤ 7
32. • Time from clock to valid output at pin, to be used by external ckt
- attribute: output_delay
– command: set_output_delay 7 –clock CLK d1
output_delay 7 d1
d1
Output constraints
External Circuit
Example: Clock cycle = 20
External ckt flip-flop setup time = 2
External ckt logic cloud (LC B) delay = 11
Output at d1 needed by 20 – (11 + 2) = 7
D
clk
LC
B
33. Sequential circuit example
create_clock -period 20 -waveform {5 15} clka
create_clock -period 30 -waveform {10 25} clkb
set_input_delay 10.4 -clock clka in1
set_input_delay 6.4 -clock clkb -add_delay in1
set_output_delay 1.6 -clock clka -min out1
set_output_delay 4.8 -clock clka -max out1
Arrival at input pin from
previous clock edge
Setup time of output pin
from next clock edge
Required clock periods
34. Path-based commands
Path startpoint = input pin or register clock pin
Path endpoint =output pin or register data pin
Path constraint
set_max_delay –from from-list –to to-list value
to/from-list = port, pin, clock or cell names
If clock in from-list: all paths affected by that clock
If clock in to-list: all related register data pins
Register data pin: FF1 or FF1/D
Can specify –rise and/or –fall times
Can add –through P to capture paths passing through P
Can specify [all_outputs] or [all_inputs]
35. Path delay examples
Max delay requirements
set_max_delay 10 -to out1 –from Reset
set_max_delay 5.1 –from {ff1 ff2} -to {o1 o2}
set_max_delay 3 –from busA[*] –to u1/Z
set_max_delay 6 –to [all_outputs]
If no “from list”, constrain paths from all start points
set_max_delay 8 –from [all_inputs]
If no “to list”, constrain paths to all end points
Above also applies to: set_min_delay
36. Compiling the design
Compile (and optimize) the design
compile –map_effort $mapEffort1
design hierarchy preserved
map_effort = medium(default) or high
compile –ungroup_all –map_effort $mapEffort1
design “flattened” (ungrouped – all levels collapsed)
compile –incremental_mapping –map_effort $mapEffort2
work on it some more – incremental improvements
High-effort compile
compile_ultra
use on high-performance designs, tight time constraints
specify –no_autoungroup to preserve hierarchy
DC User Guide
Chapter 8
38. Additional timing report options
report_timing
-to {list of signals} Inputs/flipflop outputs to these signals
-from {list of signals} Flip-flop outputs/inputs to these signals
-through {list of pins} Paths that go through these pins
-max_paths N Number of paths to report
-loops {timing loops} Timing loops (comb. logic feedback)
39. Balancing Loads
Resolve load violations throughout the design
Fix loads after changing attributes, without rerunning optimize
Load balancing always done as part of optimize
Pays attention to OUTPUT_LOADS, OUTPUT_FANOUTS
Mostly used at boundaries of hierarchical modules
Optimize balances loads within modules
Command:
balance_loads [design-name] [-single]