PCD – Process Control Daemon is a light-weight system level process manager for Embedded-Linux based projects (consumer electronics, network devices, etc.).
PCD starts, stops and monitors all the user space processes in the system, in a synchronized manner, using a textual configuration file.
PCD recovers the system in case of errors and provides useful and detailed debug information.
Agenda:
In this talk we will present various locking mechanisms implemented in the linux kernel.
From System V locks to raw spinlocks and the RT patch.
Speaker:
Mark Veltzer - CTO of Hinbit and a senior instructor at John Bryce. Mark is also a member of the Free Source Foundation and contributes to many free projects.
https://github.com/veltzer
PCD – Process Control Daemon is a light-weight system level process manager for Embedded-Linux based projects (consumer electronics, network devices, etc.).
PCD starts, stops and monitors all the user space processes in the system, in a synchronized manner, using a textual configuration file.
PCD recovers the system in case of errors and provides useful and detailed debug information.
Agenda:
In this talk we will present various locking mechanisms implemented in the linux kernel.
From System V locks to raw spinlocks and the RT patch.
Speaker:
Mark Veltzer - CTO of Hinbit and a senior instructor at John Bryce. Mark is also a member of the Free Source Foundation and contributes to many free projects.
https://github.com/veltzer
Build a full-functioned virtual machine from scratch, when Brainfuck is used. Basic concepts about interpreter, optimizations techniques, language specialization, and platform specific tweaks.
Kernel Recipes 2017 - Understanding the Linux kernel via ftrace - Steven RostedtAnne Nicolas
Ftrace is the official tracer of the Linux kernel. It has been apart of Linux since 2.6.31, and has grown tremendously ever since. Ftrace’s name comes from its most powerful feature: function tracing. But the ftrace infrastructure is much more than that. It also encompasses the trace events that are used by perf, as well as kprobes that can dynamically add trace events that the user defines.
This talk will focus on learning how the kernel works by using the ftrace infrastructure. It will show how to see what happens within the kernel during a system call; learn how interrupts work; see how ones processes are being scheduled, and more. A quick introduction to some tools like trace-cmd and KernelShark will also be demonstrated.
Steven Rostedt, VMware
Machine Learning on Your Hand - Introduction to Tensorflow Lite PreviewModulabs
TF Dev Summit × Modulabs : Learn by Run !
Machine Learning on Your Hand - Introduction to Tensorflow Lite Preview (발표자 : 강재욱)
※ 모두의연구소 페이지 : https://www.facebook.com/lab4all/
※ 모두의연구소 커뮤니티 그룹 : https://www.facebook.com/groups/modulabs
Compare Performance-power of Arm Cortex vs RISC-V for AI applications_oct_2021Deepak Shankar
Abstract: In the Webinar, we will show you how to construct, simulate, analyze, validate, optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of ARM Cortex A53, SiFive u74, ARM Cortex A77, and other vendor cores. The system will be built around custom switches, Ingress/Egress buffers, credit flow control, AI accelerators, NoC and AMBA AXI buses with multi-level caches, DDR4 DRAM and DMA. The evaluation and optimization criteria will be task latency, dCache hit-ratio, power consumed/task and memory bandwidth. The parameters to be modified are bus topology, cache size, processor clock speed, custom arbiters, task thread allocation and changing the processor pipeline.
Selection of cores is a combination of financial and technical bias. Technical comparison of processor cores requires the understanding of the workload, task partitioning and cache-memory structure. A core must be evaluated in the context of the target application. To evaluate these selections, architecture simulation software must be fortified with a library of Intellectual property for power and timing accurate processor cores, simulator at 100 million events per second, peripherals, and all possible traffic distributions
Key Takeaways:
1. Validating architecture models using mathematical calculus and hardware traces
2. Construct custom policies, arbitrations and configure processor cores
3. Select the right combination of statistics to detect bottlenecks and optimize the architecture
4. Identify the right use of stochastic, transaction, cycle-accurate and traces to construct the model
Speaker Bio:
Alex Su is a FPGA solution architect at E-Elements Technology, Hsinchu, Taiwan. He has been an FPGA Solution Architect and Xilinx FPGA Trainer for a number of years, supporting companies, research centers and universities in China and Taiwan. Prior to that, Mr Su has worked at ARM Ltd for 5 years in technical support of Arm CPU and System IP. Alex has also been engaged with a variety of FPGA-based Hardware Emulation System and over ten years in ASIC/SoC design and verification engineer.
Deepak Shankar is the Founder of Mirabilis Design and has been involved in the architecture exploration of over 250 SoC and processors. Mr. Shankar started Mirabilis Design because of a vacuum in the systems engineering and modeling space with the focus shifting to network design and early software development. Deepak has published over 50 articles and presented at over 30 conferences in EDA, semiconductors and embedded computing. Mr. Shankar has an MBA from UC Berkeley, MS in from Clemson University and BS from Coimbatore Institute of Technology, both in Electronics and Communication.
It is the presentation file used by Jim Huang (jserv) at OSDC.tw 2009. New compiler technologies are invisible but highly integrated around our world, and we can enrich the experience via facilitating LLVM.
投影片講解視訊影片網址:
http://www.youtube.com/playlist?list=PLFL0ylDooClTaryk1IPAvDsqsFQ85-Rd1
This slide is made by the RoBoard team of DMP Electronics Inc.:
https://www.facebook.com/roboard.fans
Build a full-functioned virtual machine from scratch, when Brainfuck is used. Basic concepts about interpreter, optimizations techniques, language specialization, and platform specific tweaks.
Kernel Recipes 2017 - Understanding the Linux kernel via ftrace - Steven RostedtAnne Nicolas
Ftrace is the official tracer of the Linux kernel. It has been apart of Linux since 2.6.31, and has grown tremendously ever since. Ftrace’s name comes from its most powerful feature: function tracing. But the ftrace infrastructure is much more than that. It also encompasses the trace events that are used by perf, as well as kprobes that can dynamically add trace events that the user defines.
This talk will focus on learning how the kernel works by using the ftrace infrastructure. It will show how to see what happens within the kernel during a system call; learn how interrupts work; see how ones processes are being scheduled, and more. A quick introduction to some tools like trace-cmd and KernelShark will also be demonstrated.
Steven Rostedt, VMware
Machine Learning on Your Hand - Introduction to Tensorflow Lite PreviewModulabs
TF Dev Summit × Modulabs : Learn by Run !
Machine Learning on Your Hand - Introduction to Tensorflow Lite Preview (발표자 : 강재욱)
※ 모두의연구소 페이지 : https://www.facebook.com/lab4all/
※ 모두의연구소 커뮤니티 그룹 : https://www.facebook.com/groups/modulabs
Compare Performance-power of Arm Cortex vs RISC-V for AI applications_oct_2021Deepak Shankar
Abstract: In the Webinar, we will show you how to construct, simulate, analyze, validate, optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of ARM Cortex A53, SiFive u74, ARM Cortex A77, and other vendor cores. The system will be built around custom switches, Ingress/Egress buffers, credit flow control, AI accelerators, NoC and AMBA AXI buses with multi-level caches, DDR4 DRAM and DMA. The evaluation and optimization criteria will be task latency, dCache hit-ratio, power consumed/task and memory bandwidth. The parameters to be modified are bus topology, cache size, processor clock speed, custom arbiters, task thread allocation and changing the processor pipeline.
Selection of cores is a combination of financial and technical bias. Technical comparison of processor cores requires the understanding of the workload, task partitioning and cache-memory structure. A core must be evaluated in the context of the target application. To evaluate these selections, architecture simulation software must be fortified with a library of Intellectual property for power and timing accurate processor cores, simulator at 100 million events per second, peripherals, and all possible traffic distributions
Key Takeaways:
1. Validating architecture models using mathematical calculus and hardware traces
2. Construct custom policies, arbitrations and configure processor cores
3. Select the right combination of statistics to detect bottlenecks and optimize the architecture
4. Identify the right use of stochastic, transaction, cycle-accurate and traces to construct the model
Speaker Bio:
Alex Su is a FPGA solution architect at E-Elements Technology, Hsinchu, Taiwan. He has been an FPGA Solution Architect and Xilinx FPGA Trainer for a number of years, supporting companies, research centers and universities in China and Taiwan. Prior to that, Mr Su has worked at ARM Ltd for 5 years in technical support of Arm CPU and System IP. Alex has also been engaged with a variety of FPGA-based Hardware Emulation System and over ten years in ASIC/SoC design and verification engineer.
Deepak Shankar is the Founder of Mirabilis Design and has been involved in the architecture exploration of over 250 SoC and processors. Mr. Shankar started Mirabilis Design because of a vacuum in the systems engineering and modeling space with the focus shifting to network design and early software development. Deepak has published over 50 articles and presented at over 30 conferences in EDA, semiconductors and embedded computing. Mr. Shankar has an MBA from UC Berkeley, MS in from Clemson University and BS from Coimbatore Institute of Technology, both in Electronics and Communication.
It is the presentation file used by Jim Huang (jserv) at OSDC.tw 2009. New compiler technologies are invisible but highly integrated around our world, and we can enrich the experience via facilitating LLVM.
投影片講解視訊影片網址:
http://www.youtube.com/playlist?list=PLFL0ylDooClTaryk1IPAvDsqsFQ85-Rd1
This slide is made by the RoBoard team of DMP Electronics Inc.:
https://www.facebook.com/roboard.fans
86Duino 12自由度小六足機器人 DIY 教學
86小六足3D列印機構檔: http://www.thingiverse.com/thing:964149
86小六足原始設計檔: https://github.com/roboard/86Hexapod
This slide is made by the RoBoard team of DMP Electronics Inc.:
https://www.facebook.com/roboard.fans
投影片講解視訊影片網址:
http://www.youtube.com/playlist?list=PLFL0ylDooClTXfy-cFbq7rV1iwP57JFaF
This slide is made by the RoBoard team of DMP Electronics Inc.:
https://www.facebook.com/roboard.fans
Hi,
My name is Rohan Narula. I am a Fresh Graduate from The University of Texas at Arlington (MS Electrical Engineering) seeking full-time opportunities from June 2017. My specializations are in Embedded Systems / Firmware Development, Automation & Controls.
Best Practices and Performance Studies for High-Performance Computing ClustersIntel® Software
This session focuses on key system tunables for maximizing application performance of high-performance computing (HPC) workloads, and addresses porting, optimizing, and running applications to maximize performance. We present practical tips and techniques for building and running applications on multicore processors. We analyze sample performance and scaling data from various applications, and identify the best options.
The Microarchitecure Of FPGA Based Soft ProcessorDeepak Tomar
this presentation is on the Paper "The Microarchitecure Of FPGA Based Soft Processor" by Peter Yiannacouras, Jonathan Rose and
J Gregory Steffan
Dept. of Electrical and Computer Engineering
University of Toronto
Replacing iptables with eBPF in Kubernetes with CiliumMichal Rostecki
Cilium is an open source project which provides networking, security and load balancing for application services that are deployed using Linux container technologies by using the native eBPF technology in the Linux kernel. In this presentation we talked about:
- The evolution of the BPF filters and explained the advantages of eBPF Filters and its use cases today in Linux especially on how Cilium networking utilizes the eBPF Filters to secure the Kubernetes workload with increased performance when compared to legacy iptables.
- How Cilium uses SOCKMAP for layer 7 policy enforcement - How Cilium integrates with Istio and handles L7 Network Policies with Envoy Proxies.
- The new features since the last release such as running Kubernetes cluster without kube-proxy, providing clusterwide NetworkPolicies, providing fully distributed networking and security observability platform for cloud native workloads etc.
The Swiss ISP SWITCH has developed a scalable IPFIX exporter built using Snabb.
In 2022 the application gained many new features, and was upstreamed into the
main Snabb repository. We will showcase a production-grade Snabb application,
and discuss implementation challenges and how Snabb helps you deal with them.
(c) FOSDEM 2023
4 & 5 February 2023
https://fosdem.org/2023/schedule/event/network_snabbflow_ipfix/
Sudheer Mechineni, Head of Application Frameworks, Standard Chartered Bank
Discover how Standard Chartered Bank harnessed the power of Neo4j to transform complex data access challenges into a dynamic, scalable graph database solution. This keynote will cover their journey from initial adoption to deploying a fully automated, enterprise-grade causal cluster, highlighting key strategies for modelling organisational changes and ensuring robust disaster recovery. Learn how these innovations have not only enhanced Standard Chartered Bank’s data infrastructure but also positioned them as pioneers in the banking sector’s adoption of graph technology.
Elevating Tactical DDD Patterns Through Object CalisthenicsDorra BARTAGUIZ
After immersing yourself in the blue book and its red counterpart, attending DDD-focused conferences, and applying tactical patterns, you're left with a crucial question: How do I ensure my design is effective? Tactical patterns within Domain-Driven Design (DDD) serve as guiding principles for creating clear and manageable domain models. However, achieving success with these patterns requires additional guidance. Interestingly, we've observed that a set of constraints initially designed for training purposes remarkably aligns with effective pattern implementation, offering a more ‘mechanical’ approach. Let's explore together how Object Calisthenics can elevate the design of your tactical DDD patterns, offering concrete help for those venturing into DDD for the first time!
Why You Should Replace Windows 11 with Nitrux Linux 3.5.0 for enhanced perfor...SOFTTECHHUB
The choice of an operating system plays a pivotal role in shaping our computing experience. For decades, Microsoft's Windows has dominated the market, offering a familiar and widely adopted platform for personal and professional use. However, as technological advancements continue to push the boundaries of innovation, alternative operating systems have emerged, challenging the status quo and offering users a fresh perspective on computing.
One such alternative that has garnered significant attention and acclaim is Nitrux Linux 3.5.0, a sleek, powerful, and user-friendly Linux distribution that promises to redefine the way we interact with our devices. With its focus on performance, security, and customization, Nitrux Linux presents a compelling case for those seeking to break free from the constraints of proprietary software and embrace the freedom and flexibility of open-source computing.
SAP Sapphire 2024 - ASUG301 building better apps with SAP Fiori.pdfPeter Spielvogel
Building better applications for business users with SAP Fiori.
• What is SAP Fiori and why it matters to you
• How a better user experience drives measurable business benefits
• How to get started with SAP Fiori today
• How SAP Fiori elements accelerates application development
• How SAP Build Code includes SAP Fiori tools and other generative artificial intelligence capabilities
• How SAP Fiori paves the way for using AI in SAP apps
UiPath Test Automation using UiPath Test Suite series, part 5DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 5. In this session, we will cover CI/CD with devops.
Topics covered:
CI/CD with in UiPath
End-to-end overview of CI/CD pipeline with Azure devops
Speaker:
Lyndsey Byblow, Test Suite Sales Engineer @ UiPath, Inc.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
GraphSummit Singapore | The Art of the Possible with Graph - Q2 2024Neo4j
Neha Bajwa, Vice President of Product Marketing, Neo4j
Join us as we explore breakthrough innovations enabled by interconnected data and AI. Discover firsthand how organizations use relationships in data to uncover contextual insights and solve our most pressing challenges – from optimizing supply chains, detecting fraud, and improving customer experiences to accelerating drug discoveries.
A tale of scale & speed: How the US Navy is enabling software delivery from l...sonjaschweigert1
Rapid and secure feature delivery is a goal across every application team and every branch of the DoD. The Navy’s DevSecOps platform, Party Barge, has achieved:
- Reduction in onboarding time from 5 weeks to 1 day
- Improved developer experience and productivity through actionable findings and reduction of false positives
- Maintenance of superior security standards and inherent policy enforcement with Authorization to Operate (ATO)
Development teams can ship efficiently and ensure applications are cyber ready for Navy Authorizing Officials (AOs). In this webinar, Sigma Defense and Anchore will give attendees a look behind the scenes and demo secure pipeline automation and security artifacts that speed up application ATO and time to production.
We will cover:
- How to remove silos in DevSecOps
- How to build efficient development pipeline roles and component templates
- How to deliver security artifacts that matter for ATO’s (SBOMs, vulnerability reports, and policy evidence)
- How to streamline operations with automated policy checks on container images
In his public lecture, Christian Timmerer provides insights into the fascinating history of video streaming, starting from its humble beginnings before YouTube to the groundbreaking technologies that now dominate platforms like Netflix and ORF ON. Timmerer also presents provocative contributions of his own that have significantly influenced the industry. He concludes by looking at future challenges and invites the audience to join in a discussion.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
Observability Concepts EVERY Developer Should Know -- DeveloperWeek Europe.pdfPaige Cruz
Monitoring and observability aren’t traditionally found in software curriculums and many of us cobble this knowledge together from whatever vendor or ecosystem we were first introduced to and whatever is a part of your current company’s observability stack.
While the dev and ops silo continues to crumble….many organizations still relegate monitoring & observability as the purview of ops, infra and SRE teams. This is a mistake - achieving a highly observable system requires collaboration up and down the stack.
I, a former op, would like to extend an invitation to all application developers to join the observability party will share these foundational concepts to build on:
GridMate - End to end testing is a critical piece to ensure quality and avoid...ThomasParaiso2
End to end testing is a critical piece to ensure quality and avoid regressions. In this session, we share our journey building an E2E testing pipeline for GridMate components (LWC and Aura) using Cypress, JSForce, FakerJS…
Threats to mobile devices are more prevalent and increasing in scope and complexity. Users of mobile devices desire to take full advantage of the features
available on those devices, but many of the features provide convenience and capability but sacrifice security. This best practices guide outlines steps the users can take to better protect personal devices and information.
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
4. About the LinuxCNC
LinuxCNC is a descendent of the original
NIST(The National Institutes of Standards
and Technology) Enhanced Machine
Controller software.
LinuxCNC is precompiled with Ubuntu LTS
(long term support) versions for ease of
installation and longevity.
LinuxCNC runs on Linux using real time
extensions.
4
6. LinuxCNC software
System Requirements
700 MHz x86 processor (1.2 GHz x86
processor recommended).
384 MB of RAM (512 MB up to 1 GB
recommended).
8 GB hard disk.
Graphics card capable of at least 1024x768
resolution.
A network or Internet connection (not strictly
needed, but very useful for updates and for
communicating with the LinuxCNC community).
6
7. LinuxCNC software
LinuxCNC provides:
a graphical user interface (actually several
interfaces to choose from).
an interpreter for G-code (the RS-274 machine tool
programming language).
a realtime motion planning system with look-ahead.
operation of low-level machine electronics such as
sensors and motor drives.
an easy to use breadboard layer for quickly creating
a unique configuration for your machine.
a software PLC programmable with ladder diagrams
easy installation with a Live-CD.
7
9. LinuxCNC Hierarchical
Four main components to the LinuxCNC
software:
a motion controller (EMCMOT)
a discrete IO controller (EMCIO)
a task executor which coordinates them
(EMCTASK)
and one of several graphical user interfaces
In addition there is a layer called HAL
(Hardware Abstraction Layer) which
allows configuration of LinuxCNC without
the need of recompiling.
9
14. Configuring LinuxCNC
INI : The ini file overrides defaults that are
compiled into the LinuxCNC code.
HAL : The HAL files start up process modules and
provide linkages between LinuxCNC signals and
specific hardware pins.
VAR : The var file is a way for the interpreter to
save some values from one run to the next. These
values are saved from one run to another but not
always saved immediately.
TBL : The tbl file saves tool information.
NML : The nml file configures the communication
channels used by the LinuxCNC. It is normally
setup to run all of the communication within a
single computer but can be modified to
communicate between several computers.
14
15. Configuring LinuxCNC
The INI File Components
Comments
Sections
Variables
Custom Sections and Variables
Sections
Comments
Variables
15
16. Configuring LinuxCNC
Sections
[EMC] general information
[DISPLAY] settings related to the graphical user interface
[FILTER] settings input filter programs
[RS274NGC] settings used by the g-code interpreter
[EMCMOT] settings used by the real time motion
controller
[TASK] settings used by the task controller
[HAL] specifies .hal files
[HALUI] MDI commands used by HALUI
[TRAJ] additional settings used by the real time motion
controller
[AXIS_n] individual axis variables
[EMCIO] settings used by the I/O Controller
Example
16
18. Configuring LinuxCNC
Hardware Abstraction Layer (HAL)
Component
A HAL component is a piece of software with
well-defined inputs, outputs, and behavior,
that can be installed and interconnected as
needed.
Parameter
Many hardware components have adjustments
that are not connected to any other
components but still need to be accessed.
There are two types of parameters: input &
Output
18
19. Configuring LinuxCNC
Hardware Abstraction Layer (HAL)
Pin
Hardware components have terminals which
are used to interconnect them. The HAL
equivalent is a pin or HAL pin. HAL pins are
software entities that exist only inside the
computer.
Physical_Pin
Many I/O devices have real physical pins or
terminals that connect to external hardware.
To avoid confusion, these are referred to as
physical pins. These are the things that stick
out into the real world.
19
20. Configuring LinuxCNC
Hardware Abstraction Layer (HAL)
Signal
In a physical machine, the terminals of real
hardware components are interconnected by wires.
Type
Bit - a single TRUE/FALSE or ON/OFF value
float - a 64 bit floating point value, with
approximately 53 bits of resolution and over 1000
bits of dynamic range.
u32 - a 32 bit unsigned integer, legal values are 0
to 4,294,967,295
s32 - a 32 bit signed integer, legal values are 2,147,483,647 to +2,147,483,647
Both pins and signals have types, and signals can
only be connected to pins of the same type
20
21. Configuring LinuxCNC
Hardware Abstraction Layer (HAL)
Function
Each function is a block of code that performs
a specific action. The system integrator can
use threads to schedule a series of functions
to be executed in a particular order and at
specific time intervals.
Thread
A thread is a list of functions that runs at
specific intervals as part of a realtime task.
When a thread is first created, it has a specific
time interval (period), but no functions.
Functions can be added to the thread, and will
be executed in order every time the thread
runs.
21
23. Configuring LinuxCNC
HAL Commands
loadrt
The command loadrt loads a real time HAL
component. Real time component
functions need to be added to a thread to
be updated at the rate of the thread
23
24. Configuring LinuxCNC
HAL Commands
addf
The command addf adds a real time
component function to a thread. You have
to add a function from a HAL real time
component to a thread to get the function
to update at the rate of the thread.
24
25. Configuring LinuxCNC
HAL Commands
loadusr
The command loadusr loads a user space
HAL component. User space programs are
their own separate processes, which
optionally talk to other HAL components
via pins and parameters. You cannot load
real time components into user space.
25
30. Appendix
Parallel Port Driver
installing
Pins
loadrt hal_parport cfg="<config-string>"
parport.<p>.pin-<n>-out (bit) Drives a physical output pin.
parport.<p>.pin-<n>-in (bit) Tracks a physical input pin.
parport.<p>.pin-<n>-in-not (bit)Tracks a physical input pin,
but inverted.
Parameters
parport.<p>.pin-<n>-out-invert (bit) Inverts an output pin.
parport.<p>.pin-<n>-out-reset (bit) (only for out pins) TRUE
if this pin should be reset when the -reset function is executed.
parport.<p>.reset-time' (U32) The time (in nanoseconds)
between a pin is set by write and reset by the reset function if
it is enabled.
30
31. Appendix
Parallel Port Driver
Functions
parport.<p>.read (funct) Reads physical input pins
of port <portnum> and updates HAL -in and -innot pins.
parport.read-all (funct) Reads physical input pins of
all ports and updates HAL -in and -in-not pins.
parport.<p>.write (funct) Reads HAL -out pins of
port <p> and updates that port’s physical output
pins.
parport.write-all (funct) Reads HAL -out pins of all
ports and updates all physical output pins.
parport.<p>.reset (funct) Waits until reset-time has
elapsed since the associated write, then resets pins
to values indicated by -out-invert and -outinvert settings.
31
32. Appendix
software step pulse generation
installing
loadrt stepgen step_type=type0[,type1...]
[ctrl_type=type0[,type1...]] [user_step_type=#,#...]
FUNCTIONS
stepgen.make-pulses (no floating-point)
Generates the step pulses, using information computed
by update-freq. Must be called as frequently as possible, to
maximize the attainable step rate and minimize jitter.
Operates on all channels at once.
stepgen.capture-position (uses floating point)
Captures position feedback value from the high speed code
and makes it available on a pin for use elsewhere in the
system. Operates on all channels at once.
stepgen.update-freq (uses floating point)
Accepts a velocity or position command and converts it into a
form usable by make-pulses for step generation. Operates
on all channels at once.
32
33. Appendix
software step pulse generation
PINS
stepgen.N.counts s32 out
The current position, in counts, for channel N. Updated by captureposition.
stepgen.N.position-fb float out
The current position, in length units (see parameter position-scale).
Updated by capture-position.
stepgen.N.enable bit in
Enables output steps - when false, no steps are generated.
stepgen.N.velocity-cmd float in (velocity mode only)
Commanded velocity, in length units per second (see
parameter position-scale).
stepgen.N.position-cmd float in (position mode only)
Commanded position, in length units (see parameter position-scale).
stepgen.N.step bit out
Step pulse output.
stepgen.N.dir bit out
Direction output: low for forward, high for reverse.
33
34. Appendix
software step pulse generation
PARAMETERS
stepgen.N.frequency float ro
The current step rate, in steps per second, for channel N.
stepgen.N.maxaccel float rw
The acceleration/deceleration limit, in length units per second squared.
stepgen.N.maxvel float rw
The maximum allowable velocity, in length units per second. If the requested maximum
velocity cannot be reached with the current combination of scaling andmake-pulses thread
period, it will be reset to the highest attainable value.
stepgen.N.position-scale float rw
The scaling for position feedback, position command, and velocity command, in steps per
length unit.
stepgen.N.rawcounts s32 ro
The position in counts, as updated by make-pulses. (Note: this is updated more frequently
than the counts pin.)
stepgen.N.steplen u32 rw
The length of the step pulses, in nanoseconds. Measured from rising edge to falling edge.
stepgen.N.stepspace u32 rw
The minimum space between step pulses, in nanoseconds. Measured from falling edge to
rising edge.
stepgen.N.dirsetup u32 rw
The minimum setup time from direction to step, in nanoseconds periods. Measured from
change of direction to rising edge of step.
stepgen.N.dirhold u32 rw
The minimum hold time of direction after step, in nanoseconds. Measured from falling edge
of step to change of direction.
34
63. AXIS
1.
2.
3.
4.
Create an .xml file that contains your
panel description and put it in your
config directory.
Add the PyVCP entry to the [DISPLAY]
section of the ini file with your .xml file
name.
Add the POSTGUI_HALFILE entry to the
[HAL] section of the ini file with the
name of your postgui HAL file name.
Add the links to HAL pins for your panel
in the postgui.hal file to connect your
PyVCP panel to LinuxCNC
63
67. Stand Alone
1.
2.
3.
Create an .xml file that contains
your panel description and put it in
your config directory
Add a loadusr line to your .hal file
to load each panel.
Add the links to HAL pins for your
panel in the postgui.hal file
to connect your PyVCP panel to
LinuxCNC.
67
69. Widgets
Bits are off/on signals
Numbers can be float, s32 or u32
1.
2.
3.
4.
5.
indicate bit signals: led, rectled
control bit signals: button, checkbutton,
radiobutton
indicate number signals: number, s32, u32,
bar, meter
control number signals: spinbox, scale,
jogwheel
Helper widgets: hbox, vbox, table, label,
labelframe
69
70. Widgets -- General Notes
tag-based and attribute-based
syntax
<led halpin="my-led"/>
<led>
<halpin>"my-led"</halpin>
</led>
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