This document discusses digital filters and their implementation using FPGA. It describes how digital filters operate on digitized signals to improve output quality by achieving objectives like signal separation and distortion removal. Common filter types are described like low-pass, high-pass, band-pass and band-stop filters. Finite impulse response (FIR) filters and their implementation using shift registers and multiplication is explained. Examples of FIR filters in Verilog are provided along with test benches. Infinite impulse response (IIR) filters are also discussed and an example single-tap IIR filter implemented in Verilog is shown.

1. E N G R . R A S H I D F A R I D C H I S H T I
L E C T U R E R , D E E , F E T , I I U I
C H I S H T I @ I I U . E D U . P K
F I R , I I R F I L T E R
FPGA Based System Design
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2.  A digital filter is a system that performs mathematical algorithm that operates on a
digital input signal to improve output signal for the purpose of achieving a filter
objective such as:
 separation of signals that have been combined
 restoration of signals that have been distorted
 Digital filter mostly operates on digitized analog signals or just numbers, representing
some variable, stored in a computer memory
 A simplified block diagram of a real-time digital filter, with analog input and output
signals, is given below.
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Digital Filter
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3.  A low-pass filter is a filter that passes low-frequency signals but attenuates
(reduces the amplitude of) signals with frequencies that are higher than the cut
off frequency.
 A high-pass filter, is a filter that passes signals containing high frequencies, but
attenuates frequencies lower than the filter's cut off frequency.
 A band-pass filter is a device that passes frequencies within a certain range and
rejects (attenuates) frequencies outside that range.
 A band-stop filter or band-rejection filter is a filter that passes most frequencies
unaltered, but attenuates those in a specific range to very low levels.
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Digital Filter Types
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4.  A Finite Impulse Response (FIR) filter is a type of a signal processing filter whose
impulse response ( or response to any finite length input ) is of finite duration , because it
settles to zero in finite time.
 The impulse response of an Nth-order discrete - time FIR filter lasts for N+1 samples, and
then dies to zero. For a discrete-time FIR filter, the output is a weighted sum of the current
and a finite number of previous input values.
 The operation is described by the following equation, which defines the output sequence
y[n] in terms of its input sequence x[n] :
 y[n] = b0 x[n] + b x[n-1] + ................ +b x[n-N]
 y[n] = (Summation i=0 to N ) bi x[n-i]
 x[n] = input signal, y[n] = output signal, bi = filter co-efficients, N = filter order
BLOCK DIAGRAM
OF DIGITAL
FIR FILTER
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Digital FIR (Finite Impulse Response) Filter
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5.  5-Tap FIR Filter Example:
y[n] = h0*x[n] + h1*x[n-1] + h2*x[n-2] + h3*x[n-3]+ h4*x[n-4]
 The critical path (or the minimum time required for processing a new sample) is
limited by 1 multiply and 4 add times. Thus the “sample period” (or the “sample
frequency”) is given by:
Tsample ≥ TM + 4TA Here TM is multiplication time
fsample ≤ 1/ (TM + 4TA) TA is addition time
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Digital FIR (Finite Impulse Response) Filter
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y[n]
x[n] x[n-1] x[n-2] x[n-3] x[n-4]
h0 h1 h2 h3 h4
Z-1
Z-1
Z-1
Z-1

6. // Module uses multipliers to implement an FIR filter
module FIR_filter(
input signed [15:0] x, input clk,
output reg signed [31:0] yn );
reg signed [15:0] xn [4:0]; wire signed [31:0] v;
// Coeefficients of the filter
wire signed [15:0] h0 = 16'h0325;
wire signed [15:0] h1 = 16'h1e00;
wire signed [15:0] h2 = 16'h3DB6;
wire signed [15:0] h3 = 16'h1e00;
wire signed [15:0] h4 = 16'h0325;
// Implementing filters using multiplication and addition operators
assign v = (h0*xn[0] + h1*xn[1] + h2*xn[2] + h3*xn[3] + h4*xn[4]);
always @(posedge clk) begin
xn[0] <= x; xn[1] <= xn[0];
xn[2] <= xn[1]; xn[3] <= xn[2];
xn[4] <= xn[3];
yn <= v; // Registering the output
end
endmodule
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FIR Filter: Verilog Programming
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7. module Test_FIR_filter;
reg signed [15:0] x; reg clk; wire signed [31:0] yn;
initial $monitor ( $time, "," , x , "," , yn);
FIR_filter FIR1(x, clk, yn);
initial begin clk = 0; repeat (250) #5 clk = ~clk; end
initial begin x = 0; repeat (5) #100 x = x+100;
repeat (5) #100 x = x-100; end
endmodule
input output response
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FIR Filter: Test Bench
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8.  This example implements a simple single tap infinite impulse response (IIR) filter in
RTL Verilog and writes its stimulus to demonstrate coding of a design with feedback
registers. The design implements the following equation:
y [n] = 0.5y[n-1] + x[n]
 The multiplication by 0.5 is implemented by an arithmetic shift right by 1 operation.
 A register y _reg realizes y [n -1] in the feedback path of the design, thus needing
reset logic. The reset logic is implemented as an active-low asynchronous reset.
 The module has 16-bit data x, clock clk, reset rst_n as inputs and the value of y as
output.
 The module IIR has two procedural blocks. One block models combinational logic
and the other sequential. The block that models combinational logic consists of an
adder and hard-wired shifter. The adder adds the input data x in shifted value of y_reg.
 The output of the combinational cloud is assigned to y.
 The sequential block latches the value of y in y_reg.
 The RTL Verilog code for the module IIR is given next:
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IIR Filter
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9. // Implimenting FIR Filter y[n] = 0.5y[n-1] + x[n]
module iir(
input signed [15:0] Xn, input clk, rst_n, output reg signed [31:0] Yn);
reg signed [31:0] Yn_1;
always @(Yn_1 or Xn) Yn = (Yn_1 >>> 1) + Xn; // combinitional logic block
always @(posedge clk or negedge rst_n) begin // sequential logic block
if (!rst_n) Yn_1 <= 0;
else Yn_1 <= Yn;
end
Endmodule
module stimulus_irr;
reg [15:0] X; reg CLK, RST_N;
wire [31:0] Y;
iir IRR0(X, CLK, RST_N, Y); // instantiation of the module
initial begin #5 RST_N = 0; #2 RST_N = 1; end
initial begin X = 0; repeat (5) #20 X = X+1;
repeat (5) #20 X = X-1; end
initial begin CLK = 0; repeat (30) #10 CLK = ~CLK; end
initial $monitor($time, " , %d, %d", X, Y);
endmodule
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IIR Filter: Verilog Programming
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x[n]
0.5 Z-1
y[n]
y[n-1]
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IIR Filter: Verilog Programming
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