The document outlines the syllabus and key concepts related to ARM microcontrollers, specifically focusing on the ARM Cortex-M3 architecture. It discusses the advantages of ARM processors, including low power consumption, high performance, and ease of use, while highlighting the evolution and versatility of ARM technology in embedded systems. Additionally, the document details instruction sets, processor registers, and application areas for Cortex-M3, emphasizing its application in low-cost microcontrollers across various industries.

1. ARM Microcontrollers
&
Embedded Systems
Girish M.
Asst. Professor
Department of ECE
1
Class 1

2. Syllabus
Girish M, Asst. Professor
2
M1- ARM 32-bit Microcontrollers
M2- ARM Cortex M3 Instruction Sets and Programming
M3 - Embedded System Components
M4 - Embedded System Design Concepts
M5 - RTOS and IDE for Embedded System Design
1. Joseph Yiu, ―The Definitive Guide to the ARM Cortex-M3, 2nd
Edition, Newnes, (Elsevier), 2010.
2. Shibu K V, ―Introduction to Embedded Systems, Tata McGraw
Hill Education Private Limited, 2nd Edition.

3. Module-1
ARM-32 bit Microcontrollers
Girish M, Asst. Professor
3
Girish M.
Assistant Professor
Dept.of ECE

4. Outline of the Module - 1
1. Introduction, Brief History and Importance
2. Thumb-2 technology and applications of ARM
3. Architecture of ARM Cortex M3
4. Various Units in the architecture
5. Debugging support
6. General Purpose Registers
7. Special Registers
8. Exceptions and Interrupts
9. Stack operation and Reset sequence
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4

5. WHY ARM PROCESSOR?
1. Microcontroller market is vast and array of vendors,
devices, and architectures is competing in this market.
2. Requirement for higher performance microcontrollers
suits to industry’s changing needs:
Increasingly connected - USB, Ethernet, Wireless Radio-Processing
needs to support
General application complexity - more sophisticated user interfaces,
multimedia requirements, system speed, and convergence of
functionalities.
3. Handle more work without increasing a product’s
frequency or power.
Girish M, Asst. Professor 5

6. ARM Cortex-M3 processor
First of the Cortex generation of processors released by
ARM in 2006
Designed to target the 32-bit microcontroller market
Provides excellent performance at low gate count
New features previously available only in high-end
processors
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7. How it address 32-bit embedded processor
market?
1. Greater performance efficiency
2. Low power consumption
3. Enhanced determinism
4. Improved code density
5. Ease of use
6. Lower cost solutions
7. Wide choice of development tools
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8. Designers are looking at reducing the system cost-
 Single, more powerful device can potentially
replace three or four traditional 8-bit devices
 Amount of code reuse across all systems
 Can be easily programmed using the C language
 Application code can be ported and reused easily
 Reduces development time and testing costs
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9. Girish M, Asst. Professor 9

10. Brief History
• ARM - Acorn RISC Machine from Acorn
Computers Ltd. of Cambridge, UK.
• In 1990, ARM Ltd. was established joint
venture of Apple Computer, Acorn Computer
Group, and VLSI Technology and ARM was
renamed as Advanced RISC Machines.
• A semiconductor IP - Intellectual Property
company.
Girish M, Asst. Professor 10
Class 2

11. Brief History
• Licenses IP cores to partner companies e.g Nokia,
Philips Semiconductors ,Texas Instruments
• Also develop technologies to assist with the
designing of the ARM architecture
Girish M, Asst. Professor 11
ARM is not a chip producer.

12. Girish M, Asst. Professor
12
The Cortex-M3 Processor versus Cortex-M3-
Based MCUs

13. ARMVersions
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Architecture Processor
ARMv1 ARM1
ARMv2 ARM2, ARM250, ARM3
ARMv3 ARM6, ARM7
ARMv4 ARM8
ARMv4T ARM7TDMI, ARM9TDMI
ARMv5TE ARM7EJ, ARM9E, ARM10E
ARMv6 ARM11

14. ARMVersions
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Architecture Processor
ARMv6-M ARM Cortex-M0, ARM Cortex-M0+, ARM
Cortex-M1,
ARMv7E-M ARM Cortex-M4, ARM Cortex-M7
ARMv8-M ARM Cortex-M23, ARM Cortex-M33
ARMv7-R ARM Cortex-R4, ARM Cortex-R5, ARM
Cortex-R7, ARM Cortex-R8
ARMv7-A ARM Cortex-A5, ARM Cortex-A7, ARM
Cortex-A8, ARM Cortex-A9,ARM Cortex-
A12, ARM Cortex-A15, ARM Cortex-A17

15. ARM Architecture version 7
A Profile (ARMv7-A)
• Application processors
• Handle complex applications such as high-end
embedded operating systems (Symbian, Linux, and
Windows Embedded)
• Highest processing power, virtual memory system
support with memory management units (MMUs)
Girish M, Asst. Professor 15

16. ARM Architecture version 7
R Profile (ARMv7-R)
• Real-time, high-performance processors
• Higher end of the real-time market
• Applications, such as high-end breaking systems
and hard drive controllers
• High processing power, high reliability and
Low latency is important
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17. ARM Architecture version 7
M Profile (ARMv7-M)
• Embedded Microcontroller- type systems
• Low-cost applications in which processing
efficiency is important and cost, power
consumption, low interrupt latency, and ease
of use are critical
• Industrial control applications
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18. ARM Versions
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19. Instruction Set Development
ARM instructions- 32 bits- ARM state
Thumb instructions- 16 bits- Thumb state
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ARM7TDMI
T indicates Thumb instruction
D indicates JTAG debugging
M indicates fast multiplier
I- Indicates an embedded ICE
(In Circuit Emulator)module

20. Thumb technology
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21. Thumb-2 Technology
• Thumb Instruction Set Architecture into a highly efficient
and powerful instruction set
• Benefits in terms of ease of use, code size, and performance
• Superset of the previous 16-bit Thumb instruction set with
additional 16-bit instructions alongside 32-bit instructions
• More complex operations to be carried out in the Thumb
state, thus allowing higher efficiency by reducing the
number of states switching between ARM state and Thumb
state.
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Class 3

22. The Relationship between the Thumb Instruction Set in
Thumb-2 Technology and the Traditional Thumb.
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23. Thumb-2 Technology
• Small memory system devices such as
microcontrollers and reducing the size of the
processor, Cortex-M3 supports only the Thumb-2
(and traditional Thumb) instruction set.
• It uses the Thumb-2 instruction set for all operations
• Cortex-M3 processor is not backward compatible
with traditional ARM processors
• Cortex-M3 processor can execute almost all the 16-bit
Thumb instructions (supported on ARM7 family
processors) making application porting easy
Girish M, Asst. Professor 23

24. Thumb-2 Technology
• No need to switch the processor between Thumb
state (16-bit instructions) and ARM state (32-bit
instructions).
• Example
• ARM7 or ARM9 family processors need to switch to
ARM state to carry out complex calculations or a
large number of conditional operations and good
performance is needed
• The Thumb-2 instruction set is a very important
feature of the ARMv7 architecture.
Girish M, Asst. Professor 24

25. Cortex-M3 Processor Applications
• Low-cost microcontrollers - Used in consumer
products, from toys to electrical appliances.
• lower power, high performance, and ease-of-use
• Automotive - automotive industry, used in real-time
systems.
• Very high-performance efficiency
• Low interrupt latency
• Supports up to 240 external vectored Interrupts
• Built-in interrupt controller, nested interrupt supports,
optional MPU.
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26. Cortex-M3 Processor Applications
• Data communications- Bluetooth and ZigBee
• Low power and high efficiency
• Instructions in Thumb-2 for bit-field manipulation
• Industrial control: Simplicity, fast response, and
reliability are key factors.
• Interrupt feature, low interrupt latency
• Enhanced fault-handling features
• Consumer products: high-performance
microprocessor
• Highly efficient and low in power and Supports MPU
Girish M, Asst. Professor 26

27. Overview of Cortex M3
32 bit-൞
Data path
Register bank
Memory interfaces
H𝐚𝐫𝐯𝐚𝐫𝐝 𝐀𝐫𝐜𝐡𝐢𝐭𝐞𝐜𝐭𝐮𝐫𝐞
Seperate Instructio𝒏 𝒂𝒏𝒅 𝑫𝒂𝒕𝒂 𝑩𝒖𝒔
𝑰nstructions and data accesses
to take place at the same time
Not affect the instruction pipeline
Girish M, Asst. Professor 27

28. Overview of Cortex m3
• Optional Memory Protection Unit (MPU)
• Possible to use an external cache if it’s required
• Both little endian and big endian memory
systems are supported
• Number of fixed internal debugging components
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29. Overview of Cortex m3
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30. Registers in cortex m3
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31. Special Registers in cortex m3
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32. General Purpose Registers R0 through R7:
• Low registers
• Can be accessed by all 16-bit Thumb instructions and all
32-bit Thumb-2 instructions
• Size: 32 bit
• Default Value: Unpredictable
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Class 4

33. General Purpose Registers R8 through R12:
•High registers
• Can be accessed by all 32-bit Thumb instructions but
not all 16-bit Thumb-2 instructions
•Size: 32 bit
•Default Value: Unpredictable
Girish M, Asst. Professor 33

34. Supports 2 SP- Allows two Separate stack memories to be set
up
Main Stack Pointer (MSP):
• Default SP
• Used by the operating system (OS) kernel, exception handlers,
and all application codes that require privileged access.
Process Stack Pointer (PSP):
• Used by the base-level application code
(when not running an exception handler)
• Always the last 2 bit of SP are Zero – indicates Word aligned
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Stack Pointer R13

35. Girish M, Asst. Professor 35
Because register PUSH and POP operations are always word aligned
(their addresses must be 0x0, 0x4, 0x8, ...)

36. The Cortex-M3 uses a full - descending stack
arrangement.
PUSH {R0} ; R13=R13-4, then Memory[R13] = R0
POP {R0} ; R0 = Memory[R13], then R13 = R13 + 4
Multiple registers can also be stored in SP
subroutine_1
PUSH {R0-R7, R12, R14} ; Save registers
. . . .………….... . . . .. . .. . .. . . ; Do your processing
POP {R0-R7, R12, R14} ; Restore registers
BX R14 ; Return to calling function
Instead of using R13, SP can be used in program codes
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37. Link Register R14
LR is used to store the return program counter (PC)
when a subroutine or function is called.
main ; Main program
...
BL function1 ; Call function1 using Branch with Link instruction.
; PC = function1 and
; LR = the next instruction in main
...
function1
.......................... ; Program code for function 1
BX LR ; Return
Instead of using R14, LR can be used in program codes
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38. Program Counter R15
• In assembler code it can be access either by R15 or
PC.
• Because of the pipelined nature of the Cortex-M3
processor, when you read this register, you will find
that the value is different than the location of the
executing instruction, normally by 4.
0x1000 : MOV R0, PC ; R0 = 0x1004
• Writing to the PC will cause a branch (but LRs do not
get updated).
Girish M, Asst. Professor 38

39. Special Registers
• Program Status registers (PSRs)
• Interrupt Mask registers
• (PRIMASK, FAULTMASK, and BASEPRI)
• Control register (CONTROL)
• Special registers can only be accessed via MSR and
MRS instructions; They do not have memory
addresses
MRS <reg>, <special_reg>; Read special register
MSR <special_reg>, <reg>; write to special register
Girish M, Asst. Professor 39

40. Program Status registers (PSRs)
PSRs are subdivided into three status registers
• Application Program Status register (APSR)
• Interrupt Program Status register (IPSR)
• Execution Program Status register (EPSR)
Can be accessed together(xPSR) or separately
using the special register access instructions
MSR and MRS
To Read the PSR - MRS instruction
To change the APSR-MSR instruction
EPSR and IPSR are read-only
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40

41. MRS r0, APSR ; Read Flag state into R0
MRS r0, IPSR ; Read Exception/Interrupt state
MRS r0, EPSR ; Read Execution state
MSR APSR, r0 ; Write Flag state
MRS r0, PSR ; Read the combined program status word
MSR PSR, r0 ; Write combined program state word
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42. Program Status Registers (PSRs) in the Cortex-M3
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Combined Program Status Registers (xPSR) in the Cortex-M3
Class 5

43. Bit Description
N Negative
Z Zero
C Carry/borrow
V Overflow
Q Sticky saturation flag
ICI/IT Interrupt- Continuable Instruction (ICI) bits, IF-THEN
instruction status bit
T Thumb state, always 1; trying to clear this bit will cause
a fault exception
Exception
number
Indicates which exception the processor is handling
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44. PRIMASK, FAULTMASK and BASEPRI
Registers
• These registers are used to disable exceptions.
• The PRIMASK and BASEPRI registers are useful
for temporarily disabling interrupts in timing-
critical tasks.
• An OS could use FAULTMASK to temporarily
disable fault handling when a task has crashed.
Girish M, Asst. Professor 44

45. PRIMASK Register
• 1-bit register
• when this is set, it allows non- maskable interrupt
(NMI) and the hard fault exception
• All other interrupts and exceptions are masked
• The default value is 0, which means that no
masking is set
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46. FAULTMASK Register
• 1-bit register
• when this is set, it allows only non - maskable
interrupt (NMI)
• all interrupts and Fault handling exceptions are
disabled
• The default value is 0, which means that no
masking is set
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47. BASEPRI Register
• A register of up to 8 bits
• It defines the masking priority level
• Fault handling and exceptions are disabled
• When this is set, it disables all interrupts of the same
or lower level.
• Higher priority interrupts can still be allowed
• The default value is 0, which means that no masking
is set
Girish M, Asst. Professor 47

48. Device driver libraries provided by the
microcontroller vendors
x = __get_BASEPRI(); // Read BASEPRI register
x = __get_PRIMARK(); // Read PRIMASK register
x = __get_FAULTMASK(); // Read FAULTMASK register
__set_BASEPRI(x); // Set new value for BASEPRI
__set_PRIMASK(x); // Set new value for PRIMASK
__set_FAULTMASK(x); // Set new value for FAULTMASK
Girish M, Asst. Professor 48

49. In assembly language, the MRS and MSR
instructions are used
MRS r0, BASEPRI ; Read BASEPRI register into R0
MRS r0, PRIMASK ; Read PRIMASK register into R0
MRS r0, FAULTMASK ; Read FAULTMASK register into R0
MSR BASEPRI, r0 ; Write R0 into BASEPRI register
MSR PRIMASK, r0 ; Write R0 into PRIMASK register
MSR FAULTMASK, r0 ; Write R0 into FAULTMASK register
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50. The Control Register
• The control register has 2 bits
• This is used to define the privilege level and the SP
selection
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Bit Function
CONTROL[1] Stack status:
1 = Alternate stack is used
0 = Default stack (MSP) is used
CONTROL[0] 0 = Privileged in thread mode
1 = User state in thread mode

51. To access the control register in C
x = __get_CONTROL(); // Read the current value of CONTROL
__set_CONTROL(x); // Set the CONTROL value to x
To access the control register in assembly, the MRS
and MSR instructions are used:
MRS r0, CONTROL ; Read CONTROL register into R0
MSR CONTROL, r0 ; Write R0 into CONTROL register
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52. Operation Mode
Girish M, Asst. Professor 52
• Cortex-M3 processor supports two modes and
two privilege levels.
Figure: Operation Modes and Privilege Levels in Cortex-M3.
Class 6

53. Thread
mode
Privileged
Level
User level
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Handler
mode
Privileged
Level
Access to the system control space (SCS)—a part of the memory
region for configuration registers and debugging components— is
blocked. MSR Instruction cannot be used
Control Register

54. Switching of Operation Mode by Programming the
Control Register or by Exceptions
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55. Girish M, Asst. Professor 55

56. Simple Applications Do Not Require User Access
Level in Thread Mode
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56
The mode and access level of the processor are defined by the
control register. When the control register bit 0 is 0, the
processor mode changes when an exception takes place.

57. Switching Processor Mode at Interrupt
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58. Advantages
The support of privileged and user access levels
provides a more secure and robust architecture
When a user program goes wrong, it will not be able to
corrupt control registers
Memory Protection Unit (MPU) is present, it is possible to
block user programs from accessing memory regions used by
privileged processes
Separate the user application stack from the kernel stack
memory to avoid the possibility of crashing a system caused
by stack operation errors in user programs.
User program uses -PSP, Exception handlers use the MSP.
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59. Exceptions and Interrupts
Supports number of exceptions
{Fixed number of system exceptions + Number of
interrupts(IRQ)}
The number of interrupt inputs on a Cortex-M3
microcontroller depends on the individual design.
Interrupts generated by peripherals are also
connected to the interrupt input signals.
Non-maskable interrupt (NMI) input signal-
watchdog timer or a voltage-monitoring block.
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61. Vector Tables
To determine the starting address of the exception
handler, a vector table mechanism is used
The vector table is an array of word data inside the
system memory, each representing the starting address of
one exception type
The vector table is relocatable, and the relocation is
controlled by a relocation register in the NVIC
The LSB of each exception vector indicates whether the
exception is to be executed in the Thumb State
(The LSB of all the exception vectors should be set to 1)
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Class 7

62. Girish M, Asst. Professor
62

63. Nested Vectored Interrupt Controller
(NVIC) features
Nested interrupt support: programmed to
different Priority levels - override
Vectored interrupt support: ISR is located from a
vector table in memory – no software required reduces the
time to process.
Dynamic priority changes support: Priority
levels of interrupts can be changed during run time.
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64. Nested Vectored Interrupt Controller
(NVIC) features
Reduction of interrupt latency:
• Includes a number of advanced features to lower the interrupt
latency.
• These include automatic saving and restoring some register
contents, reducing delay in switching from one ISR to another
Interrupt masking:
• Interrupt masking registers BASEPRI, PRIMASK, and
FAULTMASK.
• They can be used to ensure that time-critical tasks can be
finished on time without being interrupted.
Girish M, Asst. Professor 64

65. Stack Memory Operations
Memory write or read operations
Address specified by SP
Software-controlled stack PUSH and POP
Also carried out automatically when entering or
exiting an exception/interrupt handler
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66. Basic Operations of the Stack
• Memory write or read operations
• Address specified by SP
• Data in registers is saved into stack memory by a PUSH
operation and can be restored to registers later by a POP
operation
• The SP is adjusted automatically in PUSH and POP so that
multiple data PUSH will not cause old stacked data to be
erased.
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67. Main program
...
; R0 = X, R1 =Y, R2 = Z
BL function1 Subroutine
function1
PUSH {R0} ; store R0 to stack & adjust SP
PUSH {R1} ; store R1 to stack & adjust SP
PUSH {R2} ; store R2 to stack & adjust SP
... ; Executing task (R0, R1 and R2 could be changed)
POP {R2} ; restore R2 and SP re-adjusted
POP {R1} ; restore R1 and SP re-adjusted
POP {R0} ; restore R0 and SP re-adjusted
BX LR ; Return
; Back to main program
; R0 = X, R1 =Y, R2 = Z
... ; next instructions
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Stack Implementation in Cortex M3

68. Main program
...
; R0 = X, R1 =Y, R2 = Z
BL function1
Subroutine
function1
PUSH {R0 – R2} ; store R0 ,R1,R2 to stack
... ; Executing task (R0, R1 and
;R2could be changed)
POP {R0 - R2} ; restore R0 ,R1,R2
BX LR ; Return
; Back to main program
; R0 = X, R1 =Y, R2 = Z
... ; next instructions
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Stack Operation Basics: Multiple Register Stack Operation.

69. Main program
...
; R0 = X, R1 =Y, R2 = Z
BL function1
Subroutine
function1
PUSH {R0 – R2,LR} ; Save Register including
;Link register
... ; Executing task (R0, R1 and R2could be changed)
POP {R0 - R2, PC} ; restore R0 ,R1,R2 and Return
; Back to main program
; R0 = X, R1 =Y, R2 = Z
... ; next instructions
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Stack Operation Basics: Combining Stack POP and RETURN.

70. Address Stack Memory
0x20007FFC Occupied
0x20007 FF8 Occupied
0x20007 FF4 Last Pushed data
0x20007 FF0
----
----
----
----
----
0x20007C00
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The Cortex-M3 uses a full-descending stack operation model
0x20007 FF4
SP
0x20008000
SP

71. Girish M, Asst. Professor 71
PUSH R0

72. POP {R0}
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Because each PUSH/POP operation transfers 4 bytes of
data (each register contains 1 word, or 4 bytes),
the SP decrements/increments by 4 at a time or a multiple of
4 if more than 1 register is pushed or popped.

73. The two-stack model in the cortex-m3
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CONTROL [1]
0 MSP is used for both thread mode
and handler mode
1 PSP is used in thread mode
MSP is used in handler mode
• Cortex-M3 has two SPs: the MSP and the PSP.
• When CONTROL[1] is 0 - same stack memory region
• When the CONTROL[1] is 1 - separate stack memory
regions
Class 8

74. The two-stack model in the cortex-m3
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CONTROL
[1]
0 MSP is used for both thread mode and
handler mode

75. The two-stack model in the cortex-m3
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CONTROL
[1] 1 PSP is used in thread mode
MSP is used in handler mode

76. Possible to perform read/write operations directly
to the MSP and PSP only in privileged level
x = __get_MSP(); // Read the value of MSP
__set_MSP(x); // Set the value of MSP
x = __get_PSP(); // Read the value of PSP
__set_PSP(x); // Set the value of PSP
MRS R0, MSP ; Read Main Stack Pointer to R0
MSR MSP, R0 ; Write R0 to Main Stack Pointer
MRS R0, PSP ; Read Process Stack Pointer to R0
MSR PSP, R0 ; Write R0 to Process Stack Pointer
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77. Reset Sequence
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0x200080000x00000000
PC
PC loaded with address 0x00000000
Processor read the value from this addres
to MSP
0x00000004 0x0000100
0x0000100
First
Instruction
Next
Instruction
:
PC loaded with address 0x0000004
Processor read the address of reset
handler and jumps to reset handler
Start executing the first
instruction
After the processor exits reset, it will read two
words from memory

78. Girish M, Asst. Professor 78
• This differs from traditional ARM processor behavior
• In the Cortex-M3, the initial value for the MSP is put at the
beginning of the memory map, followed by the vector
table, which contains vector address values
• Because the stack operation in the Cortex-M3 is a full
descending stack - initial SP value should be set to the
first memory after the top of the stack region

79. Initial Stack Pointer Value and Initial Program Counter Value
Example
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80. Memory Mapping
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The Cortex™-M3 processor has different memory architecture
from that of traditional ARM processors.
 First, it has a predefined memory map
 Another feature of the memory system in the Cortex-M3
is the bit-band support.
 The Cortex-M3 memory system also supports unaligned
transfers and exclusive accesses.
 Cortex-M3 supports both little endian and big endian
memory configuration.
Class 9

81. CODE
0.5GB0x00000000
0x1FFFFFFF
Mainly used for program code. Also
provides exception
vector table after power up
SRAM
0.5GB0x20000000
0x3FFFFFFF
Mainly used as static RAM
Peripherals
0.5GB0x40000000
0x5FFFFFFFF
External RAM
1GB0x60000000
0xA0000000
External device
1GB
0x9FFFFFFF
0xDFFFFFFF
System level
0.5GB0xE0000000
0xFFFFFFFF
Mainly used as external
memory
Mainly used as peripherals
Mainly used as external
peripherals
Private peripherals including
build-in interrupt controller
(NVIC), MPU control
registers, and debug components
4
G
B
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81

82. The Bus Interface
Allow the Cortex-M3 to carry instruction fetches and data
accesses at the same time
1. Code Memory Buses Accesses Code region
 I-Code
 D-Code.
2. System Bus Access (SRAM), peripherals, external RAM,
external devices, and part of the system level memory
regions.
3. Private Peripheral Bus Access to a part of the system-
level memory dedicated to private peripherals, such as
debugging components
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83. The Memory Protection Unit
• Allows to set the rules for privileged access and
user program access
• When an access rule is violated, a fault
exception is generated
• The MPU feature is optional
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84. The MPU can be used
To protect data use by the OS kernel and other
privileged processes from untrusted user programs
To make memory regions read-only, to prevent
accidental erasing of data
To isolate memory regions between different tasks
in a multitasking system
Help make embedded systems more robust and
reliable
Girish M, Asst. Professor 84

85. Debugging Support
The Cortex-M3 processor debugging features
• Program execution controls
• Halting and stepping
• Instruction breakpoints
• Data watch points
• Registers and memory accesses
• Profiling
• Traces
Girish M, Asst. Professor 85
Class 10

86. Debugging Support
• Unlike traditional ARM processors, the CPU core of
cortex M3 itself does not have JTAG Interface
• Debug Access Port (DAP) is provided at the core
level to provide an access to external debuggers,
control registers to debug hardware as well as
system memory, even when the processor is
running.
• The control of this bus interface is carried out by a
Debug Port (DP) device SWJ-DP
Girish M, Asst. Professor 86

87. Debugging Support
• When a debug event takes place, the Cortex-M3
processor can either enter halt mode or execute the
debug monitor exception handler.
• Data Watchpoint and Trace (DWT) unit perform
data watchpoint function  used to stop the
processor (or trigger the debug monitor exception
routine) or to generate data trace information
• When data trace is used, the traced data can be
output via the TPIU (Trace Port Interface Unit)
Girish M, Asst. Professor 87

88. Recommended Questions
Girish M, Asst. Professor 88
• Briefly describe the functions of the various units with the architectural block
diagram of ARM Cortex M3.
• Discuss the functions of R0 to R15 and other special registers in Cortex M3.
• Describe the functions of exceptions with a vector table and priorities.
• Explain the operation modes of Cortex M3 with diagrams
• Explain two stack model and reset sequence in ARM cortex M3.
• with a neat diagram explain the architecture of ARM Cortex-M3
Microcontroller
• Explain the Register Organizations of Cortex-M3.
• Explain the Stack operation using Push and Pop instructions in ARM Cortex
M3.
• Mention the instruction used for accessing the special registers. Explain the
same using suitable Examples
• Explain the operation modes and privilege levels in ARM Cortex M3 with a
neat transition diagram

89. THANK YOU……..
Girish M, Asst. Professor
89