The microcontroller-based system is currently having a tremendous boost with the revelation of platforms such as the Internet of Things. Low-end families of microcontroller architecture are still in demand albeit less technologically advanced due to its better I/O better application and control. However, there is clearly a lack of computational capability of the low-end architecture that will affect the pre-processing stage of the received data. The purpose of this research is to combine the best feature of an 8-bit microcontroller architecture together with the computationally complex operations without incurring extra resources. The modules’ integration is implemented using instruction set architecture (ISA) extension technique and is developed on the Field Programmable Gate Array (FPGA). Extensive simulations were performed with the and a comprehensive methodology is proposed. It was found that the ISA extension from 12-bit to 16-bit has produced a faster execution time with fewer resource utilization when implementing the bit-sorting algorithm. The overall development process used in this research is flexible enough for further investigation either by extending its module to more complex algorithms or evaluating other designs of its components.
EFFECTIVE EMBEDDED SYSTEMS SOFTWARE DESIGN METHODOLOGIEScscpconf
This paper gives Universities needs to improve their curriculum for Technology students to meet
the industry standards which will be helpful for their career .In the current improving
technologies studying of embedded system is required to understand the Electronic circuits .
They should include the new emerging technology such as multiprocessor system on chip where it is used in all the real time applications. In this paper design based tutorials will be discussed to understand Multiprocessor system on chip .The understanding of multiprocessor system on chip is difficult for a student and should be taught to meet the expectation from the industry. Since it is vast area, this paper proposes the most efficient tutoring method on multiprocessor system on chip.
An FPGA-based network system with service-uninterrupted remote functional upd...IJECEIAES
The recent emergence of 5G network enables mass wireless sensors deployment for internet-of-things (IoT) applications. In many cases, IoT sensors in monitoring and data collection applications are required to operate continuously and active at all time (24/7) to ensure all data are sampled without loss. Field-programmable gate array (FPGA)-based systems exhibit a balanced processing throughput and datapath flexibility. Specifically, datapath flexibility is acquired from the FPGA-based system architecture that supports dynamic partial reconfiguration feature. However, device functional update can cause interruption to the application servicing, especially in an FPGA-based system. This paper presents a standalone FPGA-based system architecture that allows remote functional update without causing service interruption by adopting a redundancy mechanism in the application datapath. By utilizing dynamic partial reconfiguration, only the updating datapath is temporarily inactive while the rest of the circuitry, including the redundant datapath, remain active. Hence, there is no service interruption and downtime when a remote functional update takes place due to the existence of redundant application datapath, which is critical for network and communication systems. The proposed architecture has a significant impact for application in FPGA-based systems that have little or no tolerance in service interruption.
High performance energy efficient multicore embedded computingAnkit Talele
The high-performance energy-efficient multicore embedded computing(HPEEC) domain addresses the unique design challenges of high-performance and low-power/energy embedded computing.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
ETHERNET PACKET PROCESSOR FOR SOC APPLICATIONcscpconf
As the demand for Internet expands significantly in numbers of users, servers, IP addresses,
switches and routers, the IP based network architecture must evolve and change. The design
of domain specific processors that require high performance, low power and high degree of
programmability is the bottleneck in many processor based applications. This paper describes
the design of ethernet packet processor for system-on-chip (SoC) which performs all core
packet processing functions, including segmentation and reassembly, packetization
classification, route and queue management which will speedup switching/routing
performance. Our design has been configured for use with multiple projects ttargeted to a
commercial configurable logic device the system is designed to support 10/100/1000 links with a speed advantage. VHDL has been used to implement and simulated the required functions in FPGA.
Dynamic HW Priority Queue Based Schedulers for Embedded System[ijesajournal
A real-time operating system (RTOs) is often used in embedded system, to structure the application code
and to ensure that the deadlines are met by reacting on events by executing the functions within precise
time. Most embedded systems are bound to real-time constraints with determinism and latency as a critical
metrics. RTOs are generally implemented in software, increases computational overheads, jitter and
memory footprint. Modern FPGA technology, enables the implementation of a full featured and flexible
hardware based RTOs, which helps in reducing to greater extent these overheads even if not remove
completely. Scheduling algorithms play an important role in the design of real-time systems. An Adaptive
Fuzzy Inference System (FIS) based scheduler framework proposed in this article is based on the study and
conclusion drawn from the research over the years in HW SW co-design domain. The proposed novel two
phase FIS based adaptive hardware task scheduler minimizes the processor time for scheduling activity
which uses fuzzy logic to model the uncertainty at first stage along with adaptive framework that uses
feedback which allows processors share of task running on multiprocessor to be controlled dynamically at
runtime. This Fuzzy logic based adaptive hardware scheduler breakthroughs the limit of the number of
total task and thus improves efficiency of the entire real-time system. The increased computation overheads
resulted from proposed two phase FIS scheduler can be compensated by utilising the basic characteristics
of parallelism of the hardware as scheduler being migrated to FPGA.
EFFECTIVE EMBEDDED SYSTEMS SOFTWARE DESIGN METHODOLOGIEScscpconf
This paper gives Universities needs to improve their curriculum for Technology students to meet
the industry standards which will be helpful for their career .In the current improving
technologies studying of embedded system is required to understand the Electronic circuits .
They should include the new emerging technology such as multiprocessor system on chip where it is used in all the real time applications. In this paper design based tutorials will be discussed to understand Multiprocessor system on chip .The understanding of multiprocessor system on chip is difficult for a student and should be taught to meet the expectation from the industry. Since it is vast area, this paper proposes the most efficient tutoring method on multiprocessor system on chip.
An FPGA-based network system with service-uninterrupted remote functional upd...IJECEIAES
The recent emergence of 5G network enables mass wireless sensors deployment for internet-of-things (IoT) applications. In many cases, IoT sensors in monitoring and data collection applications are required to operate continuously and active at all time (24/7) to ensure all data are sampled without loss. Field-programmable gate array (FPGA)-based systems exhibit a balanced processing throughput and datapath flexibility. Specifically, datapath flexibility is acquired from the FPGA-based system architecture that supports dynamic partial reconfiguration feature. However, device functional update can cause interruption to the application servicing, especially in an FPGA-based system. This paper presents a standalone FPGA-based system architecture that allows remote functional update without causing service interruption by adopting a redundancy mechanism in the application datapath. By utilizing dynamic partial reconfiguration, only the updating datapath is temporarily inactive while the rest of the circuitry, including the redundant datapath, remain active. Hence, there is no service interruption and downtime when a remote functional update takes place due to the existence of redundant application datapath, which is critical for network and communication systems. The proposed architecture has a significant impact for application in FPGA-based systems that have little or no tolerance in service interruption.
High performance energy efficient multicore embedded computingAnkit Talele
The high-performance energy-efficient multicore embedded computing(HPEEC) domain addresses the unique design challenges of high-performance and low-power/energy embedded computing.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
ETHERNET PACKET PROCESSOR FOR SOC APPLICATIONcscpconf
As the demand for Internet expands significantly in numbers of users, servers, IP addresses,
switches and routers, the IP based network architecture must evolve and change. The design
of domain specific processors that require high performance, low power and high degree of
programmability is the bottleneck in many processor based applications. This paper describes
the design of ethernet packet processor for system-on-chip (SoC) which performs all core
packet processing functions, including segmentation and reassembly, packetization
classification, route and queue management which will speedup switching/routing
performance. Our design has been configured for use with multiple projects ttargeted to a
commercial configurable logic device the system is designed to support 10/100/1000 links with a speed advantage. VHDL has been used to implement and simulated the required functions in FPGA.
Dynamic HW Priority Queue Based Schedulers for Embedded System[ijesajournal
A real-time operating system (RTOs) is often used in embedded system, to structure the application code
and to ensure that the deadlines are met by reacting on events by executing the functions within precise
time. Most embedded systems are bound to real-time constraints with determinism and latency as a critical
metrics. RTOs are generally implemented in software, increases computational overheads, jitter and
memory footprint. Modern FPGA technology, enables the implementation of a full featured and flexible
hardware based RTOs, which helps in reducing to greater extent these overheads even if not remove
completely. Scheduling algorithms play an important role in the design of real-time systems. An Adaptive
Fuzzy Inference System (FIS) based scheduler framework proposed in this article is based on the study and
conclusion drawn from the research over the years in HW SW co-design domain. The proposed novel two
phase FIS based adaptive hardware task scheduler minimizes the processor time for scheduling activity
which uses fuzzy logic to model the uncertainty at first stage along with adaptive framework that uses
feedback which allows processors share of task running on multiprocessor to be controlled dynamically at
runtime. This Fuzzy logic based adaptive hardware scheduler breakthroughs the limit of the number of
total task and thus improves efficiency of the entire real-time system. The increased computation overheads
resulted from proposed two phase FIS scheduler can be compensated by utilising the basic characteristics
of parallelism of the hardware as scheduler being migrated to FPGA.
System on Chip Based RTC in Power ElectronicsjournalBEEI
Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.
Ethernet Enabled Digital I/O Control in Embedded SystemsIOSR Journals
Abstract: This paper presents very simple and economical way to provide Ethernet connectivity to micro controller based embedded systems. This system uses arm7 controller to store the main application source code, web pages and TCP/IP stack which is a vital element of the system software. an Ethernet controller chip,ENC28J60 is used to handle the Ethernet controller chip.ENC28J60 is used to handle the Ethernet communications and is interfaced with the host micro controller using SPI pins. There are several I/O pins available at the micro controller which are used to interface with sensors and relays for monitoring and controlling operations. Now a day, internet has spread worldwide and most of the internet connections use Ethernet as media for data transfer. in industries or in home appliances ,most of the time we need to monitor and control different parameters using micro controllers. Once we enable Ethernet interface to such systems, we can communicate with them remotely over the internet Keywords:Ethernet controller; TCP/IP stack; serialperipheral interface (SPI),ENC28J60, Triac,Sensors
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Stable Ethernet TCP/IP Real Time Communication In Industrial Embedded Applica...IJRES Journal
A stable Ethernet communication link in industrial embedded applications and networking are possible at all levels of industrial automation, especially in the controller level whereby the data exchanges in real-time communication is mandatory. Designing a Robust and Reliable Industrial Communications Infrastructure with Ethernet has traditionally been used to network enterprise workstations and to transfer non-real-time data. The success of Ethernet in the desktop world has been due to its simplicity, expandability, robustness, and affordable implementation. Based on Ethernet’s success as a data network, embedded soft real-time communication networks are being implemented with standard 100 Mbit/s Ethernet for economy, familiarity, and compatibility with enterprise networks. By using TCP/IP on top of Ethernet, embedded systems can become globally accessible from enterprise networks. This connectivity and interoperability is possible, and affordable using commodity off-the shelf (COTS) hardware and software, which has led to a recent surge in interest in embedded Ethernet.
GSM Based Device Controlling and Fault DetectionIJCERT
The mobile communication has expanded to a great extent such that it can be applied for controlling of electrical devices. These projects make use of this capability of mobile phone to control three electrical devices with some use of embedded technology which can be extended up to eight devices. Apart from controlling it also does the sensing of the devices. Thus a user can be able to know of the status of the devices and in addition to that the user get notified if any fault is detected. Here in the project controlling and sensing is done for three electrical devices only. According to the user need both of this can be expanded.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
@SCADA+® is a comprehensive solution to supervisory control and data acquisition, managing system on a real-time basis. The solution is developed entirely on Client-Server architecture.
System on Chip Based RTC in Power ElectronicsjournalBEEI
Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.
Ethernet Enabled Digital I/O Control in Embedded SystemsIOSR Journals
Abstract: This paper presents very simple and economical way to provide Ethernet connectivity to micro controller based embedded systems. This system uses arm7 controller to store the main application source code, web pages and TCP/IP stack which is a vital element of the system software. an Ethernet controller chip,ENC28J60 is used to handle the Ethernet controller chip.ENC28J60 is used to handle the Ethernet communications and is interfaced with the host micro controller using SPI pins. There are several I/O pins available at the micro controller which are used to interface with sensors and relays for monitoring and controlling operations. Now a day, internet has spread worldwide and most of the internet connections use Ethernet as media for data transfer. in industries or in home appliances ,most of the time we need to monitor and control different parameters using micro controllers. Once we enable Ethernet interface to such systems, we can communicate with them remotely over the internet Keywords:Ethernet controller; TCP/IP stack; serialperipheral interface (SPI),ENC28J60, Triac,Sensors
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Stable Ethernet TCP/IP Real Time Communication In Industrial Embedded Applica...IJRES Journal
A stable Ethernet communication link in industrial embedded applications and networking are possible at all levels of industrial automation, especially in the controller level whereby the data exchanges in real-time communication is mandatory. Designing a Robust and Reliable Industrial Communications Infrastructure with Ethernet has traditionally been used to network enterprise workstations and to transfer non-real-time data. The success of Ethernet in the desktop world has been due to its simplicity, expandability, robustness, and affordable implementation. Based on Ethernet’s success as a data network, embedded soft real-time communication networks are being implemented with standard 100 Mbit/s Ethernet for economy, familiarity, and compatibility with enterprise networks. By using TCP/IP on top of Ethernet, embedded systems can become globally accessible from enterprise networks. This connectivity and interoperability is possible, and affordable using commodity off-the shelf (COTS) hardware and software, which has led to a recent surge in interest in embedded Ethernet.
GSM Based Device Controlling and Fault DetectionIJCERT
The mobile communication has expanded to a great extent such that it can be applied for controlling of electrical devices. These projects make use of this capability of mobile phone to control three electrical devices with some use of embedded technology which can be extended up to eight devices. Apart from controlling it also does the sensing of the devices. Thus a user can be able to know of the status of the devices and in addition to that the user get notified if any fault is detected. Here in the project controlling and sensing is done for three electrical devices only. According to the user need both of this can be expanded.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
@SCADA+® is a comprehensive solution to supervisory control and data acquisition, managing system on a real-time basis. The solution is developed entirely on Client-Server architecture.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
An octa core processor with shared memory and message-passingeSAT Journals
Abstract This being the era of fast, high performance computing, there is the need of having efficient optimizations in the processor architecture and at the same time in memory hierarchy too. Each and every day, the advancement of applications in communication and multimedia systems are compelling to increase number of cores in the main processor viz., dual-core, quad-core, octa-core and so on. But, for enhancing the overall performance of multi processor chip, there are stringent requirements to improve inter-core synchronization. Thus, a MPSoC with 8-cores supporting both message-passing and shared-memory inter-core communication mechanisms is implemented on Virtex 5 LX110T FPGA. Each core is based on MIPS III (Microprocessor without interlocked pipelined stages) ISA, handling only integer type instructions and having six-stage pipeline with data hazard detection unit and forwarding logic. The eight processing cores and one central shared memory core are inter connected using 3x3 2-D mesh topology based Network-on-chip (NoC) with virtual channel router. The router is four stage pipelined supporting DOR X-Y routing algorithm and with round robin arbitration technique. For verification and functionality test of above fully synthesized multi core processor, matrix multiplication operation is mapped onto the above said. Partitioning and scheduling of multiple multiplications and addition for each element of resultant matrix has been done accordingly among eight cores to get maximum throughput. All the codes for processor design are written in Verilog HDL. Keywords: MPSoC, message-passing, shared memory, MIPS, ISA, wormhole router, network-on-chip, SIMD, data level parallelism, 2-D Mesh, virtual channel
Fpga based 128 bit customised vliw processor for executing dual scalarvector ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Performance of State-of-the-Art Cryptography on ARM-based MicroprocessorsHannes Tschofenig
Position paper for the NIST Lightweight Cryptography Workshop, 20th and 21st July 2015, Gaithersburg, US.
The link to the workshop is available at: http://www.nist.gov/itl/csd/ct/lwc_workshop2015.cfm
The vast majority of embedded system designs start with a processor-based system, using a microcontroller or microprocessor as the core element to predict and process the basic control tasks. This paper aims to increase the reliability of controlling a stepper motor by an embedded circuit, which generates four digital signals of pulse width modulation (PWM). The manager of this circuit is an embedded processor licensed from Microblaze, which sits within the FPGA architecture Virtex 5. This processor analyzes the parameters to execute the rotation under the best conditions (energy consumption, speed, precision, and reliability). The communication with the PC takes place via the RS232 link to provide feedback. The autonomous processor generates an independent control frequency of the PC. The four digital signals of PWM are simulated on Xilinx's ISim interface and sent to the ULN2803 amplifier circuit to run the stepper motor.
Effect on Substation Engineering Costs of IEC61850 & System Configuration ToolsSchneider Electric
Change management, software configuration training, and human error all impact the cost associated with substation automation engineering. Object-oriented engineering approaches as defined in the IEC 61850 standard represent significant cost savings when compared to traditional methods using hardwire and Distributed Network Protocol (DNP3). New multivendor system configuration tools are described that further reduce substation automation engineering costs.
Remote temperature and humidity monitoring system using wireless sensor networkseSAT Journals
Abstract Today’s world has become very advanced with smart appliances and devices like laptops, tablets, televisions. smart phones with different features and their usage has been enormously increasing in our day-to-day life. The technology advancement in Digital Electronics and Micro Electro Mechanical Systems. In this scenario the most important role is played by Wireless Sensor Networks and its development and usage in heterogeneous fields and several contexts. the home automation field and process control systems and health control systems widely uses wireless sensor networks. Moreover with WSN we can monitor environments and its conditions also. We are designing a protocol to monitor the environmental temperature and humidity at different conditions. The architecture is simple to construct and ease to implement and also has an advantage of low power consumption. The aim of our paper to describe and show how to create a simple protocol for environment monitoring using a wireless development kit. we are using advanced technology of crossbow motes and NESC Language Programming. Keywords: Motes, WSN, sensor, TinyOS, Nesc.
Design and implementation of microcontroller in fpga for io tIJARIIT
One of the buzz words in the Information Technology is the Internet of Things (IoT). In coming years, IoT will
transform the objects which are present in the real world into virtual objects. IoT keep us informed about the status of objects
and controls of things in a sensor network. Sensor node comprises of the sensor, microcontroller and RF transceiver. A
microcontroller is an integrated circuit which basically performs one task and executes a particular application. It contains
programmable in/out peripherals, memory, and processor. Microcontrollers are mostly designed in view of embedded and are
used to automatically controllable systems. In digital system design microcontrollers and field programmable gate arrays
(FPGAs), both are widely used. Microcontroller based devices are becoming increasingly widespread. On one hand, high speed,
power, and falling prices make them an obvious choice whereas fast growing popularity of FPGAs, the availability of powerful
development tools and the increase in speed and high density have made FPGA based systems an alternative choice. Sensor node
controller is going to develop using VHDL with behavioral modeling which is an abstract model of the controller and breaks
down of the system into subcomponents and functional blocks.
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Run-Time Adaptive Processor Allocation of Self-Configurable Intel IXP2400 Net...CSCJournals
An ideal Network Processor, that is, a programmable multi-processor device must be capable of offering both the flexibility and speed required for packet processing. But current Network Processor systems generally fall short of the above benchmarks due to traffic fluctuations inherent in packet networks, and the resulting workload variation on individual pipeline stage over a period of time ultimately affects the overall performance of even an otherwise sound system. One potential solution would be to change the code running at these stages so as to adapt to the fluctuations; a near robust system with standing traffic fluctuations is the dynamic adaptive processor, reconfiguring the entire system, which we introduce and study to some extent in this paper. We achieve this by using a crucial decision making model, transferring the binary code to the processor through the SOAP protocol.
Bibliometric analysis highlighting the role of women in addressing climate ch...IJECEIAES
Fossil fuel consumption increased quickly, contributing to climate change
that is evident in unusual flooding and draughts, and global warming. Over
the past ten years, women's involvement in society has grown dramatically,
and they succeeded in playing a noticeable role in reducing climate change.
A bibliometric analysis of data from the last ten years has been carried out to
examine the role of women in addressing the climate change. The analysis's
findings discussed the relevant to the sustainable development goals (SDGs),
particularly SDG 7 and SDG 13. The results considered contributions made
by women in the various sectors while taking geographic dispersion into
account. The bibliometric analysis delves into topics including women's
leadership in environmental groups, their involvement in policymaking, their
contributions to sustainable development projects, and the influence of
gender diversity on attempts to mitigate climate change. This study's results
highlight how women have influenced policies and actions related to climate
change, point out areas of research deficiency and recommendations on how
to increase role of the women in addressing the climate change and
achieving sustainability. To achieve more successful results, this initiative
aims to highlight the significance of gender equality and encourage
inclusivity in climate change decision-making processes.
Voltage and frequency control of microgrid in presence of micro-turbine inter...IJECEIAES
The active and reactive load changes have a significant impact on voltage
and frequency. In this paper, in order to stabilize the microgrid (MG) against
load variations in islanding mode, the active and reactive power of all
distributed generators (DGs), including energy storage (battery), diesel
generator, and micro-turbine, are controlled. The micro-turbine generator is
connected to MG through a three-phase to three-phase matrix converter, and
the droop control method is applied for controlling the voltage and
frequency of MG. In addition, a method is introduced for voltage and
frequency control of micro-turbines in the transition state from gridconnected mode to islanding mode. A novel switching strategy of the matrix
converter is used for converting the high-frequency output voltage of the
micro-turbine to the grid-side frequency of the utility system. Moreover,
using the switching strategy, the low-order harmonics in the output current
and voltage are not produced, and consequently, the size of the output filter
would be reduced. In fact, the suggested control strategy is load-independent
and has no frequency conversion restrictions. The proposed approach for
voltage and frequency regulation demonstrates exceptional performance and
favorable response across various load alteration scenarios. The suggested
strategy is examined in several scenarios in the MG test systems, and the
simulation results are addressed.
Enhancing battery system identification: nonlinear autoregressive modeling fo...IJECEIAES
Precisely characterizing Li-ion batteries is essential for optimizing their
performance, enhancing safety, and prolonging their lifespan across various
applications, such as electric vehicles and renewable energy systems. This
article introduces an innovative nonlinear methodology for system
identification of a Li-ion battery, employing a nonlinear autoregressive with
exogenous inputs (NARX) model. The proposed approach integrates the
benefits of nonlinear modeling with the adaptability of the NARX structure,
facilitating a more comprehensive representation of the intricate
electrochemical processes within the battery. Experimental data collected
from a Li-ion battery operating under diverse scenarios are employed to
validate the effectiveness of the proposed methodology. The identified
NARX model exhibits superior accuracy in predicting the battery's behavior
compared to traditional linear models. This study underscores the
importance of accounting for nonlinearities in battery modeling, providing
insights into the intricate relationships between state-of-charge, voltage, and
current under dynamic conditions.
Smart grid deployment: from a bibliometric analysis to a surveyIJECEIAES
Smart grids are one of the last decades' innovations in electrical energy.
They bring relevant advantages compared to the traditional grid and
significant interest from the research community. Assessing the field's
evolution is essential to propose guidelines for facing new and future smart
grid challenges. In addition, knowing the main technologies involved in the
deployment of smart grids (SGs) is important to highlight possible
shortcomings that can be mitigated by developing new tools. This paper
contributes to the research trends mentioned above by focusing on two
objectives. First, a bibliometric analysis is presented to give an overview of
the current research level about smart grid deployment. Second, a survey of
the main technological approaches used for smart grid implementation and
their contributions are highlighted. To that effect, we searched the Web of
Science (WoS), and the Scopus databases. We obtained 5,663 documents
from WoS and 7,215 from Scopus on smart grid implementation or
deployment. With the extraction limitation in the Scopus database, 5,872 of
the 7,215 documents were extracted using a multi-step process. These two
datasets have been analyzed using a bibliometric tool called bibliometrix.
The main outputs are presented with some recommendations for future
research.
Use of analytical hierarchy process for selecting and prioritizing islanding ...IJECEIAES
One of the problems that are associated to power systems is islanding
condition, which must be rapidly and properly detected to prevent any
negative consequences on the system's protection, stability, and security.
This paper offers a thorough overview of several islanding detection
strategies, which are divided into two categories: classic approaches,
including local and remote approaches, and modern techniques, including
techniques based on signal processing and computational intelligence.
Additionally, each approach is compared and assessed based on several
factors, including implementation costs, non-detected zones, declining
power quality, and response times using the analytical hierarchy process
(AHP). The multi-criteria decision-making analysis shows that the overall
weight of passive methods (24.7%), active methods (7.8%), hybrid methods
(5.6%), remote methods (14.5%), signal processing-based methods (26.6%),
and computational intelligent-based methods (20.8%) based on the
comparison of all criteria together. Thus, it can be seen from the total weight
that hybrid approaches are the least suitable to be chosen, while signal
processing-based methods are the most appropriate islanding detection
method to be selected and implemented in power system with respect to the
aforementioned factors. Using Expert Choice software, the proposed
hierarchy model is studied and examined.
Enhancing of single-stage grid-connected photovoltaic system using fuzzy logi...IJECEIAES
The power generated by photovoltaic (PV) systems is influenced by
environmental factors. This variability hampers the control and utilization of
solar cells' peak output. In this study, a single-stage grid-connected PV
system is designed to enhance power quality. Our approach employs fuzzy
logic in the direct power control (DPC) of a three-phase voltage source
inverter (VSI), enabling seamless integration of the PV connected to the
grid. Additionally, a fuzzy logic-based maximum power point tracking
(MPPT) controller is adopted, which outperforms traditional methods like
incremental conductance (INC) in enhancing solar cell efficiency and
minimizing the response time. Moreover, the inverter's real-time active and
reactive power is directly managed to achieve a unity power factor (UPF).
The system's performance is assessed through MATLAB/Simulink
implementation, showing marked improvement over conventional methods,
particularly in steady-state and varying weather conditions. For solar
irradiances of 500 and 1,000 W/m2
, the results show that the proposed
method reduces the total harmonic distortion (THD) of the injected current
to the grid by approximately 46% and 38% compared to conventional
methods, respectively. Furthermore, we compare the simulation results with
IEEE standards to evaluate the system's grid compatibility.
Enhancing photovoltaic system maximum power point tracking with fuzzy logic-b...IJECEIAES
Photovoltaic systems have emerged as a promising energy resource that
caters to the future needs of society, owing to their renewable, inexhaustible,
and cost-free nature. The power output of these systems relies on solar cell
radiation and temperature. In order to mitigate the dependence on
atmospheric conditions and enhance power tracking, a conventional
approach has been improved by integrating various methods. To optimize
the generation of electricity from solar systems, the maximum power point
tracking (MPPT) technique is employed. To overcome limitations such as
steady-state voltage oscillations and improve transient response, two
traditional MPPT methods, namely fuzzy logic controller (FLC) and perturb
and observe (P&O), have been modified. This research paper aims to
simulate and validate the step size of the proposed modified P&O and FLC
techniques within the MPPT algorithm using MATLAB/Simulink for
efficient power tracking in photovoltaic systems.
Adaptive synchronous sliding control for a robot manipulator based on neural ...IJECEIAES
Robot manipulators have become important equipment in production lines, medical fields, and transportation. Improving the quality of trajectory tracking for
robot hands is always an attractive topic in the research community. This is a
challenging problem because robot manipulators are complex nonlinear systems
and are often subject to fluctuations in loads and external disturbances. This
article proposes an adaptive synchronous sliding control scheme to improve trajectory tracking performance for a robot manipulator. The proposed controller
ensures that the positions of the joints track the desired trajectory, synchronize
the errors, and significantly reduces chattering. First, the synchronous tracking
errors and synchronous sliding surfaces are presented. Second, the synchronous
tracking error dynamics are determined. Third, a robust adaptive control law is
designed,the unknown components of the model are estimated online by the neural network, and the parameters of the switching elements are selected by fuzzy
logic. The built algorithm ensures that the tracking and approximation errors
are ultimately uniformly bounded (UUB). Finally, the effectiveness of the constructed algorithm is demonstrated through simulation and experimental results.
Simulation and experimental results show that the proposed controller is effective with small synchronous tracking errors, and the chattering phenomenon is
significantly reduced.
Remote field-programmable gate array laboratory for signal acquisition and de...IJECEIAES
A remote laboratory utilizing field-programmable gate array (FPGA) technologies enhances students’ learning experience anywhere and anytime in embedded system design. Existing remote laboratories prioritize hardware access and visual feedback for observing board behavior after programming, neglecting comprehensive debugging tools to resolve errors that require internal signal acquisition. This paper proposes a novel remote embeddedsystem design approach targeting FPGA technologies that are fully interactive via a web-based platform. Our solution provides FPGA board access and debugging capabilities beyond the visual feedback provided by existing remote laboratories. We implemented a lab module that allows users to seamlessly incorporate into their FPGA design. The module minimizes hardware resource utilization while enabling the acquisition of a large number of data samples from the signal during the experiments by adaptively compressing the signal prior to data transmission. The results demonstrate an average compression ratio of 2.90 across three benchmark signals, indicating efficient signal acquisition and effective debugging and analysis. This method allows users to acquire more data samples than conventional methods. The proposed lab allows students to remotely test and debug their designs, bridging the gap between theory and practice in embedded system design.
Detecting and resolving feature envy through automated machine learning and m...IJECEIAES
Efficiently identifying and resolving code smells enhances software project quality. This paper presents a novel solution, utilizing automated machine learning (AutoML) techniques, to detect code smells and apply move method refactoring. By evaluating code metrics before and after refactoring, we assessed its impact on coupling, complexity, and cohesion. Key contributions of this research include a unique dataset for code smell classification and the development of models using AutoGluon for optimal performance. Furthermore, the study identifies the top 20 influential features in classifying feature envy, a well-known code smell, stemming from excessive reliance on external classes. We also explored how move method refactoring addresses feature envy, revealing reduced coupling and complexity, and improved cohesion, ultimately enhancing code quality. In summary, this research offers an empirical, data-driven approach, integrating AutoML and move method refactoring to optimize software project quality. Insights gained shed light on the benefits of refactoring on code quality and the significance of specific features in detecting feature envy. Future research can expand to explore additional refactoring techniques and a broader range of code metrics, advancing software engineering practices and standards.
Smart monitoring technique for solar cell systems using internet of things ba...IJECEIAES
Rapidly and remotely monitoring and receiving the solar cell systems status parameters, solar irradiance, temperature, and humidity, are critical issues in enhancement their efficiency. Hence, in the present article an improved smart prototype of internet of things (IoT) technique based on embedded system through NodeMCU ESP8266 (ESP-12E) was carried out experimentally. Three different regions at Egypt; Luxor, Cairo, and El-Beheira cities were chosen to study their solar irradiance profile, temperature, and humidity by the proposed IoT system. The monitoring data of solar irradiance, temperature, and humidity were live visualized directly by Ubidots through hypertext transfer protocol (HTTP) protocol. The measured solar power radiation in Luxor, Cairo, and El-Beheira ranged between 216-1000, 245-958, and 187-692 W/m 2 respectively during the solar day. The accuracy and rapidity of obtaining monitoring results using the proposed IoT system made it a strong candidate for application in monitoring solar cell systems. On the other hand, the obtained solar power radiation results of the three considered regions strongly candidate Luxor and Cairo as suitable places to build up a solar cells system station rather than El-Beheira.
An efficient security framework for intrusion detection and prevention in int...IJECEIAES
Over the past few years, the internet of things (IoT) has advanced to connect billions of smart devices to improve quality of life. However, anomalies or malicious intrusions pose several security loopholes, leading to performance degradation and threat to data security in IoT operations. Thereby, IoT security systems must keep an eye on and restrict unwanted events from occurring in the IoT network. Recently, various technical solutions based on machine learning (ML) models have been derived towards identifying and restricting unwanted events in IoT. However, most ML-based approaches are prone to miss-classification due to inappropriate feature selection. Additionally, most ML approaches applied to intrusion detection and prevention consider supervised learning, which requires a large amount of labeled data to be trained. Consequently, such complex datasets are impossible to source in a large network like IoT. To address this problem, this proposed study introduces an efficient learning mechanism to strengthen the IoT security aspects. The proposed algorithm incorporates supervised and unsupervised approaches to improve the learning models for intrusion detection and mitigation. Compared with the related works, the experimental outcome shows that the model performs well in a benchmark dataset. It accomplishes an improved detection accuracy of approximately 99.21%.
Developing a smart system for infant incubators using the internet of things ...IJECEIAES
This research is developing an incubator system that integrates the internet of things and artificial intelligence to improve care for premature babies. The system workflow starts with sensors that collect data from the incubator. Then, the data is sent in real-time to the internet of things (IoT) broker eclipse mosquito using the message queue telemetry transport (MQTT) protocol version 5.0. After that, the data is stored in a database for analysis using the long short-term memory network (LSTM) method and displayed in a web application using an application programming interface (API) service. Furthermore, the experimental results produce as many as 2,880 rows of data stored in the database. The correlation coefficient between the target attribute and other attributes ranges from 0.23 to 0.48. Next, several experiments were conducted to evaluate the model-predicted value on the test data. The best results are obtained using a two-layer LSTM configuration model, each with 60 neurons and a lookback setting 6. This model produces an R 2 value of 0.934, with a root mean square error (RMSE) value of 0.015 and a mean absolute error (MAE) of 0.008. In addition, the R 2 value was also evaluated for each attribute used as input, with a result of values between 0.590 and 0.845.
A review on internet of things-based stingless bee's honey production with im...IJECEIAES
Honey is produced exclusively by honeybees and stingless bees which both are well adapted to tropical and subtropical regions such as Malaysia. Stingless bees are known for producing small amounts of honey and are known for having a unique flavor profile. Problem identified that many stingless bees collapsed due to weather, temperature and environment. It is critical to understand the relationship between the production of stingless bee honey and environmental conditions to improve honey production. Thus, this paper presents a review on stingless bee's honey production and prediction modeling. About 54 previous research has been analyzed and compared in identifying the research gaps. A framework on modeling the prediction of stingless bee honey is derived. The result presents the comparison and analysis on the internet of things (IoT) monitoring systems, honey production estimation, convolution neural networks (CNNs), and automatic identification methods on bee species. It is identified based on image detection method the top best three efficiency presents CNN is at 98.67%, densely connected convolutional networks with YOLO v3 is 97.7%, and DenseNet201 convolutional networks 99.81%. This study is significant to assist the researcher in developing a model for predicting stingless honey produced by bee's output, which is important for a stable economy and food security.
A trust based secure access control using authentication mechanism for intero...IJECEIAES
The internet of things (IoT) is a revolutionary innovation in many aspects of our society including interactions, financial activity, and global security such as the military and battlefield internet. Due to the limited energy and processing capacity of network devices, security, energy consumption, compatibility, and device heterogeneity are the long-term IoT problems. As a result, energy and security are critical for data transmission across edge and IoT networks. Existing IoT interoperability techniques need more computation time, have unreliable authentication mechanisms that break easily, lose data easily, and have low confidentiality. In this paper, a key agreement protocol-based authentication mechanism for IoT devices is offered as a solution to this issue. This system makes use of information exchange, which must be secured to prevent access by unauthorized users. Using a compact contiki/cooja simulator, the performance and design of the suggested framework are validated. The simulation findings are evaluated based on detection of malicious nodes after 60 minutes of simulation. The suggested trust method, which is based on privacy access control, reduced packet loss ratio to 0.32%, consumed 0.39% power, and had the greatest average residual energy of 0.99 mJoules at 10 nodes.
Fuzzy linear programming with the intuitionistic polygonal fuzzy numbersIJECEIAES
In real world applications, data are subject to ambiguity due to several factors; fuzzy sets and fuzzy numbers propose a great tool to model such ambiguity. In case of hesitation, the complement of a membership value in fuzzy numbers can be different from the non-membership value, in which case we can model using intuitionistic fuzzy numbers as they provide flexibility by defining both a membership and a non-membership functions. In this article, we consider the intuitionistic fuzzy linear programming problem with intuitionistic polygonal fuzzy numbers, which is a generalization of the previous polygonal fuzzy numbers found in the literature. We present a modification of the simplex method that can be used to solve any general intuitionistic fuzzy linear programming problem after approximating the problem by an intuitionistic polygonal fuzzy number with n edges. This method is given in a simple tableau formulation, and then applied on numerical examples for clarity.
The performance of artificial intelligence in prostate magnetic resonance im...IJECEIAES
Prostate cancer is the predominant form of cancer observed in men worldwide. The application of magnetic resonance imaging (MRI) as a guidance tool for conducting biopsies has been established as a reliable and well-established approach in the diagnosis of prostate cancer. The diagnostic performance of MRI-guided prostate cancer diagnosis exhibits significant heterogeneity due to the intricate and multi-step nature of the diagnostic pathway. The development of artificial intelligence (AI) models, specifically through the utilization of machine learning techniques such as deep learning, is assuming an increasingly significant role in the field of radiology. In the realm of prostate MRI, a considerable body of literature has been dedicated to the development of various AI algorithms. These algorithms have been specifically designed for tasks such as prostate segmentation, lesion identification, and classification. The overarching objective of these endeavors is to enhance diagnostic performance and foster greater agreement among different observers within MRI scans for the prostate. This review article aims to provide a concise overview of the application of AI in the field of radiology, with a specific focus on its utilization in prostate MRI.
Seizure stage detection of epileptic seizure using convolutional neural networksIJECEIAES
According to the World Health Organization (WHO), seventy million individuals worldwide suffer from epilepsy, a neurological disorder. While electroencephalography (EEG) is crucial for diagnosing epilepsy and monitoring the brain activity of epilepsy patients, it requires a specialist to examine all EEG recordings to find epileptic behavior. This procedure needs an experienced doctor, and a precise epilepsy diagnosis is crucial for appropriate treatment. To identify epileptic seizures, this study employed a convolutional neural network (CNN) based on raw scalp EEG signals to discriminate between preictal, ictal, postictal, and interictal segments. The possibility of these characteristics is explored by examining how well timedomain signals work in the detection of epileptic signals using intracranial Freiburg Hospital (FH), scalp Children's Hospital Boston-Massachusetts Institute of Technology (CHB-MIT) databases, and Temple University Hospital (TUH) EEG. To test the viability of this approach, two types of experiments were carried out. Firstly, binary class classification (preictal, ictal, postictal each versus interictal) and four-class classification (interictal versus preictal versus ictal versus postictal). The average accuracy for stage detection using CHB-MIT database was 84.4%, while the Freiburg database's time-domain signals had an accuracy of 79.7% and the highest accuracy of 94.02% for classification in the TUH EEG database when comparing interictal stage to preictal stage.
Analysis of driving style using self-organizing maps to analyze driver behaviorIJECEIAES
Modern life is strongly associated with the use of cars, but the increase in acceleration speeds and their maneuverability leads to a dangerous driving style for some drivers. In these conditions, the development of a method that allows you to track the behavior of the driver is relevant. The article provides an overview of existing methods and models for assessing the functioning of motor vehicles and driver behavior. Based on this, a combined algorithm for recognizing driving style is proposed. To do this, a set of input data was formed, including 20 descriptive features: About the environment, the driver's behavior and the characteristics of the functioning of the car, collected using OBD II. The generated data set is sent to the Kohonen network, where clustering is performed according to driving style and degree of danger. Getting the driving characteristics into a particular cluster allows you to switch to the private indicators of an individual driver and considering individual driving characteristics. The application of the method allows you to identify potentially dangerous driving styles that can prevent accidents.
Hyperspectral object classification using hybrid spectral-spatial fusion and ...IJECEIAES
Because of its spectral-spatial and temporal resolution of greater areas, hyperspectral imaging (HSI) has found widespread application in the field of object classification. The HSI is typically used to accurately determine an object's physical characteristics as well as to locate related objects with appropriate spectral fingerprints. As a result, the HSI has been extensively applied to object identification in several fields, including surveillance, agricultural monitoring, environmental research, and precision agriculture. However, because of their enormous size, objects require a lot of time to classify; for this reason, both spectral and spatial feature fusion have been completed. The existing classification strategy leads to increased misclassification, and the feature fusion method is unable to preserve semantic object inherent features; This study addresses the research difficulties by introducing a hybrid spectral-spatial fusion (HSSF) technique to minimize feature size while maintaining object intrinsic qualities; Lastly, a soft-margins kernel is proposed for multi-layer deep support vector machine (MLDSVM) to reduce misclassification. The standard Indian pines dataset is used for the experiment, and the outcome demonstrates that the HSSF-MLDSVM model performs substantially better in terms of accuracy and Kappa coefficient.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
Courier management system project report.pdfKamal Acharya
It is now-a-days very important for the people to send or receive articles like imported furniture, electronic items, gifts, business goods and the like. People depend vastly on different transport systems which mostly use the manual way of receiving and delivering the articles. There is no way to track the articles till they are received and there is no way to let the customer know what happened in transit, once he booked some articles. In such a situation, we need a system which completely computerizes the cargo activities including time to time tracking of the articles sent. This need is fulfilled by Courier Management System software which is online software for the cargo management people that enables them to receive the goods from a source and send them to a required destination and track their status from time to time.
Vaccine management system project report documentation..pdfKamal Acharya
The Division of Vaccine and Immunization is facing increasing difficulty monitoring vaccines and other commodities distribution once they have been distributed from the national stores. With the introduction of new vaccines, more challenges have been anticipated with this additions posing serious threat to the already over strained vaccine supply chain system in Kenya.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
NO1 Uk best vashikaran specialist in delhi vashikaran baba near me online vas...Amil Baba Dawood bangali
Contact with Dawood Bhai Just call on +92322-6382012 and we'll help you. We'll solve all your problems within 12 to 24 hours and with 101% guarantee and with astrology systematic. If you want to take any personal or professional advice then also you can call us on +92322-6382012 , ONLINE LOVE PROBLEM & Other all types of Daily Life Problem's.Then CALL or WHATSAPP us on +92322-6382012 and Get all these problems solutions here by Amil Baba DAWOOD BANGALI
#vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore#blackmagicformarriage #aamilbaba #kalajadu #kalailam #taweez #wazifaexpert #jadumantar #vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore #blackmagicforlove #blackmagicformarriage #aamilbaba #kalajadu #kalailam #taweez #wazifaexpert #jadumantar #vashikaranspecialist #astrologer #palmistry #amliyaat #taweez #manpasandshadi #horoscope #spiritual #lovelife #lovespell #marriagespell#aamilbabainpakistan #amilbabainkarachi #powerfullblackmagicspell #kalajadumantarspecialist #realamilbaba #AmilbabainPakistan #astrologerincanada #astrologerindubai #lovespellsmaster #kalajaduspecialist #lovespellsthatwork #aamilbabainlahore #Amilbabainuk #amilbabainspain #amilbabaindubai #Amilbabainnorway #amilbabainkrachi #amilbabainlahore #amilbabaingujranwalan #amilbabainislamabad
Democratizing Fuzzing at Scale by Abhishek Aryaabh.arya
Presented at NUS: Fuzzing and Software Security Summer School 2024
This keynote talks about the democratization of fuzzing at scale, highlighting the collaboration between open source communities, academia, and industry to advance the field of fuzzing. It delves into the history of fuzzing, the development of scalable fuzzing platforms, and the empowerment of community-driven research. The talk will further discuss recent advancements leveraging AI/ML and offer insights into the future evolution of the fuzzing landscape.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Automobile Management System Project Report.pdfKamal Acharya
The proposed project is developed to manage the automobile in the automobile dealer company. The main module in this project is login, automobile management, customer management, sales, complaints and reports. The first module is the login. The automobile showroom owner should login to the project for usage. The username and password are verified and if it is correct, next form opens. If the username and password are not correct, it shows the error message.
When a customer search for a automobile, if the automobile is available, they will be taken to a page that shows the details of the automobile including automobile name, automobile ID, quantity, price etc. “Automobile Management System” is useful for maintaining automobiles, customers effectively and hence helps for establishing good relation between customer and automobile organization. It contains various customized modules for effectively maintaining automobiles and stock information accurately and safely.
When the automobile is sold to the customer, stock will be reduced automatically. When a new purchase is made, stock will be increased automatically. While selecting automobiles for sale, the proposed software will automatically check for total number of available stock of that particular item, if the total stock of that particular item is less than 5, software will notify the user to purchase the particular item.
Also when the user tries to sale items which are not in stock, the system will prompt the user that the stock is not enough. Customers of this system can search for a automobile; can purchase a automobile easily by selecting fast. On the other hand the stock of automobiles can be maintained perfectly by the automobile shop manager overcoming the drawbacks of existing system.
2. ISSN: 2088-8708
Int J Elec & Comp Eng, Vol. 8, No. 4, August 2018 : 2595 – 2601
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important to note that most of the data processing tasks in an IoT system are executed in the cloud server
while the IoT board only responsible for data acquisition. The IoT board is connected to various sensors and
minimal pre-processing tasks are required before the data are relayed to the cloud server through the internet
connection. As the IoT device transmits its data serially in a protocol, having an optimized 8-bit architecture
would suit the requirement of the IoT board better than the 32-bit architecture, without all the unnecessarily
peripherals that are integrated into the 32-bit architecture.
A soft-core processor is a microprocessor fully described in software which can be synthesized in
programmable hardware, such as FPGAs. Soft-core processors implemented in FPGAs can be easily
customized to the needs of a specific target application. A microprocessor defined in software code usually in
hardware description language (HDL). As the processors are available in programming code, the developers
are able to modify and reuse pre-designed hardware components in the form of intellectual property (IP)
cores. This method would reduce design time at the expense of area and performance penalty.
In general, having a soft-core processor provide several advantages in embedded system
development. Soft-core processors have a higher level of abstraction that makes it easier to understand.
Flexibility is also offered to the developer that enable the core to be edited and changed the parameters.
Notable applications of the soft-core processor are in motor control system [4], pulse width modulation
(PWM) generation [5] and cryptographic algorithm [6]. However, there is very little detail of the
implementation and choices made during the development process i.e. design decisions and performance
trade-off [7], [8]. There is the need to established a methodology that promotes incremental design
improvement for a system that is based on the soft-core processor.
UTeMRISC0 [9, 10] is a softcore processor that is essentially based on the PIC architecture, that is
also the fundamental architecture of several other soft-core processors previously mentioned in this thesis.
The UTeMRISC0 soft-core processor was first introduced in [11] as a part of the experimental setup to
maximise the capability in delivering highest performance achievable by a processor core compared to their
physical IC counterpart. The previous PIC-based soft-core processors are heavily reliant to the MPlab to
compile and generate the processor’s bit file. For UTeMRISC0 processor, a retargetable assembler is
designed exclusively from the ground up to replace the MPlab as the de-facto assembler. In the early phase,
the assembler is designed to match the existing instruction set in the PIC data sheet within a simulated
computer architecture environment called the CPUSim.
One of the prominent paper with regards to the instruction set extension on reconfigurable
processors was published by [12]. The overall target for manipulating the instruction set is to achieve higher
parallelism to the instruction execution. Over the years, different techniques to increase the level of
parallelism have been introduced at instruction level: for instance, techniques such as instruction pipelining,
superscalar execution, out-of-order execution, and register renaming. Parallelism has also been exploited at
other levels: bit-level, data-level, and loop-level parallelism. Although the level of parallelism has been
increased over the years, it is still relatively limited for highly parallelizable applications, which become poor
candidates for implementation of these architectures.
2. RESEARCH METHOD
The instruction set extension technique applied in this research is not necessarily focused on adding
new instructions to the instruction set [13]. It is also could encompass modification to the current instruction,
altering the behavior of the available instruction to perform a command that is totally different from its
original purpose and also omitting the unrelated instructions that are not involved in the specific application.
These customizations are done through manual configuration [14].
Manual extensions involved a degree of human effort to identify and implement the instruction set
extensions. Human ingenuity in the manual creation of custom capabilities creates high-quality results which
within the context of the application’s result. As the design grows more complex and constraint on the time-
to-market requirement, automatic design flow is desirable for the use of these new capabilities. For a large set
of instruction candidates, selection of multiple custom instructions involves complex trade-off and can be
hard to execute manually. However, as this research is focusing on low-end digital signal controller platform,
the custom instructions that are manually identified and created. These instructions are considered sufficient
to perform DSP tasks successfully within the hardware limitation.
2.1. 12-bit ISA to 16-bit ISA
Using the original 12-bit ISA [15] as the reference point, the ISA is extended to become 16-bit in
width that in the end becomes the configured ISA for the UTeMRISC01 microcontroller. The customized
instruction set is created by expanding the available instruction tokens to vacate more space to execute more
data-transfer tasks such as register swapping. Figure 1 shows the instruction format for both the 12-bit ISA
3. Int J Elec & Comp Eng ISSN: 2088-8708
Instruction Set Extension of a Low-End Reconfigurable Microcontroller in Bit-Sorting … (Sani Irwan)
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and the 16-bit ISA with three different modes; (1) Literal operation, (2) byte-oriented operation with
direction and (3) bit-oriented operations.
The new 16-bit ISA now comprised of 6-bit of the opcode and 10 bits of the operand. The total
number of 16 is chosen as it is byte addressable and could easily accommodate more bits for future
expansion. Opcode bit is set to 6 bits that could stretch the maximum number of instructions to up to 64
instructions. The file register address is extended to 7 bits that enable theoretically up to 128 registers that
can be addressed by each instruction. The literal value maintained at 8-bit of raw data with a 3-bit select bit
to point to any position in the 8-bit data. Finally, the single directional bit is used to indicate the destination
of the data either to the working register or the register that is addressed in the operand. Technically, the
16-bit ISA provide the best setup for the low-end digital signal controller whereby there a lot of room to
exploit in adding new instructions, expanding the number of registers and also offered extra bits for literal
values for precision and sign extended data.
(1)
(2)
(3)
(a) (b)
Figure 1. Conversions from 12-bit ISA in (a) to 16-bit ISA in (b) for all instruction types
Compiler generator or retargetable code generator is used to synthesize code for the particular
applications. Once the instruction set is generated, the retargetable assembler is developed to accommodate
all changes made in the instruction set. The assembler then is responsible to decode and generate the object
code of the program based on the new instruction set [16]-[18].
2.2. Workflow and related tools
Specific tasks and procedures are followed to ensure smooth transactions as well as getting the right
tools. The UTeMRISC01 processor is implemented in the Xilinx ML605 FPGA board and the retargetable
assembler is developed from the ground up using the Visual Basic software by Microsoft. Once
implemented, the performance parameters such as resource utilization and the execution times are obtained
through the synthesis and Post-PAR timing report. Further measurements are also conducted using the logic
analyzer to verify the execution times of the bit-sorting program.
During the early phases of the design, the new instruction is tested and simulated using the CPUSim
software. CPU Sim is a Java application that allows users to design simple computer CPUs at the microcode
level and to run the machine-language or the assembly-language programs on those CPUs through
simulation [19].
The tools used in the hardware implementation phase are exclusively done on Xilinx environment,
including its Integrated Synthesis Environment (ISE) Design Suite. The Xilinx ISE Design Suite is
responsible for the bulk of the work by providing the tools to develop HDL modules in the processor
architecture. The behavioral simulations are completed by using the ISE simulators, also known as ISim,
which its main purpose is to perform functional and timing simulations for Verilog designs. Xilinx ISE will
perform the logic synthesis and design implementation to generate the bit file. Using a software called
iMPACT (integrated with the Xilinx ISE), the bit file is configured and loaded to the FPGA board, in this
case, the ML605 FPGA board).
2.3. Bit-sorting algorithm
There are various methods of sorting, such as interchange or bubble sort, shell sort, bucket sort and
radix interchange sort. Bubble sort is one of the popular methods, although the execution is not very efficient.
The key idea of bubble sort is to take adjacent pairs of elements in the list of data and put them in order by
interchanging their positions when it is necessary. By continuously executing the interchanging operations,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(a) x x k k k k k k k k
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(b) f f f f f f f x x d
direction
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(c) f f f f f f f b b b
opcode
file register (f)
bit (b)file register (f)
opcode literal (k)
opcode
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the data are sorted ascendingly within the data range. Figure 2 shows the step-by-step implementation flow of
the bit sorting algorithm.
Start
Set numbers
to be sorted
Set the starting
address
Compare value with
the adjacent address
Less than?
Set next
number
Swap value and
interchange address
End of entire array?
Re-check each
array value?
End
N
Y
Y
N
Y
N
Figure 2. Flowchart for bit-sorting algorithm
3. RESULTS AND ANALYSIS
Establishing the benchmark of the soft-core processor is vital at this stage. The performance
parameters for the modified architecture are evaluated and compared with the performance of the original
processor architecture. In this case, the 8-bit soft-core processor called UTeMRISC0 resemble greatly to its
packaged-IC counterpart which is the PIC16C57. The UTeMRISC0 will be the starting point for the
architecture expansion and modification.
The instruction set architecture extension is performed on the UTeMRISC0 architecture. Originally,
the ISA consisted of 12-bit and is expanded to become 16-bit. The expansion does not solely involve the
lengthening of the ISA register. It also required further modifications to other modules and registers such as
the instruction decoder module, the ROM module and instruction registers. New opcodes are also assigned to
the instruction set. At this point, the original list of instruction is maintained as per original while a single
new instruction called ‘swapfw’ is created to demonstrate the capability of the architecture in handling and
executing the new instruction. To reflect the major changes being made due to the ISA expansion, the
modified processor now is called UTeMRISC01 [20], [21].
3.1. Instruction set generation
A new instruction is created and called ‘swapfw’ that would take both of its operands as register
address. To optimize the instruction set, the ‘swapfw’ instruction would occupy the space for another
instruction called ‘movf f,1’. Originally, this instruction only functions to transfer data from a register back to
its own address which it impractical unless a certain condition bit is required to be generated. Therefore, the
new ‘swapfw’ instruction is assigned to the previous opcode allocation but now with different function, as
shown in Table 1.
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Table 1. New Instruction for Bit-Sorting
CPU Sim
Format 16-bit Opcode
Opcode Mnemonics
0B swapfw f 6 7 -3 0010_11ff_ffff_fxxx
3.2. Code synthesis
Referring to Figure 3, the new instruction the is simulated using the CPUSim software with the
UTeMRISC01 architecture is loaded as the main processor execution. The new instruction’s micro-operation
is defined in this process to iterate the sequence of the instruction execution.
Figure 3. Machine instruction editing in CPUSim
3.3. Hardware synthesis
The findings from the code synthesis stage are brought forward to the FPGA implementation by
replicating the instruction execution sequence, this time in Verilog code. The instruction’s opcode and ISA
are updated in the instruction decoder and ALU module. Once the architecture is successfully synthesized
and implemented, the performance parameters are observed and measured using the logic analyzer.
When the UTeMRISC01 architecture is implemented for the bit-sorting program, an increase of
registers and LUTs have been recorded. As the UTeMRISC01 are equipped with the new ISA and an
improved instruction register, the increase in the slice register number is expected, as shown in Table 2.
Further optimization of the ALU module, especially in reducing the redundant instructions also contributed
to a smaller usage of slice LUTs. For the bit sorting program, the new instruction is introduced by
overwriting an unused instruction and this ensures the overhead of resource utilization is kept to a minimum.
The new ‘swap’ instruction only involved register data transfer, which is already embedded in the original
architecture, hence there is no additional hardware is required to execute the instruction.
Table 2. Resource Utilization for Bit-Sorting Program
Parameter
UTeMRISC0
(12-bit ISA)
UTeMRISC01
(16-bit ISA)
Difference
Number of Slice registers 102 119 16.7%
Number of Slice LUTs 457 355 22.3%
Number of LUT Flip Flop pairs used 494 409 17.2%
In terms of execution times, the UTeMRISC01 architecture consistently produced lower execution
times throughout the bit-sorting program implementation. Therefore, the program is ended much quicker, as
shown in Figure 4. By calculations, the UTeMRISC01 architecture could finish executing the same bit-
sorting program faster than the UTeMRSIC0 architecture by 12%. This is clearly due to the lower instruction
cycle, resulted in the introduction of the new swap instruction.
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Figure 4. Execution times for bit-sorting program
4. CONCLUSION
In the bit-sorting programs, the number of registers in the UTeMRISC01 is reduced due to several
optimization steps are done to the original UTeMRISC0 architecture. There is no new module added to the
architecture and the new instruction is introduced by occupying the existing instruction slot in the instruction
set. The execution times also improved that makes the program finished earlier. The reduced time is not
because of the less-complexity of the bit-sorting program or the architecture itself but it is due to the
efficiency of the new instruction that replaced the repetitive instruction previously existed in the original
architecture. It is demonstrated here that the adoption of instruction set extension technique on the
UTeMRISC01 architecture has optimized the processor capability in dealing with a more complex task. The
overall development process used in this research is flexible enough for further investigation either by
extending its module or to adopt more complex algorithms in the future. While the focus of this research is to
reduce the execution times and the reduce utilization, power consumption will be considered in the future
iterations of the processor.
ACKNOWLEDGEMENTS
The author would like to thank Universiti Teknikal Malaysia Melaka and Ministry of Higher
Education Malaysia for the financial support through the research grant number PJP / 2016 / FKEKK-CETRI
/ S01496.
REFERENCES
[1] R. Cravotta. (2012, 11 July). One Processor to Rule Them All? Available: http://www.edn.com/design/systems-
design/4398890/One-processor-to-rule-them-all
[2] J. Ganssle. (2012, 2 July). Is 8-bits dying? Available: http://www.embedded.com/electronics-blogs/break-
points/4389890/Is-8-bits-dying-
[3] Microchip, "8-bit PIC® Microcontroller Solutions," Microchip Technology Incorporated 2014.
[4] T. Sutikno, N. R. N. Idris, A. Z. Jidin, and A. Jidin, "A Model of FPGA-based Direct Torque Controller,"
Indonesian Journal of Electrical Engineering and Computer Science, vol. 11, pp. 747-753, 2013.
[5] A. Zemmouri, R. Elgouri, M. Alareqi, M. Benbrahim, and L. Hlou, "Design and Implementation of Pulse Width
Modulation Using Hardware/Software MicroBlaze Soft-Core," International Journal of Power Electronics and
Drive Systems (IJPEDS), vol. 8, pp. 167-175, 2017.
[6] C. Kannan, "NIOS II Based Secure Test Wrapper Design for Testing Cryptographic Algorithms," International
Journal of Reconfigurable and Embedded Systems, vol. 4, 2015.
[7] F. Plavec, B. Fort, Z. G. Vranesic, and S. D. Brown, "Experiences with Soft-Core Processor Design," in IPDPS,
2005, p. 167.2.
[8] F. Plavec, "Soft-core processor design," Master of Applied Science, Graduate Department of Electrical and
Computer Engineering, University of Toronto, 2004.
[9] A. J. Salim, S. I. M. Salim, N. R. Samsudin, and Y. Soo, "Conversion of an 8-bit to a 16-bit Soft-core RISC
Processor," International Journal of Electronics Communication and Computer Technology, vol. 3, pp. 393-397,
2013.
[10] N. R. Samsudin, S. I. M. Salim, and A. J. Salim, "Designing UTeMRISCII Processor for Multiply-Accumulate
Operation," in 3rd International Conference on Engineering and ICT (ICEI2012), 2012, pp. 88-91.
[11] L. E. Yong and A. J. Salim, "Implementation of an 8-bit RISC Microcontroller Chip," in 4th International
Symposium on Broadband Communication, 2010, pp. 1-4.
7. Int J Elec & Comp Eng ISSN: 2088-8708
Instruction Set Extension of a Low-End Reconfigurable Microcontroller in Bit-Sorting … (Sani Irwan)
2601
[12] C. Galuzzi and K. Bertels, "The Instruction-Set Extension Problem: A Survey," ACM Trans Reconfigurable
Technol. Syst., vol. 4, pp. 1-28, 2011.
[13] A. J. Salim, S. I. M. Salim, N. R. Samsudin, and Y. Soo, "Instruction Set Extension Through Partial Customization
of Low-End RISC Processor," Australian Journal of Basic and Applied Sciences, vol. 7, pp. 678-687, 2013.
[14] D. Liu, Embedded DSP Processor Design, : Application Specific Instruction Set Processors: Morgan Kaufmann,
2008.
[15] T. Coonan. (1999, 4 January). RISC8 Verilog Core. Available:
http://pldworld.info/_hdl/2/_ip/mindspring/~tcoonan/risc8doc.html
[16] S. I. M. Salim, H. A. Sulaiman, R. Jamaluddin, L. Salahuddin, M. N. S. Zainudin, and A. J. Salim, "Two-pass
assembler design for a reconfigurable RISC processor," in IEEE Conference on Open Systems (ICOS), 2013,
pp. 77-82.
[17] S. I. M. Salim, H. A. Sulaiman, R. Jamaluddin, L. Salehuddin, M. N. S. Zainudin, and S. Yewguan, "Assembler
Design Techniques for A Reconfigurable Soft-Core Processor," Journal of Theoretical and Applied Information
Technology, vol. 64, 2014.
[18] S. I. M. Salim, H. A. Sulaiman, M. N. S. Zainudin, R. Jamaluddin, and L. Salahuddin, "One-pass assembler design
for a low-end reconfigurable RISC processor," in International Symposium onTechnology Management and
Emerging Technologies (ISTMET), 2014, pp. 492-496.
[19] D. Skrien, "CPU Sim 3.1: A Tool for Simulating Computer Architectures for Computer Organization Classes,"
Journal on Educational Resources in Computing (JERIC), vol. 1, pp. 46-59, 2001.
[20] A. J. Salim, N. R. Samsudin, S. I. M. Salim, and S. Yewguan, "Modification of Instruction Set Architecture in a
UTeMRISCII Processor," International Journal of Computer Trends and Technology (IJCTT), vol. 4,
pp. 1196-1201, 2013.
[21] A. J. Salim, N. R. Samsudin, S. I. M. Salim, and S. Yewguan, "Multiply-accumulate instruction set extension in a
soft-core RISC Processor," in 10th IEEE International Conference on Semiconductor Electronics (ICSE), 2012,
pp. 512-516.
BIOGRAPHIES OF AUTHORS
Sani Irwan Md Salim obtained his first degree in B.Eng (Electronic Engineering), from the Universiti
Teknologi Malaysia (UTM), in 2002. Following that, he obtained his M.EngSc (Computer &
Communication) from Queensland University of Technology (QUT), Australia. He is currently
working as senior lecturer in the Computer Engineering Department, Faculty of Electronic and
Computer Engineering, UTeM. His main research area is in reconfigurable computing with interest in
FPGA applications.
Dr Soo Yew Guan joins Universiti Teknikal Malaysia Melaka (UTeM) as academician since 2001.
Currently he is the Senior Lecturer in Microprocessor and Microcontroller Technology in the Faculty
of Electronics and Computer Engineering (FKEKK). As a professional trainer in Embedded System,
he has conducted CAN Bus Communication in in Embedded System training to Western Digital (M)
Sdn Bhd and Internet of Thing (IoT) programs in Faculty. His research interests include Embedded
System and Robotics, particularly on the myo-electric robotic prosthesis and sensory substitution for
amputees. In addition, his is also interested in software development for various mobile platforms
(iOS, Win8 Phone, and Android) and Internet Technologies (Linux, Apache, MySQL, PHP, and
JSON).
Dr Sharatul Izah Samsudin graduated for her his first degree in B.Eng (Electronic Engineering) at
Universiti Sains Malaysia (USM). Following that, she obtained her M.Eng. and PhD from Universiti
Teknologi Malaysia (UTM). She specializes on control system modeling with interest in water quality
control environment and IoT applications. She is currently working as a senior lecturer in the Industrial
Electronic Department, Faculty of Electronic and Computer Engineering, UTeM.