International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Instruction Set Extension of a Low-End Reconfigurable Microcontroller in Bit-...IJECEIAES
The microcontroller-based system is currently having a tremendous boost with the revelation of platforms such as the Internet of Things. Low-end families of microcontroller architecture are still in demand albeit less technologically advanced due to its better I/O better application and control. However, there is clearly a lack of computational capability of the low-end architecture that will affect the pre-processing stage of the received data. The purpose of this research is to combine the best feature of an 8-bit microcontroller architecture together with the computationally complex operations without incurring extra resources. The modules’ integration is implemented using instruction set architecture (ISA) extension technique and is developed on the Field Programmable Gate Array (FPGA). Extensive simulations were performed with the and a comprehensive methodology is proposed. It was found that the ISA extension from 12-bit to 16-bit has produced a faster execution time with fewer resource utilization when implementing the bit-sorting algorithm. The overall development process used in this research is flexible enough for further investigation either by extending its module to more complex algorithms or evaluating other designs of its components.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
EFFECTIVE EMBEDDED SYSTEMS SOFTWARE DESIGN METHODOLOGIEScscpconf
This paper gives Universities needs to improve their curriculum for Technology students to meet
the industry standards which will be helpful for their career .In the current improving
technologies studying of embedded system is required to understand the Electronic circuits .
They should include the new emerging technology such as multiprocessor system on chip where it is used in all the real time applications. In this paper design based tutorials will be discussed to understand Multiprocessor system on chip .The understanding of multiprocessor system on chip is difficult for a student and should be taught to meet the expectation from the industry. Since it is vast area, this paper proposes the most efficient tutoring method on multiprocessor system on chip.
Instruction Set Extension of a Low-End Reconfigurable Microcontroller in Bit-...IJECEIAES
The microcontroller-based system is currently having a tremendous boost with the revelation of platforms such as the Internet of Things. Low-end families of microcontroller architecture are still in demand albeit less technologically advanced due to its better I/O better application and control. However, there is clearly a lack of computational capability of the low-end architecture that will affect the pre-processing stage of the received data. The purpose of this research is to combine the best feature of an 8-bit microcontroller architecture together with the computationally complex operations without incurring extra resources. The modules’ integration is implemented using instruction set architecture (ISA) extension technique and is developed on the Field Programmable Gate Array (FPGA). Extensive simulations were performed with the and a comprehensive methodology is proposed. It was found that the ISA extension from 12-bit to 16-bit has produced a faster execution time with fewer resource utilization when implementing the bit-sorting algorithm. The overall development process used in this research is flexible enough for further investigation either by extending its module to more complex algorithms or evaluating other designs of its components.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
EFFECTIVE EMBEDDED SYSTEMS SOFTWARE DESIGN METHODOLOGIEScscpconf
This paper gives Universities needs to improve their curriculum for Technology students to meet
the industry standards which will be helpful for their career .In the current improving
technologies studying of embedded system is required to understand the Electronic circuits .
They should include the new emerging technology such as multiprocessor system on chip where it is used in all the real time applications. In this paper design based tutorials will be discussed to understand Multiprocessor system on chip .The understanding of multiprocessor system on chip is difficult for a student and should be taught to meet the expectation from the industry. Since it is vast area, this paper proposes the most efficient tutoring method on multiprocessor system on chip.
System on Chip Based RTC in Power ElectronicsjournalBEEI
Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.
@Station is an Integrated Control and Protection designed for the operation of transmission and distribution substations. The system incorporates the latest technology in the field of substation automation to provide its users with innovative solutions to their requirements.
Control and indicating equipment communicating via the peripheral component i...journalBEEI
Nowadays, the Intruder Alarm system is commonly used to protect the life, health and the possession of people in big companies. However, these systems have limited options for managing and remote control. This lack is very often criticized by big companies which want to use the Intruder Alarm System with other applications like Access and Attendance control. The aim of this article is to design a Control and Indicating Equipment which can be implemented into commercially made Personal Computer as expansion card. The designed card provides the main function of the Intruder Alarm system which can be further extended by other applications. The system consists of external communication like Universal Serial Bus, Ethernet and General Packet Radio Service interface. Each individual part of the system is driven by a single microcontroller ATmega328P which can handle communication and evaluation of the current state obtained by devices connected to it. The design can offer all alarm and non-alarm visualization of smart control like irrigation, lights control, audio system, etc. The whole design is driven by the proper standardization and the design consists of every schematic which comes with the explanation
5 Techniques to Achieve Functional Safety for Embedded SystemsAngela Hauber
Failures of safety-critical electronic systems can result in loss of life, substantial financial damage or severe harm to the environment.
Safe computer systems are typically used in avionics or railway applications requiring particularly high reliability. This also goes for the medical market, while industrial automation environments demand more and more functional safety as technology becomes readily available.
Using Virtualization Technique to Increase Security and Reduce Energy Consump...IJORCS
An approach has been presented in this paper in order to generate a secure environment on internet Based Virtual Computing platform and also to reduce energy consumption in green cloud computing. The proposed approach constantly checks the accuracy of stored data by means of a central control service inside the network environment and also checks system security through isolating single virtual machines using a common virtual environment. This approach has been simulated on two types of Virtual Machine Manager (VMM) Quick EMUlator (Qemu), HVM (Hardware Virtual Machine) Xen and outputs of the simulation in VMInsight show that when service is getting singly used, the overhead of its performance will be increased. As a secure system, the proposed approach is able to recognize malicious behaviors and assure service security by means of operational integrity measurement. Moreover, the rate of system efficiency has been evaluated according to the amount of energy consumption on five applications (Defragmentation, Compression, Linux Boot Decompression and Kernel Boot). Therefore, this has been resulted that to secure multi-tenant environment, managers and supervisors should independently install a security monitoring system for each Virtual Machines (VMs) which will come up to have the management heavy workload of. While the proposed approach, can respond to all VM’s with just one virtual machine as a supervisor.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
System on Chip Based RTC in Power ElectronicsjournalBEEI
Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.
@Station is an Integrated Control and Protection designed for the operation of transmission and distribution substations. The system incorporates the latest technology in the field of substation automation to provide its users with innovative solutions to their requirements.
Control and indicating equipment communicating via the peripheral component i...journalBEEI
Nowadays, the Intruder Alarm system is commonly used to protect the life, health and the possession of people in big companies. However, these systems have limited options for managing and remote control. This lack is very often criticized by big companies which want to use the Intruder Alarm System with other applications like Access and Attendance control. The aim of this article is to design a Control and Indicating Equipment which can be implemented into commercially made Personal Computer as expansion card. The designed card provides the main function of the Intruder Alarm system which can be further extended by other applications. The system consists of external communication like Universal Serial Bus, Ethernet and General Packet Radio Service interface. Each individual part of the system is driven by a single microcontroller ATmega328P which can handle communication and evaluation of the current state obtained by devices connected to it. The design can offer all alarm and non-alarm visualization of smart control like irrigation, lights control, audio system, etc. The whole design is driven by the proper standardization and the design consists of every schematic which comes with the explanation
5 Techniques to Achieve Functional Safety for Embedded SystemsAngela Hauber
Failures of safety-critical electronic systems can result in loss of life, substantial financial damage or severe harm to the environment.
Safe computer systems are typically used in avionics or railway applications requiring particularly high reliability. This also goes for the medical market, while industrial automation environments demand more and more functional safety as technology becomes readily available.
Using Virtualization Technique to Increase Security and Reduce Energy Consump...IJORCS
An approach has been presented in this paper in order to generate a secure environment on internet Based Virtual Computing platform and also to reduce energy consumption in green cloud computing. The proposed approach constantly checks the accuracy of stored data by means of a central control service inside the network environment and also checks system security through isolating single virtual machines using a common virtual environment. This approach has been simulated on two types of Virtual Machine Manager (VMM) Quick EMUlator (Qemu), HVM (Hardware Virtual Machine) Xen and outputs of the simulation in VMInsight show that when service is getting singly used, the overhead of its performance will be increased. As a secure system, the proposed approach is able to recognize malicious behaviors and assure service security by means of operational integrity measurement. Moreover, the rate of system efficiency has been evaluated according to the amount of energy consumption on five applications (Defragmentation, Compression, Linux Boot Decompression and Kernel Boot). Therefore, this has been resulted that to secure multi-tenant environment, managers and supervisors should independently install a security monitoring system for each Virtual Machines (VMs) which will come up to have the management heavy workload of. While the proposed approach, can respond to all VM’s with just one virtual machine as a supervisor.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Data Acquisition and Control System for Real Time Applicationsijsrd.com
This paper proposes an Embedded Ethernet which is nothing but a processor that is capable to communicate with the network. This helps in data acquisition and status monitoring with the help of standard LAN. Currently device with processor is widely used in industrial field. The Embedded Ethernet provides web access to distributed measurement/control systems and provides optimization for instrumentation, educational laboratories and home automation. However, a large number of devices don't have the network interface and the data from them cannot be transmitted in network. A design of ARM Processor based Embedded Ethernet interface is presented. In this design, data can be transmitted transparently through Ethernet interface unit to remote end desktop computer. By typing the IP address of LAN on the ARM9 board, the user gets sensor values on the PC screen at remote station. This provides the status of the devices at remote field. The user can also control the devices interfaced to the ARM9 Board by pressing the button displayed on the GUI of the remote Desktop PC.
Embedded Web Server based Interactive data acquisition and Control SystemIOSR Journals
ABSTRACT: Design of on-line embedded web server is a one of the difficult task of many real time data acquisition and control system applications. The global system of interconnected computer networks is called as World Wide Web which uses the standard Internet Protocol Suite (TCP/IP) to aid billion of users worldwide and enables the user to interface many real time embedded applications like data acquisition,Industrial automations and safety measures etc,. This paper tells the design and development of on-line Interactive Data Acquisition and Control System (IDACS) using ARM9 based embedded web server. It is permitted to a network, intelligent and digital distributed control system. Single chip IDACS method increses the processing speed of a system and also avoids the problem of poor real time and reliability.This system uses ARM9 Processor and RTLinux. Web server application is ported into an ARM processor using embedded ‘C’ language. Web pages are designed in Hyper text markup language (HTML). Keywords - Embedded ARM9 Processor, RTLinux RTOS, Embedded web server, IDACS.
Embedded Web Server based Interactive data acquisition and Control SystemIOSR Journals
Design of on-line embedded web server is a one of the difficult task of many real time data
acquisition and control system applications. The global system of interconnected computer networks is called as
World Wide Web which uses the standard Internet Protocol Suite (TCP/IP) to aid billion of users worldwide and
enables the user to interface many real time embedded applications like data acquisition,Industrial automations
and safety measures etc,. This paper tells the design and development of on-line Interactive Data Acquisition
and Control System (IDACS) using ARM9 based embedded web server. It is permitted to a network, intelligent
and digital distributed control system. Single chip IDACS method increses the processing speed of a system and
also avoids the problem of poor real time and reliability.This system uses ARM9 Processor and RTLinux. Web
server application is ported into an ARM processor using embedded ‘C’ language. Web pages are designed in
Hyper text markup language (HTML)
On-line IDACS for Embedded Real Time ApplicationAM Publications
Design of on-line embedded web server is a challenging part of many embedded and real time data acquisition and control system applications. The World Wide Web is a global system of interconnected computer networks that use the standard Internet Protocol Suite (TCP/IP) to serve billion of users worldwide and allows the user to interface many real time embedded applications like data acquisition, Industrial automations and safety measures etc,. This paper approached towards the design and development of on-line Interactive Data Acquisition and Control System (IDACS) using ARM based embedded web server. It can be a network, intelligent and digital distributed control system. Single chip IDACS method improves the processing capability of a system and overcomes the problem of poor real time and reliability. This system uses ARM9 Processor portability with Real Time Linux operating system (RTLinux RTOS) it makes the system more real time and handling various processes based on multi-tasking and reliable scheduling mechanisms. Web server application is ported into an ARM processor using embedded ‘C’ language. Web pages are written by Hyper text markup language (HTML); it is beneficial for real time IDACS, Mission critical applications, ATM networks and more. Mission critical applications, ATM networks and more.
On-line IDACS for Embedded Real Time ApplicationAM Publications
Design of on-line embedded web server is a challenging part of many embedded and real time data acquisition and control system applications. The World Wide Web is a global system of interconnected computer networks that use the standard Internet Protocol Suite (TCP/IP) to serve billion of users worldwide and allows the user to interface many real time embedded applications like data acquisition, Industrial automations and safety measures etc,. This paper approached towards the design and development of on-line Interactive Data Acquisition and Control System (IDACS) using ARM based embedded web server. It can be a network, intelligent and digital distributed control system. Single chip IDACS method improves the processing capability of a system and overcomes the problem of poor real time and reliability. This system uses ARM9 Processor portability with Real Time Linux operating system (RTLinux RTOS) it makes the system more real time and handling various processes based on multi-tasking and reliable scheduling mechanisms. Web server application is ported into an ARM processor using embedded ‘C’ language. Web pages are written by Hyper text markup language (HTML); it is beneficial for real time IDACS, Mission critical applications, ATM networks and more. Mission critical applications, ATM networks and more.
Reliable embedded systems play an increasing role in modern life, especially in modern
automotive designs. Many studies have proved that it performs better in many situations.
Firstly, reliable embedded systems provide the system reliability improvements. Secondly,
reliable embedded systems also can improve the development efficiency and make the
development cycle shorter.
However, in the high real-time required occasion, the software implementation of the RTOS
can`t fully meet requirements. To have better real-time only through the algorithm improvement
or just increase the processor speed. On the contrary, operating system based on a hardware
implementation can make it more real-time and more reliable. The reason is due to that the
hardware circuit is independent of the processor running and do not take up the processing time
of the processor. Thereby it can save time to execute other tasks and improve real-time. In this
paper, ARM+FPGA will be choose as the IP hardware development platform.
SIMULATION-BASED APPLICATION SOFTWARE DEVELOPMENT IN TIME-TRIGGERED COMMUNICA...IJSEA
This paper introduces a simulation-based approach for design and test of application software for timetriggered
communication systems. The approach is based on the SIDERA simulation system that supports
the time-triggered real-time protocols TTP and FlexRay. We present a software development platform for
FlexRay based communication systems that provides an implementation of the AUTOSAR standard
interface for communication between host application and FlexRay communication controllers. For
validation, we present an application example in the course of which SIDERA has been deployed for
development and test of software modules for an automotive project in the field of driving dynamics
control.
Design and Development of ARM9 Based Embedded Web ServerIJERA Editor
This paper describes the design of embedded web server based on ARM9 processor and Linux platform. It
analyses hardware configuration and software implementation for monitoring and controlling systems or
devices. User can monitor and control temperature and smoke information. It consists of application program
written in „C‟ for accessing data through the serial port and updating the web page, porting of Linux 2.6.3x
Kernel with application program on ARM9 board and booting it from the RAM.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
DIVISION AND REPLICATION OF DATA IN GRID FOR OPTIMAL PERFORMANCE AND SECURITYijgca
Using Grid Storage, users can remotely store their data and enjoy the on-demand high quality applications and services from a shared networks of configurable computing resources, without the burden of local data storage and maintenance. In this project based on the dynamic secrets proposed design an encryption scheme for SG wireless communication, named as dynamic secret-based encryption (DSE). Dynamic encryption key (DEK) is updated by XOR the previous DEK with current DS. In this project based on the dynamic secrets proposed design an encryption scheme for SG wireless communication, named as dynamic secret-based encryption (DSE). The basic idea of dynamic secrets is to generate a series of secrets from unavoidable transmission errors and other random factors in wireless communications In DSE, the previous packets are coded as binary values 0 and 1 according to whether they are retransmitted due to channel error. This 0/1 sequence is called as retransmission sequence (RS) which is applied to generate dynamic secret (DS). Dynamic encryption key (DEK) is updated by XOR the previous DEK with current DS.
DIVISION AND REPLICATION OF DATA IN GRID FOR OPTIMAL PERFORMANCE AND SECURITYijgca
Using Grid Storage, users can remotely store their data and enjoy the on-demand high quality applications and services from a shared networks of configurable computing resources, without the burden of local data storage and maintenance. In this project based on the dynamic secrets proposed design an encryption scheme for SG wireless communication, named as dynamic secret-based encryption (DSE). Dynamic encryption key (DEK) is updated by XOR the previous DEK with current DS. In this project based on the dynamic secrets proposed design an encryption scheme for SG wireless communication, named as dynamic secret-based encryption (DSE). The basic idea of dynamic secrets is to generate a series of secrets from unavoidable transmission errors and other random factors in wireless communications In DSE, the previous packets are coded as binary values 0 and 1 according to whether they are retransmitted due to channel error. This 0/1 sequence is called as retransmission sequence (RS) which is applied to generate dynamic secret (DS). Dynamic encryption key (DEK) is updated by XOR the previous DEK with current DS.
DIVISION AND REPLICATION OF DATA IN GRID FOR OPTIMAL PERFORMANCE AND SECURITYijgca
Using Grid Storage, users can remotely store their data and enjoy the on-demand high quality applications and services from a shared networks of configurable computing resources, without the burden of local data storage and maintenance. In this project based on the dynamic secrets proposed design an encryption scheme for SG wireless communication, named as dynamic secret-based encryption (DSE). Dynamic encryption key (DEK) is updated by XOR the previous DEK with current DS. In this project based on the dynamic secrets proposed design an encryption scheme for SG wireless communication, named as dynamic secret-based encryption (DSE). The basic idea of dynamic secrets is to generate a series of secrets from unavoidable transmission errors and other random factors in wireless communications In DSE, the previous packets are coded as binary values 0 and 1 according to whether they are retransmitted due to channel error. This 0/1 sequence is called as retransmission sequence (RS) which is applied to generate dynamic secret (DS). Dynamic encryption key (DEK) is updated by XOR the previous DEK with current DS
RITA SECURE COMMUNICATION PROTOCOL: APPLICATION TO SCADAcsandit
Supervisory control and data acquisition (SCADA) systems have their own constrains and specifications. These systems control many of our critical industrial infrastructures, yet they are hardly secured. The biggest problem in securing these systems is the lack of cryptography support especially that most SCADA systems work in real-time which is not compatible with most cryptography algorithms. Additionally, a SCADA network may include a huge amount of embedded devices with little computational powers which adds to the cost of any security improvement. In this paper we present a new approach that would secure SCADA communications by coding information without the need of the complex cryptography algorithms. The reconfigurable information transmitter agent (RITA) protocol that we present does not need the already installed devices to be modified nor replaced, it only needs to add costless electrical chips to these devices. This approach can also be used to secure any type of communication that respects the protocol's constraints.
DYNAMIC HW PRIORITY QUEUE BASED SCHEDULERS FOR EMBEDDED SYSTEMijesajournal
A real-time operating system (RTOs) is often used in embedded system, to structure the application code
and to ensure that the deadlines are met by reacting on events by executing the functions within precise
time. Most embedded systems are bound to real-time constraints with determinism and latency as a critical
metrics. RTOs are generally implemented in software, increases computational overheads, jitter and
memory footprint. Modern FPGA technology, enables the implementation of a full featured and flexible
hardware based RTOs, which helps in reducing to greater extent these overheads even if not remove
completely. Scheduling algorithms play an important role in the design of real-time systems. An Adaptive
Fuzzy Inference System (FIS) based scheduler framework proposed in this article is based on the study and
conclusion drawn from the research over the years in HW SW co-design domain. The proposed novel two
phase FIS based adaptive hardware task scheduler minimizes the processor time for scheduling activity
which uses fuzzy logic to model the uncertainty at first stage along with adaptive framework that uses
feedback which allows processors share of task running on multiprocessor to be controlled dynamically at
runtime. This Fuzzy logic based adaptive hardware scheduler breakthroughs the limit of the number of
total task and thus improves efficiency of the entire real-time system. The increased computation overheads
resulted from proposed two phase FIS scheduler can be compensated by utilising the basic characteristics
of parallelism of the hardware as scheduler being migrated to FPGA.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
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1. Saurabh Kumar et al Int. Journal of Engineering Research and Application
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RESEARCH ARTICLE
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OPEN ACCESS
Detection of Errors on Serial Communication Lines in RTOS
Based-Embedded Systems
Saurabh Kumar*, Narayanaraju Samunuri**
*(Department of ECE, Sreenidhi Institute of Science and Technology, JNTU-Hyderabad, India)
ABSTRACT
Embedded Real Time application uses multi threading, a key concept of any conventional OS. The advantage of
multi-threading include greater throughput, more efficient use of CPU such that it cannot remain idle for long
time, better system reliability, improved performance on multiprocessor computer. The use of Real Time
Operating Systems (RTOSs) became an attractive solution to simplify the design of safety-critical real-time
embedded systems. Due to their demanding strict attention to rules and procedures constraints such as highspeed, low voltage operation and battery-power dependence, because of sudden up and down of voltages,
transients in flow of current can cause error in serial communication lines. External conditions, such as
Electromagnetic Interference (EMI), Heavy-Ion Radiation (HIR) as well as Power Supply Disturbances (PSD)
can also cause transient faults. As the major consequence, the system’s reliability degrades.
In this paper, the main focus will be on the detection of the errors on the serial communication lines. This is
achieved by using a hardware approach with the combination of Cyclic Redundancy Check and RTOS. During
execution of these programs, the proposed system exposed to EMI according to the international standard for
voltage transients, voltage dips and short interruptions on the serial communication lines of electronic systems.
The obtained result shows that the proposed approach is able to provide higher fault coverage.
Keywords__ Hardware-Based Approach, Real-Time Operating System, Reliable Embedded System,
Electromagnetic Interference (EMI), Serial Communication lines, Cyclic Check Redundancy (CRC).
I.
INTRODUCTION
One of the key characteristic of an operating
system (OS) is its ability to handle to multiple tasks at
a time on a time sharing basis commonly referred to as
Multi-tasking. It is also responsible for managing the
hardware resources of a computer and hosting
applications that execute on the computer. A real-time
operating system is a specialized type of operating
system where execution of tasks has to be done
precisely without exceeding the deadlines and is
intended to use for Real-time systems.
The OS meant for RTS is referred as RTOS where
the time at which results are produced is of major
concern. Basically, real-time systems are classified in
to two types: Hard and Soft real-time systems. Now
days, all real time embedded systems for safety
measures uses timing constraints. In general terms,
real-time systems have to provide not only logically
correct results [1] but also in how much time they are
producing it. The necessity to adopt Real-Time
Operating Systems (RTOSs) is increased as the real
time systems are getting complex day by day in order
to simplify the design. Though, embedded systems
based on RTOSs exploit some important facilities
associated to RTOSs’ native intrinsic mechanisms to
manage tasks, concurrency, memory as well as
interrupts. In other words, RTOSs serve as an interface
between software and hardware.
At the same time, the environment’s always
increasing hostility caused substantially by the
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ubiquitous adoption of wireless technologies, such as
mobile telephones, represents a huge challenge for the
reliability [2] of real-time embedded systems as these
equipments causes’ radiations and affects the behavior
of any embedded system which can leads to many
fatal results. In detail, external conditions, such as
Electromagnetic Interference (EMI) [3], Heavy-Ion
Radiation (HIR) as well as Power Supply Disturbances
(PSD) [4] may cause transient errors. Currently, the
consequences of transient errors represent a wellknown concern in microelectronic systems. Though,
embedded systems based on RTOS are subject to
Single Event Upsets (SEUs) causing transient errors,
which can affect the application running on embedded
systems.
The suggested approach in this paper is to use
the Plasma MIPS architecture with the combination of
RTOS μC/OS-II (Platform) with Cyclic Check
Redundancy (CRC) [5] to detect the errors on serial
Communication lines. To test and achieve the required
performance it is run on FPGA kit and the output is to
be observed on the HyperTerminal via UART
II.
IMPLEMENTATION
The implementation of this concept consists of
Software Approach (which consists of combination of
Real Time Operating System (μC/OS-II) with the
application of detecting error i.e. Cyclic Redundancy
Check) on Plasma MIPS architecture (Processor
Used).
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MIPS architecture is linked with the software
approach to produce desire results.
Fig.1: Block Diagram of Proposed Approach
1.1 Processor Used (Plasma MIPS Architecture)
To evaluate the hardware based approach it
consists of RTOS running on Plasma MIPS
architecture [10]. The Plasma MIPS is implemented in
VHDL with exception of the load/store instruction, an
instruction set compatible to the MIPS architecture.
The Plasma RTOS uses the Pre-emptive scheduling
algorithm with priority support compose of the
following three states: blocked, ready and executing.
1.2 Software Approach
The software approach consists of μC/OS-II
[6] platform with the application of detecting the
errors which causes deviation in the outputs or
generates dysfunctions that could lead to incorrect
system behaviour using cyclic redundancy check. The
main operation of software approach is to detect the
fault on serial communication lines which causes the
data corruption.
To carry out this approach GNU tool chain
[7] is used to compile the μC/OS-II files with the
application to detect the faults i.e. Cyclic Redundancy
Check. These files will get compiled by using MIPS
GNU Compiler to generate the individual object files
(.obj files). Now MIPS GCC Linker links all the .obj
files and gives the output as .elf32 file (Executable and
linkable format) which is saved with the extension of
.axf file (Arm executable format; which is an object
file format generated by GCC Compiler and linker and
contains both object code and debugging information).
Now with the help of convert_bin.exe command .axf
file has to be converted into .txt file. Now we have to
generate ram_image.vhd file with the help of toimage
command.
Fig.3 Project Process flow
Fig. 2 Plasma MIPS Processor Architecture
The Plasma’s RTOS provides a basic
mechanism able to detect the errors on serial
communication lines. This used processor i.e. Plasma
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Now, the generated ram_image.vhd which
contains the complete information of μC/OS-II files
and the application build to detect the error which is
written in C-code is converted into .vhd format. Now
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the generated ram_image.vhd file has to be linked
with the used architecture i.e. Plasma MIPS
architecture written in VHDL code with the help of
Xilinx ISE software to generate the Bitmap file and
then this generated bit map file is to be dump on
SPARTAN 3E 1600 FPGA kit [9] to perform the
required operation using iMPACT Programming.
Fig.5 Assigning Configuration File
4. Right on the device and select program, which
configures the FPGA device, and it displays Program
Succeeded once it is successfully finished as shown in
Fig.6.
Fig.4 Hardware Setup
III.
EXPERIMENTATION
After successfully compiling an FPGA design
and generating the bit map file using the Xilinx
development software, now the design (bit map file)
has to be downloaded on the SPARTAN 3E FPGA kit
using the iMPACT programming software and the
USB cable.
To Configure the FPGA kit the following
steps have to be followed:
1. The first step is to connect the SPARTAN board to
PC using standard USB Type A/Type B cable.
2. Click on configure device (iMPACT), it opens
iMPACT window then select boundary scan and click
on initialize JTAG chain. If board is connected
properly the software automatically recognizes the
devices in the JTAG programming file.
3. Right click on FPGA device i.e. XC3S1600E and
select assign configuration file, then browse for the bit
file and click ok and bypass remaining options as
shown in Fig.5.
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Fig.6 FPGA Configured
After successfully configured the FPGA now
SPARTAN 3E FPGA development kit is ready to run
the architecture with μC/OS-II files and the
application to detect the errors (i.e. CRC). . Before
dumping the architecture in to the FPGA the .bin file
corresponding to the architecture is being generated
and is dumped in to the board using the iMPACT
software which is part of XILINX ISE. GCC tool is
used for compiling the μC/OS-II with application and
at the same time generating the hex file corresponding
to the required application. The operating system and
application executable were loaded into the FPGA's
block RAM and executed from there. And then an
application is to be run on architecture and the
corresponding output is to be observed in
HyperTerminal by means of UART.
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IV.
RESULTS
As mentioned earlier, the application (CRC)
has to be developed with the combination of RTOS
(μC/OS-II) with MIPS architecture and has to be
dumped on FPGA kit [9]. The application tests the
successful operation of the proposed approach and
produces the required results on the HyperTerminal.
As is Fig.7, there is no corruption of data on serial
communication lines. Our proposed approach Cyclic
Redundancy Check i.e. CRC [5] on μC/OS-II platform
has produced the result as No Error Detected on the
HyperTerminal.
Fig.7 Serial Debug Log for Test application i.e.CRC
(NO ERROR DETECTED)
As in Fig.8, we have introduced the faults
using solenoid [11] by generating Electromagnetic
Interference (EMI) and Power supply Disturbances on
serial communication lines. Our proposed approach
Cyclic Redundancy Check i.e. CRC [5] on μC/OS-II
platform has produced the result as CRC Detected the
Error on the Received Byte on HyperTerminal
successfully.
V.
REFERENCES
[1]
[2]
[4]
[5]
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CONCLUSION AND FUTURE
SCOPE
The main contribution of this paper consists of
providing significantly more robust way of detecting
the errors on serial communication lines on MIPS
architecture with μC/OS-II RTOS, implemented and
tested on Xilinx FPGA kit [9]. In this paper we
proposed a Cyclic Redundancy Check (CRC)
approach able to detect error occurrences on serial
communication lines causing the data corruption. In
general terms, the proposed approach targets transient
errors affecting the data on serial bus, where it can be
used for the scheduling process of the RTOS. It has
been developed using cyclic check redundancy (CRC)
to perform on-line detection of such type of faults. The
main contribution of this paper consists of drastically
improving the robustness of MIPS architecture based
processor and μC/OS-II RTOS embedded systems
operating in harsh environments like those where the
electronics is exposed to conducted EMI noise. The
proposed approach provides nearly 100% of fault
coverage.
To conclude, we are convinced that the CRCbased approach proposed herein represents an
important improvement to the state-of the- art of
designing hardened embedded systems running on
RTOSs. Future work includes correction of errors
apart from the error detection, using error correction
techniques such as hamming code etc. And also this
can be extended to other serial communication buses
like SPI, USB etc.
[3]
Fig.8 Serial Debug Log for Test application i.e.CRC
(CRC DETECTED THE ERROR)
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N. Ignat, B. Nicolescu, Y. Savari, G.
Nicolescu, “Soft-Error Classification and
Impact Analysis on Real-Time Operating
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E. Touloupis, J. A. Flint, V. A. Chouliaras, D.
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ISSN : 2248-9622, Vol. 3, Issue 5, Sep-Oct 2013, pp.1439-1443
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[6]
Micrium Expands RTOS Family with
µC/OS-II" (Press release). Micriµm, Inc.
2009-03-24. Retrieved 2010-02-14.
[7]
Programming Languages Supported by
GCC". GNU Project. Retrieved 2011-11-25.
[8]
Denton J. Dailey (2004), Programming Logic
Fundamentals Using Xilinx ISE and CPLDs,
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PLDs using Xilinx ISE.
[9]
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Fulfilling the Programmable Imperative.”
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[10] MIPS32 Architecture". MIPS Technologies.
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[11] D. Howard Dellinger, L. E. Whittmore, and R.
S. Ould (1924). "Radio Instruments and
Measurements". NBS
Circular (National
Bureau of Standards) C74. Retrieved 200909-07.
Author’s biography
Saurabh Kumar, pursuing
M.Tech in Digital systems and Computer Electronics
(DSCE), Department of ECE, from Sreenidhi Institute
of Science and Technology, JNTU-Hyderabad (A.P).
Narayanaraju Samunuri, M.Tech in Embedded
Systems, with an experience of 11 years in Core
Embedded System domain, published International
paper on Flex ray Communication and Context
Switching.
www.ijera.com
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