The document discusses the 555 timer integrated circuit. It provides a brief history and overview of the 555 timer IC, describes its pin configurations and operating modes, and gives examples of its applications. The 555 timer can be used to generate precise time delays ranging from microseconds to hours in monostable, bistable, and astable configurations. It has widespread uses in applications like timers, oscillators, pulse generators, and more.

1. *
By
-Abhijit H/ adl1av (Roll no 02)
-(Roll no 58)

2. y•
e
0 Introduction
0 Pin Configuration
0 Purpose of pin
O 555 Integral circuit
0 Opera ting modes
. / Bistable
. / Monostable
. / Astable
0 Application
0 Conclusion
0 Biblography

3. *
•• The SSS ICwas designed tin 1971
by Hans Camenzind under
contract to SigNetics
Corpora tion.
•• 555 tim er is a h ighly stabl
e
circuit used to generate
time
delays, or Oscilla tions.
•• A single SSS timer can
provid e tin1e delay ra nging from
microseconds to l1ours.
•• I t opera tes from a wide ra
nge
of power supplies ra ngi ng from +
5 Volts to + 18 Volts supply

4. Co
•Pin- 1: Ground
• Pin- 2: Trigger
• Pin- 3: Output
•Pin-4: Re et GND •
• Pin- 5: Control V
oltage TRIG
• Pin-6: Threshold
•Pin- 7: Discharge
•Pin- 8: Yee
•
g
ou
·
r
I 'Lf
555
DI
·
r1lR
CTRL

5. Pin noName Purpose
1 GN D Grou nd reference voltage, low level (0 V)
2 TRIG The OUT pin goes high and a lim ing interval starts when this
input falls below Y.z of CTRL voltage.
3 OUT Driven approx. 1.7 V below Vee or GN D
4 RESE
T
A tin1ing in terval may be reset by driving th is input to GN D.
5 CTRL Provides "control" access to the internal voltage divider (by
default 2/3 Vee) at THR is greater than that at CTRL
6 TllR The tim ing interval ends when the voltage at Tll R is greater
than that at CTRL
7 DIS Open collector output which may dishcha rge the capacitor
benveen interval in phase with output.
8 Vee Positive supply voltage, which is usually between 3 and 15 V
depending on the va ria tion.

6. *sssc•

7. *one
•
g
./ IC 555 has three operating modes:
1. mode or • 111+ t-. ,,, • - the SSS can operate as a
, i f the DIS pin is not connected and no capacitor is used. Uses incl
ude bounce-free latched switches.
mode - in this mode, the SSS functi ons as a "one-shot" pulse
generator. Applica tions incl ude timers, missing pulse detection, bou
nce-free switches, touch
switches, frequen cy divider, capacitance measuremen t,
(PWM) and so on.
(free-running) mode - the SSS can operate as an
2.
3.
I
r t
• Uses include and lamp flashers,
pulse generation, logic clocks, tone generation, security
alarms, and so on.

8. , In bistable (also called
the SSS tin1er acts as a basic flip-flop.
) mode,
,The trigge r and reset inputs (pins 2 and 4
respectively on a 555) are held high via
whtle the th reshold in pu t (pin 6) is simply
floating.
,Th us configured, pu lling the trigger
momen tarily to ground acts as a 'set' and
tra nsitions the outpu t pin (pin 3) to Vee (high
state).
-,. Pulling the reset: input to ground acts as a 'reset'
and transitions the outpu t pin to ground (low
state). No timing capaci tors
,Pi n 5 (control voltage) is con nected to ground via a
small-va lue capacitor (usua lly 0.01 to 0.1µF).
Pin 7 (d ischarge) is left floa ting
v
-
. .. a
RES
E
T v
2
TRIG
--
Tngge
r
6
THR
DIS
GNO CTRL
OUT
3 -
-
-
7
OUt
l s
lOn
f
GNO =
I

9. • Pulse generator circuit which the period is calculated from RC network
and connected to external of SSS timer
•Stable when the output logic LOW (logic = 0)
•When a pulse is trigger at pin 2 (normally negative trigger pulse), timer
outpu t wi ll change to H I GH (+Vs) for a wh ile and change to LOW (stable
condition). The condition willcontinue LOW until pulse is trigger again.
•The timing period is triggered (sta rted) when trigger input (SSS p in 2) is
less than 1/ 3 Vs, th is makes the output h igh (+Vs) and the capacitor Cl
starts to charge through resistor Rl. Once the time period has started further
trigger pulses are ignored.
•The threshold inpu t (SSS pi n 6) monitors the voltage across Cl and when
this reaches 2/3 Vs the time period over and the output becomes LOW,
•At the same tin1e discharge (SSS pi n 7) is connected to OV, dischargi ng the
capacitor ready for the next trigge r.

10. - - - - -
-
4+vcc
8
R
-
input trigger
r 1/3 Vee
- - - - - - - - - , Discharge
tra nsi tor
I I
:3
I
S Q Inverter 1
- - - - +
- - - - - - - - - -'
-
7•
I
6•
I
I
I
I
21
I
One-shot operation
-
-
1
R
-
I
I
I
The inpu t trigger resets the flip-flop an d C then charges u ntil
the u pper compa rator trip and cts the flip-flop.

11. *
0utpo1
n-
n-
.n_
Ra 6 SSS t -
3
2 ,
s
./ Astable multivibrators are also
known as Free
running Multivibrator.
./ Astable do not 11eed n-igge r
pulse for external to change
the output.
./ The period for LOW and
H IGH can be calculated based
on resistor and capacitor
value that
connected at outside of timer.
+V
a:
::::- 0.01µP
1
1
-
-
C charge through R + R8
and di charge through R8•

12. *
. /
. /
. /
. /
. /
. /
. /
. /
. /
Schmitt trigger PPM
PWM
linear Ramp genera tor
Precision Timing
Pulse Generation
Time Delay Generation
Sequential Timing
Used as a quad timer

13. c us•
0
Hence 555 IC timer can prod uce very accurate
and stable time delays,from microseconds to hours. It
can be used with supply voltage varying from 5
to 18 V. Tirner can be used in monostable mode of
operation or astable mode of
operation. I ts various applications include waveform
generator, missing pulse detector, frequency divider,
pulse width modulator, burg lar alarm,
FSK generator, ramp generator, pulse position
modulator etc.