This document proposes a high endurance hybrid cache design with access aware policies and dynamic cache partitioning. It addresses the problems of high leakage power in SRAM caches and high write latency/energy in STT-RAM caches. The design uses a hybrid local cache with both SRAM and STT-RAM cells to reduce write pressure on any single bank. Access aware policies direct writes to the SRAM portion when possible to utilize its fast write speeds. Dynamic cache partitioning further balances the write distribution and reduces cache misses over time. Analysis shows this approach improves write counts, lifetime, and performance compared to a traditional cache design.

1. High Endurance Hybrid Cache
Design with Access Aware
policies and Dynamic Cache
Partitioning
By Thallam Keerthi
Under Guidance of Mrs.Namitha Palecha
RVCE VLSI Design and Embedded systems

2. OverviewOverview
 Problem Description
 Introduction to STT-RAM
 Local Bank Hybrid Cache Architecture
 Access Aware Policies
 STT-RAM Write Management Policy (Algorithm)
 SRAM Read Management Policy (Algorithm)
 Dynamic Cache Partitioning (Algorithm)
 Performance Analysis
 Conclusion

3. Problem DescriptionProblem Description
 Increasing frequency of operations on one core-
increases the heat Dissipation
 CMP – Chip Multiprocessors solves the issue without
increasing the frequency of each core
 Last level cache(LLC) – Shared memory for cores –
Usually composed of SRAM’s – High leakage power

4. Problem DescriptionProblem Description
SRAM STT-RAM
Density 1X 4X
Read Time Very fast Fast
Write Time Very fast Slow
Read Energy Low Low
Write Energy Low High
Leakage Energy High Low
Endurance 10^16 4*10^12
SRAM has high leakage power and STT-RAM requires
high write energy and write latency is more

5. Hybrid Cache ArchitectureHybrid Cache Architecture
 Problem: Local Bank
suffers from more
write counts and
wears out fast.
 Non-Uniform
distribution of
workload among
different memory
banks

6. Hybrid Cache ArchitectureHybrid Cache Architecture
Part of local bank consists of
SRAM cells and remaining
part consists of STT-RAM cells
This decreases the write
pressure on the local bank
(Banks)
(Write
count)
Showing the unequal workload

7. Hybrid Cache ArchitectureHybrid Cache Architecture
 All writes on non-hybrid local bank are
redirected to SRAM bank and only few writes of
local hybrid bank are redirected to SRAM cell

8. Access Aware PoliciesAccess Aware Policies
 STT-RAM Write Management Policy

9. Access Aware PoliciesAccess Aware Policies
 SRAM Read Management Policy (Increases Write Utilization of SRAM)

10. Access Aware PoliciesAccess Aware Policies
 Dynamic Cache Partitioning
1) Which Partition size needs to be changed
2) Which region in a partition needs to be changed
• Ideally WPSW should be high
•WPNW should be minimum or
less

11. Access Aware PoliciesAccess Aware Policies
 Cache Partitioning Algorithm

12. Performance AnalysisPerformance Analysis
Unbalanced Write distribution on different banks

13. Performance AnalysisPerformance Analysis
Improved Write counts on local and non-local
banks with Hybrid Cache

14. Performance AnalysisPerformance Analysis
Increase of lifetime with Hybrid cache Write counts on STT-RAM

15. Performance AnalysisPerformance Analysis
Variations with respect to changes in the SRAM size in
Local Hybrid Bank

16. ConclusionConclusion
 CMP Architecture – No. of operations can be
increased working with same frequency
 Hybrid Cache – Balances the write distribution
among the banks
 Access Aware Policies – increases the write
utilization of SRAM and decreases the
endurance problem of STT-RAM cells
 Dynamic Cache Partitioning – Decreases the
hit latency, decreases the cache miss rate.

17. Thank you
Any Questions?