This document discusses lightweight cryptography techniques for RFID systems with limited resources. It compares the Data Encryption Standard (DES) algorithm and a simplified version called Lightweight DES (DESL). DESL reduces gate complexity by eliminating initial/final permutations and using a single S-box, providing around a 20% reduction in gates compared to DES while maintaining throughput. The document also briefly introduces the Advanced Encryption Standard (AES) algorithm.
This document discusses lightweight cryptography. It begins by defining lightweight cryptography as cryptographic primitives designed for devices with limited resources like memory, speed and power consumption. It then outlines various lightweight cryptographic mechanisms like block ciphers, hash functions, stream ciphers and authenticated ciphers. For each mechanism, it discusses their desirable properties and design principles. It also discusses implementation issues like decryption costs and resistance to related key attacks. Finally, it mentions the Fair Evaluation of Lightweight Cryptographic Systems (FELICS) benchmarking tool for evaluating and comparing the performance of lightweight cryptographic algorithms on different platforms.
Малоресурсная криптография - Сергей МартыненкоHackIT Ukraine
Презентация с форума http://hackit-ukraine.com/
Сергей Мартыненко
Ст.преп. кафедры комп. систем и сетей, ХАИ
Малоресурсная криптография
О спикере: Ст. преподаватель кафедры компьютерных сетей и систем. Опыт в области криптографической защиты информации и критических систем более 5 лет. Занимается защитой информации в малоресурсных системах.
Proposed Lightweight Block Cipher Algorithm for Securing Internet of ThingsSeddiq Q. Abd Al-Rahman
The presentation of paper is published in The 3rd International Conference on Computing, Communications, and Information Technology 24-25 April 2019, Organized by College of Computer Science and IT, University of Anbar, Ramadi, Iraq
The document discusses lightweight cryptography for constrained devices. It presents the objectives of designing a lightweight bit-permutation instruction called PERMS to accelerate cryptography in software, and a new lightweight block cipher called Khudra suitable for both FPGAs and ASICs. It also aims to analyze Khudra's security against cryptanalysis techniques. The PERMS instruction is based on bit swapping to achieve permutation efficiently in hardware using control bits.
High throughput implementations of cryptography algorithms on GPU and FPGAnitin3940
This document summarizes a seminar presentation on implementing cryptography algorithms with high throughput on GPUs and FPGAs. It introduces tiny encryption algorithm (TEA) and an extended version of TEA (XTEA) as lightweight cryptography algorithms suitable for hardware acceleration. It describes implementing TEA and XTEA on GPUs and FPGAs using cryptographic co-processors and hardware acceleration tools. Results show that FPGAs perform better for smaller plaintext sizes while GPUs achieve higher throughput for larger plaintext sizes.
Hardware Implementation of Algorithm for Cryptanalysisijcisjournal
Cryptanalysis of block ciphers involves massive computations which are independent of each other and can
be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low
cost Field Programmable Gate Arrays (FPGA’s), building special purpose hardware for computationally
intensive applications has now become possible. For this the Data Encryption Standard (DES) is used as a
proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on
FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared
and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this
work is to make cryptanalysis faster and better.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document describes the Hummingbird ultra-lightweight cryptographic algorithm targeted for resource-constrained devices. It presents the hybrid model of Hummingbird which combines a block cipher and stream cipher. The algorithm uses a 256-bit key, 80-bit internal state, and 16-bit blocks. It consists of four 16-bit block ciphers and registers that encrypt plaintext blocks through consecutive operations. Simulation results show it encrypting a sample plaintext into ciphertext on an FPGA with lower area requirements than other lightweight algorithms. The algorithm is suitable for high-security embedded applications with limited resources.
This document discusses lightweight cryptography. It begins by defining lightweight cryptography as cryptographic primitives designed for devices with limited resources like memory, speed and power consumption. It then outlines various lightweight cryptographic mechanisms like block ciphers, hash functions, stream ciphers and authenticated ciphers. For each mechanism, it discusses their desirable properties and design principles. It also discusses implementation issues like decryption costs and resistance to related key attacks. Finally, it mentions the Fair Evaluation of Lightweight Cryptographic Systems (FELICS) benchmarking tool for evaluating and comparing the performance of lightweight cryptographic algorithms on different platforms.
Малоресурсная криптография - Сергей МартыненкоHackIT Ukraine
Презентация с форума http://hackit-ukraine.com/
Сергей Мартыненко
Ст.преп. кафедры комп. систем и сетей, ХАИ
Малоресурсная криптография
О спикере: Ст. преподаватель кафедры компьютерных сетей и систем. Опыт в области криптографической защиты информации и критических систем более 5 лет. Занимается защитой информации в малоресурсных системах.
Proposed Lightweight Block Cipher Algorithm for Securing Internet of ThingsSeddiq Q. Abd Al-Rahman
The presentation of paper is published in The 3rd International Conference on Computing, Communications, and Information Technology 24-25 April 2019, Organized by College of Computer Science and IT, University of Anbar, Ramadi, Iraq
The document discusses lightweight cryptography for constrained devices. It presents the objectives of designing a lightweight bit-permutation instruction called PERMS to accelerate cryptography in software, and a new lightweight block cipher called Khudra suitable for both FPGAs and ASICs. It also aims to analyze Khudra's security against cryptanalysis techniques. The PERMS instruction is based on bit swapping to achieve permutation efficiently in hardware using control bits.
High throughput implementations of cryptography algorithms on GPU and FPGAnitin3940
This document summarizes a seminar presentation on implementing cryptography algorithms with high throughput on GPUs and FPGAs. It introduces tiny encryption algorithm (TEA) and an extended version of TEA (XTEA) as lightweight cryptography algorithms suitable for hardware acceleration. It describes implementing TEA and XTEA on GPUs and FPGAs using cryptographic co-processors and hardware acceleration tools. Results show that FPGAs perform better for smaller plaintext sizes while GPUs achieve higher throughput for larger plaintext sizes.
Hardware Implementation of Algorithm for Cryptanalysisijcisjournal
Cryptanalysis of block ciphers involves massive computations which are independent of each other and can
be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low
cost Field Programmable Gate Arrays (FPGA’s), building special purpose hardware for computationally
intensive applications has now become possible. For this the Data Encryption Standard (DES) is used as a
proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on
FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared
and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this
work is to make cryptanalysis faster and better.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The document describes the Hummingbird ultra-lightweight cryptographic algorithm targeted for resource-constrained devices. It presents the hybrid model of Hummingbird which combines a block cipher and stream cipher. The algorithm uses a 256-bit key, 80-bit internal state, and 16-bit blocks. It consists of four 16-bit block ciphers and registers that encrypt plaintext blocks through consecutive operations. Simulation results show it encrypting a sample plaintext into ciphertext on an FPGA with lower area requirements than other lightweight algorithms. The algorithm is suitable for high-security embedded applications with limited resources.
Analysis of symmetric key cryptographic algorithmsIRJET Journal
This document analyzes and compares several symmetric key cryptographic algorithms. It begins with an introduction about the importance of data security and encryption. Then it provides an overview of symmetric key cryptography and describes the basic process of using a shared secret key for encryption and decryption. The rest of the document summarizes and compares the most common symmetric algorithms including DES, 3DES, IDEA, AES, RC4, RC5, RC6, and Blowfish. It analyzes the key details of how each algorithm works including block size, number of rounds, and security issues. The conclusion is that symmetric key cryptography is important for data security and continues to be improved through ongoing research.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
With increasing technology development in field of communication and Electronic devices, there is a need for better security service for information transfer in Medical Sectors, Banking, Financial and in other IoT applications etc. Fight against security attacks is of prime importance. Through Cryptographic techniques we can provide Authenticity as well as Confidentiality for the user data. In this paper, hardware implementation has been described for a real-time application of speech data encryption and decryption using AES algorithm along with the speech recognition using cross correlation technique. Verilog programming environment is used for AES cryptography whereas MATLAB is used for Speech recognition. ASIC design on AES core is implemented using Cadence tools. Number of gates, area and power used by AES core design has been drastically reduced by specifying wide range of constraints during front end designing. In Backend designing, layout of AES design, which is the physical geometric representation is also developed.
Wireless Network Security Architecture with Blowfish Encryption ModelIOSR Journals
Abstract: In this research paper ,we developed a model for a large network, wireless nodes are interconnected and each can be considered as a node processor that offer services to other node processors connected to a specific network. A very high proportion of the nodes that offer services need to carry out an authentication process so as to make an access request to the node offering the service. In this context, an integrated reconfigurable network security architecture moved to the application layer has become the need of the day for secure wireless data sharing. The security schemes of the seven layer OSI architecture need to be placed intrinsically in the wireless node itself and should be capable of supporting the MAC layer, IP address based layer and the routing protocols of the network layer. This work focuses on the use of emulator and embedded hardware architectures for wireless network security. In this work, the individual nodes can have a unique security signature pattern maintained by respective wireless nodes using an encryption algorithm and this is made dynamic. The metrics includes latency, throughput, Scalability, Effects of data transfer operation on node processor and application data located in the processor Keywords:Wireless Network security, Embedded hardware, Reconfigurable architecture, blowfish algorithm
A Survey on Generation and Evolution of Various Cryptographic TechniquesIRJET Journal
This document summarizes previous research that has surveyed and compared various symmetric key cryptographic techniques. Several studies analyzed the performance of algorithms like DES, 3DES, AES, Blowfish, RC4 in terms of encryption/decryption time, memory usage, power consumption, throughput, and security against attacks. Most found that Blowfish had among the best performance overall, being fast and requiring few resources while maintaining strong security. AES generally required more processing power and time than alternatives like DES or RC4. The performance of algorithms could also vary based on file/data type, size, and the computing platform or operating system used.
This document proposes a hybrid encryption-decryption algorithm combining AES and DES. It implements the algorithm in VHDL using a Modelsim platform. The hybrid algorithm integrates AES into each iteration of DES's Feistel network, using AES operations like substitution and key addition. This increases computational complexity compared to the individual standards. The VHDL implementation includes modules for AES encryption/decryption and the hybrid algorithm. Simulations validate the code works correctly. Future work could increase iterations to suit different security levels or implement a 128-bit AES variant. The hybrid approach strengthens AES security against attacks.
A Secure Data Communication System Using Cryptography and SteganographyIJCNCJournal
The information security has become one of the most significant problems in data communication. So it
becomes an inseparable part of data communication. In order to address this problem, cryptography and
steganography can be combined. This paper proposes a secure communication system. It employs
cryptographic algorithm together with steganography. The jointing of these techniques provides a robust
and strong communication system that able to withstand against attackers. In this paper, the filter bank
cipher is used to encrypt the secret text message, it provide high level of security, scalability and speed.
After that, a discrete wavelet transforms (DWT) based steganography is employed to hide the encrypted
message in the cover image by modifying the wavelet coefficients. The performance of the proposed system
is evaluated using peak signal to noise ratio (PSNR) and histogram analysis. The simulation results show
that, the proposed system provides high level of security.
Pairing Based Elliptic Curve Cryptosystem for Message AuthenticationIJTET Journal
This document summarizes a research paper on using elliptic curve cryptography for message authentication. It begins with an introduction to elliptic curve cryptography and how it can provide equivalent security to other public key encryption methods but with smaller key sizes. It then describes the proposed methodology which includes generating an ECC key pair, encrypting a message with the public key, transmitting the encrypted message, and decrypting it with the private key. The results show a message being encrypted and decrypted correctly using this ECC process. It concludes that ECC can provide an efficient method for authentication in systems like vehicular networks due to its lower computation and communication overhead compared to other encryption methods.
This document discusses database access pattern protection using a partial shuffle scheme. It proposes a new encryption algorithm called Reverse Encryption Algorithm (REA) that aims to provide security while limiting performance degradation from encryption. It also discusses prior work on Private Information Retrieval (PIR) techniques and their limitations. The key idea of the proposed scheme is to introduce a trusted component that shuffles only a portion of the database periodically, providing privacy assurances similar to PIR but with lower computation costs than a full database shuffle each time.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
In today’s network-based cloud computing era, software applications are playing big role. The security of these software applications is paramount to the successful use of these applications. These applications utilize cryptographic algorithms to secure the data over the network through encryption and decryption
processes. The use of parallel processors is now common in both mobile and cloud computing scenarios.
Cryptographic algorithms are compute intensive and can significantly benefit from parallelism. This paper
introduces a parallel approach to symmetric stream cipher security algorithm known as RC4A, which is
one of the strong variants of RC4. We present an efficient parallel implementation to the compute intensive
PRGA that is pseudo-random generation algorithm portion of the RC4A algorithm and the resulted
algorithm will be named as PARC4-I. We have added some functionality in terms of lookup tables.
Modified algorithm is having four lookup tables instead of two and is capable of returning four distinct
output bytes at each iteration. Further, with the help of Parallel Additive Stream Cipher Structure and loop
unrolling method, encryption/decryption is being done on multi core machine. Finally, the results shows
that PARC4-I is a time efficient algorithm.
A novel authenticated cipher for rfid systemsijcisjournal
In this paper, we present RBS (Redundant Bit Security) algorithm which is a low-complexity symmetric
encryption with a 132-bit secret key. In this algorithm redundant bits are distributed among plaintext data
bits to change the location of the plaintext bits in the transmitted data without changing their order. The
location of redundant bits inside the transmitted data represents the secret key between sender and
receiver. The algorithm provides integrity and authentication of the original data as well. The
implementation comparison of this algorithm with other algorithms confirms that it a good candidate for
resource-constraint devices such as RFID systems and wireless sensors.
This document summarizes a research paper that proposes a novel symmetric key cryptography algorithm (N-SKC) to improve data security in cloud computing. The N-SKC algorithm uses multiple computational steps, random operator and delimiter selections to encrypt data with the same key producing different ciphertexts. It is designed to protect against brute force attacks. The paper also proposes using RSA for key exchange between the cloud provider and user to secretly share a symmetric key for encryption. Experimental results testing the N-SKC algorithm show it produces different ciphertexts for the same plaintext and key.
Design and Implementation of Ipv6 Address Using Cryptographically Generated A...IJERA Editor
The document discusses improvements to the Cryptographically Generated Addresses (CGA) method used in IPv6 addressing. CGA allows devices to automatically generate secure IPv6 addresses. However, the computation required for high security levels makes CGA impractical for many applications. The proposed improvements reduce the security parameter from 16 to 8 bits, making CGA generation faster and more feasible while still providing adequate security for most applications. The improvements were implemented using C programming language on Linux, and evaluate reducing the computational overhead of CGA generation to make it more practical.
Secrecy and Performance Analysis of Symmetric Key Encryption AlgorithmsTharindu Weerasinghe
The document analyzes the secrecy and performance of symmetric key encryption algorithms including block ciphers (DES, TripleDES, AES), stream ciphers (RC2, RC4) and hybrid algorithms combining block and stream ciphers (TripleDES+RC4, AES+RC4). The analysis is conducted based on two measurement criteria (secrecy of ciphers and encryption time) under two circumstances (variable input plaintext size and variable input plaintext length representing passwords). Results are presented in a table showing average secrecy values for each algorithm over varying input data sizes. The tool created allows users to select an algorithm and see corresponding performance and secrecy results.
“Proposed Model for Network Security Issues Using Elliptical Curve Cryptography”IOSR Journals
Abstract: Elliptic Curve Cryptography (ECC) plays an important role in today’s public key based security
systems. . ECC is a faster and more secure method of encryption as compared to other Public Key
Cryptographic algorithms. This paper focuses on the performance advantages of using ECC in the wireless
network. So in this paper its algorithm has been implemented and analyzed for various bit length inputs. The
Private key is known only to sender and receiver and hence data transmission is secure.
IRJET - Implementation of DNA Cryptography in Cloud Computing and using S...IRJET Journal
This document discusses implementing DNA cryptography in cloud computing using socket programming. It proposes using a bi-directional DNA encryption algorithm (BDEA) that provides two layers of security. The BDEA encrypts plaintext into a DNA digital code using binary-to-DNA conversion tables, then a key combination is used to generate an amplified message. Encryption and decryption involve converting between binary, DNA digital code, and the amplified message. Snapshots demonstrate the encryption and decryption processes. Implementing BDEA in cloud computing on Amazon Web Services is discussed. The approach aims to enhance data security for non-English users compared to existing techniques.
RSA is one of the most popular Public Key Cryptography based algorithm mainly used for digital
signatures, encryption/decryption etc. It is based on the mathematical scheme of factorization of very large
integers which is a compute-intensive process and takes very long time as well as power to perform.
Several scientists are working throughout the world to increase the speedup and to decrease the power
consumption of RSA algorithm while keeping the security of the algorithm intact. One popular technique
which can be used to enhance the performance of RSA is parallel programming. In this paper we are
presenting the survey of various parallel implementations of RSA algorithm involving variety of hardware
and software implementations.
IRJET- Enhancement of Efficiant Data Security Algorithm using Combined AES an...IRJET Journal
This document proposes a new algorithm to enhance data security by combining AES and rail fence encryption techniques. It describes encrypting plaintext using a rail fence technique with multiple transpositions, and then decrypting the ciphertext. The goal is to increase complexity and security by adding multiple encryption steps. Flowcharts and pseudocode are provided to illustrate the encryption and decryption processes. Prior research on rail fence and other ciphers is reviewed to show room for improvement in security.
Design and implementation of proposed 320 bit RC6-cascaded encryption/decrypt...IJECEIAES
This paper attempts to build up a simple, strong and secure cryptographic algorithm. The result of such an attempt is “RC6-Cascade” which is 320-bits RC6 like block cipher. The key can be any length up to 256 bytes. It is a secret-key block cipher with precise characteristics of RC6 algorithm using another overall structure design. In RC6-Cascade, cascading of F-functions will be used instead of rounds. Moreover, the paper investigates a hardware design to efficiently implement the proposed RC6-Cascade block cipher core on field programmable gate array (FPGA). An efficient compact iterative architecture will be designed for the F-function of the above algorithm. The goal is to design a more secure algorithm and present a very fast encryption core for low cost and small size applications.
Blind Signature Scheme Based On Elliptical Curve Cryptography (ECC)IOSR Journals
This document summarizes a blind signature scheme based on elliptic curve cryptography. It begins with an introduction to cryptography and the history of cryptography. It then discusses symmetric key cryptography, asymmetric key cryptography including public and private key pairs. It describes digital signatures, how they are generated and verified. It introduces the concept of blind signatures, how a message can be signed without revealing its contents to the signer. It discusses the mathematics behind elliptic curves and elliptic curve cryptography. It describes how to represent points on an elliptic curve and perform operations like point addition. The document focuses on implementing a blind digital signature scheme using elliptic curve cryptography.
Social Case History Forum 2016: - #inflUTILITY in azione: il caso POLLIYourBrand.Camp
Polli Social Food, il progetto YourBrand.Camp per Polli, che ha visto la partecpazione di tre ambassador speciali, in grado di esprimere liberamente la loro creatività. Presentazione di Flavia Rubino, Founder di YBC, al Social Case History Forum (Milano, 17 Novembre 2016)
Analysis of symmetric key cryptographic algorithmsIRJET Journal
This document analyzes and compares several symmetric key cryptographic algorithms. It begins with an introduction about the importance of data security and encryption. Then it provides an overview of symmetric key cryptography and describes the basic process of using a shared secret key for encryption and decryption. The rest of the document summarizes and compares the most common symmetric algorithms including DES, 3DES, IDEA, AES, RC4, RC5, RC6, and Blowfish. It analyzes the key details of how each algorithm works including block size, number of rounds, and security issues. The conclusion is that symmetric key cryptography is important for data security and continues to be improved through ongoing research.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
With increasing technology development in field of communication and Electronic devices, there is a need for better security service for information transfer in Medical Sectors, Banking, Financial and in other IoT applications etc. Fight against security attacks is of prime importance. Through Cryptographic techniques we can provide Authenticity as well as Confidentiality for the user data. In this paper, hardware implementation has been described for a real-time application of speech data encryption and decryption using AES algorithm along with the speech recognition using cross correlation technique. Verilog programming environment is used for AES cryptography whereas MATLAB is used for Speech recognition. ASIC design on AES core is implemented using Cadence tools. Number of gates, area and power used by AES core design has been drastically reduced by specifying wide range of constraints during front end designing. In Backend designing, layout of AES design, which is the physical geometric representation is also developed.
Wireless Network Security Architecture with Blowfish Encryption ModelIOSR Journals
Abstract: In this research paper ,we developed a model for a large network, wireless nodes are interconnected and each can be considered as a node processor that offer services to other node processors connected to a specific network. A very high proportion of the nodes that offer services need to carry out an authentication process so as to make an access request to the node offering the service. In this context, an integrated reconfigurable network security architecture moved to the application layer has become the need of the day for secure wireless data sharing. The security schemes of the seven layer OSI architecture need to be placed intrinsically in the wireless node itself and should be capable of supporting the MAC layer, IP address based layer and the routing protocols of the network layer. This work focuses on the use of emulator and embedded hardware architectures for wireless network security. In this work, the individual nodes can have a unique security signature pattern maintained by respective wireless nodes using an encryption algorithm and this is made dynamic. The metrics includes latency, throughput, Scalability, Effects of data transfer operation on node processor and application data located in the processor Keywords:Wireless Network security, Embedded hardware, Reconfigurable architecture, blowfish algorithm
A Survey on Generation and Evolution of Various Cryptographic TechniquesIRJET Journal
This document summarizes previous research that has surveyed and compared various symmetric key cryptographic techniques. Several studies analyzed the performance of algorithms like DES, 3DES, AES, Blowfish, RC4 in terms of encryption/decryption time, memory usage, power consumption, throughput, and security against attacks. Most found that Blowfish had among the best performance overall, being fast and requiring few resources while maintaining strong security. AES generally required more processing power and time than alternatives like DES or RC4. The performance of algorithms could also vary based on file/data type, size, and the computing platform or operating system used.
This document proposes a hybrid encryption-decryption algorithm combining AES and DES. It implements the algorithm in VHDL using a Modelsim platform. The hybrid algorithm integrates AES into each iteration of DES's Feistel network, using AES operations like substitution and key addition. This increases computational complexity compared to the individual standards. The VHDL implementation includes modules for AES encryption/decryption and the hybrid algorithm. Simulations validate the code works correctly. Future work could increase iterations to suit different security levels or implement a 128-bit AES variant. The hybrid approach strengthens AES security against attacks.
A Secure Data Communication System Using Cryptography and SteganographyIJCNCJournal
The information security has become one of the most significant problems in data communication. So it
becomes an inseparable part of data communication. In order to address this problem, cryptography and
steganography can be combined. This paper proposes a secure communication system. It employs
cryptographic algorithm together with steganography. The jointing of these techniques provides a robust
and strong communication system that able to withstand against attackers. In this paper, the filter bank
cipher is used to encrypt the secret text message, it provide high level of security, scalability and speed.
After that, a discrete wavelet transforms (DWT) based steganography is employed to hide the encrypted
message in the cover image by modifying the wavelet coefficients. The performance of the proposed system
is evaluated using peak signal to noise ratio (PSNR) and histogram analysis. The simulation results show
that, the proposed system provides high level of security.
Pairing Based Elliptic Curve Cryptosystem for Message AuthenticationIJTET Journal
This document summarizes a research paper on using elliptic curve cryptography for message authentication. It begins with an introduction to elliptic curve cryptography and how it can provide equivalent security to other public key encryption methods but with smaller key sizes. It then describes the proposed methodology which includes generating an ECC key pair, encrypting a message with the public key, transmitting the encrypted message, and decrypting it with the private key. The results show a message being encrypted and decrypted correctly using this ECC process. It concludes that ECC can provide an efficient method for authentication in systems like vehicular networks due to its lower computation and communication overhead compared to other encryption methods.
This document discusses database access pattern protection using a partial shuffle scheme. It proposes a new encryption algorithm called Reverse Encryption Algorithm (REA) that aims to provide security while limiting performance degradation from encryption. It also discusses prior work on Private Information Retrieval (PIR) techniques and their limitations. The key idea of the proposed scheme is to introduce a trusted component that shuffles only a portion of the database periodically, providing privacy assurances similar to PIR but with lower computation costs than a full database shuffle each time.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
In today’s network-based cloud computing era, software applications are playing big role. The security of these software applications is paramount to the successful use of these applications. These applications utilize cryptographic algorithms to secure the data over the network through encryption and decryption
processes. The use of parallel processors is now common in both mobile and cloud computing scenarios.
Cryptographic algorithms are compute intensive and can significantly benefit from parallelism. This paper
introduces a parallel approach to symmetric stream cipher security algorithm known as RC4A, which is
one of the strong variants of RC4. We present an efficient parallel implementation to the compute intensive
PRGA that is pseudo-random generation algorithm portion of the RC4A algorithm and the resulted
algorithm will be named as PARC4-I. We have added some functionality in terms of lookup tables.
Modified algorithm is having four lookup tables instead of two and is capable of returning four distinct
output bytes at each iteration. Further, with the help of Parallel Additive Stream Cipher Structure and loop
unrolling method, encryption/decryption is being done on multi core machine. Finally, the results shows
that PARC4-I is a time efficient algorithm.
A novel authenticated cipher for rfid systemsijcisjournal
In this paper, we present RBS (Redundant Bit Security) algorithm which is a low-complexity symmetric
encryption with a 132-bit secret key. In this algorithm redundant bits are distributed among plaintext data
bits to change the location of the plaintext bits in the transmitted data without changing their order. The
location of redundant bits inside the transmitted data represents the secret key between sender and
receiver. The algorithm provides integrity and authentication of the original data as well. The
implementation comparison of this algorithm with other algorithms confirms that it a good candidate for
resource-constraint devices such as RFID systems and wireless sensors.
This document summarizes a research paper that proposes a novel symmetric key cryptography algorithm (N-SKC) to improve data security in cloud computing. The N-SKC algorithm uses multiple computational steps, random operator and delimiter selections to encrypt data with the same key producing different ciphertexts. It is designed to protect against brute force attacks. The paper also proposes using RSA for key exchange between the cloud provider and user to secretly share a symmetric key for encryption. Experimental results testing the N-SKC algorithm show it produces different ciphertexts for the same plaintext and key.
Design and Implementation of Ipv6 Address Using Cryptographically Generated A...IJERA Editor
The document discusses improvements to the Cryptographically Generated Addresses (CGA) method used in IPv6 addressing. CGA allows devices to automatically generate secure IPv6 addresses. However, the computation required for high security levels makes CGA impractical for many applications. The proposed improvements reduce the security parameter from 16 to 8 bits, making CGA generation faster and more feasible while still providing adequate security for most applications. The improvements were implemented using C programming language on Linux, and evaluate reducing the computational overhead of CGA generation to make it more practical.
Secrecy and Performance Analysis of Symmetric Key Encryption AlgorithmsTharindu Weerasinghe
The document analyzes the secrecy and performance of symmetric key encryption algorithms including block ciphers (DES, TripleDES, AES), stream ciphers (RC2, RC4) and hybrid algorithms combining block and stream ciphers (TripleDES+RC4, AES+RC4). The analysis is conducted based on two measurement criteria (secrecy of ciphers and encryption time) under two circumstances (variable input plaintext size and variable input plaintext length representing passwords). Results are presented in a table showing average secrecy values for each algorithm over varying input data sizes. The tool created allows users to select an algorithm and see corresponding performance and secrecy results.
“Proposed Model for Network Security Issues Using Elliptical Curve Cryptography”IOSR Journals
Abstract: Elliptic Curve Cryptography (ECC) plays an important role in today’s public key based security
systems. . ECC is a faster and more secure method of encryption as compared to other Public Key
Cryptographic algorithms. This paper focuses on the performance advantages of using ECC in the wireless
network. So in this paper its algorithm has been implemented and analyzed for various bit length inputs. The
Private key is known only to sender and receiver and hence data transmission is secure.
IRJET - Implementation of DNA Cryptography in Cloud Computing and using S...IRJET Journal
This document discusses implementing DNA cryptography in cloud computing using socket programming. It proposes using a bi-directional DNA encryption algorithm (BDEA) that provides two layers of security. The BDEA encrypts plaintext into a DNA digital code using binary-to-DNA conversion tables, then a key combination is used to generate an amplified message. Encryption and decryption involve converting between binary, DNA digital code, and the amplified message. Snapshots demonstrate the encryption and decryption processes. Implementing BDEA in cloud computing on Amazon Web Services is discussed. The approach aims to enhance data security for non-English users compared to existing techniques.
RSA is one of the most popular Public Key Cryptography based algorithm mainly used for digital
signatures, encryption/decryption etc. It is based on the mathematical scheme of factorization of very large
integers which is a compute-intensive process and takes very long time as well as power to perform.
Several scientists are working throughout the world to increase the speedup and to decrease the power
consumption of RSA algorithm while keeping the security of the algorithm intact. One popular technique
which can be used to enhance the performance of RSA is parallel programming. In this paper we are
presenting the survey of various parallel implementations of RSA algorithm involving variety of hardware
and software implementations.
IRJET- Enhancement of Efficiant Data Security Algorithm using Combined AES an...IRJET Journal
This document proposes a new algorithm to enhance data security by combining AES and rail fence encryption techniques. It describes encrypting plaintext using a rail fence technique with multiple transpositions, and then decrypting the ciphertext. The goal is to increase complexity and security by adding multiple encryption steps. Flowcharts and pseudocode are provided to illustrate the encryption and decryption processes. Prior research on rail fence and other ciphers is reviewed to show room for improvement in security.
Design and implementation of proposed 320 bit RC6-cascaded encryption/decrypt...IJECEIAES
This paper attempts to build up a simple, strong and secure cryptographic algorithm. The result of such an attempt is “RC6-Cascade” which is 320-bits RC6 like block cipher. The key can be any length up to 256 bytes. It is a secret-key block cipher with precise characteristics of RC6 algorithm using another overall structure design. In RC6-Cascade, cascading of F-functions will be used instead of rounds. Moreover, the paper investigates a hardware design to efficiently implement the proposed RC6-Cascade block cipher core on field programmable gate array (FPGA). An efficient compact iterative architecture will be designed for the F-function of the above algorithm. The goal is to design a more secure algorithm and present a very fast encryption core for low cost and small size applications.
Blind Signature Scheme Based On Elliptical Curve Cryptography (ECC)IOSR Journals
This document summarizes a blind signature scheme based on elliptic curve cryptography. It begins with an introduction to cryptography and the history of cryptography. It then discusses symmetric key cryptography, asymmetric key cryptography including public and private key pairs. It describes digital signatures, how they are generated and verified. It introduces the concept of blind signatures, how a message can be signed without revealing its contents to the signer. It discusses the mathematics behind elliptic curves and elliptic curve cryptography. It describes how to represent points on an elliptic curve and perform operations like point addition. The document focuses on implementing a blind digital signature scheme using elliptic curve cryptography.
Social Case History Forum 2016: - #inflUTILITY in azione: il caso POLLIYourBrand.Camp
Polli Social Food, il progetto YourBrand.Camp per Polli, che ha visto la partecpazione di tre ambassador speciali, in grado di esprimere liberamente la loro creatività. Presentazione di Flavia Rubino, Founder di YBC, al Social Case History Forum (Milano, 17 Novembre 2016)
YourBrand.Camp: add value, not volume to your influencers.YourBrand.Camp
Introducing YourBrand.Camp, the first influencer marketing platform generating true advocacy through cocreation and collaboration. See how InfluTILITY works!
This document outlines safety policies and procedures for S.K.J. Engineering & Grading. It states that safety is a top priority and failure to comply with rules will result in discipline. It provides 23 rules for general office safety, including keeping exits clear, reporting injuries, using safe lifting techniques, and following electrical equipment guidelines. It also lists 25 rules for general maintenance and 27 rules for proper use of tools and equipment, including inspecting tools for damage and using appropriate safety gear like hard hats.
Training-Taking Charge of Your ClassroomAndrew Gaydos
This document provides guidance for Peace Corps volunteers on establishing an effective classroom culture and closing the gap between their teaching values and beliefs and their actual classroom practices. It recommends that volunteers first reflect on their teaching philosophy and then consider local classroom norms and student expectations to develop rules and policies that balance cultural appropriateness with their own values around topics like student behavior, assessments, and classroom roles. The document also suggests observing more experienced local teachers to understand cultural classroom conventions and looking to how students are socialized to learn classroom roles and behaviors implicitly through observation and experience. Finally, it emphasizes applying teaching values, like connecting lessons to students' lives, in culturally-sensitive classroom practices.
The document describes a student project to implement the User Datagram Protocol (UDP) in hardware using two FPGA development boards. The goals were to include a proper checksum calculation, demonstrate multiplexing and demultiplexing of ports, and introduce errors. UDP segments were sent between the boards using a simple bus protocol to simulate network transmission. The project provides a platform for exploring how UDP works and customizable hardware implementation of transport protocols.
Everything you needed to know about CERFLON®:
A reinforced PTFE occurs when a ceramic compound,
Boron Nitride, which is stronger and tougher, is
introduced into the matrix of this fluoropolymer,
thereby “reinforcing” the polymer.
1. YourBrand.Camp is a platform that allows brands to collaborate with influencers to develop authentic and engaging content through co-creation.
2. Influencers are selected and rewarded for joining brand campaigns where they generate ideas, stories, and content that promote the brands' messages.
3. The platform aims to foster advocacy over just visibility by empowering influencers and stimulating their creativity, which results in better content and returns for brands in the form of engagement and calls-to-action.
This document provides guidance on designing rubrics to assess student work. It discusses holistic vs. analytic rubrics and the steps to build a rubric, including defining criteria and performance levels. Key aspects are deciding top and bottom achievement levels, and then determining intermediate standards. Descriptive language in rubrics should focus on relative frequencies of errors or qualities rather than specific numbers. Rubrics should be based on learning objectives and understandable by others. A sample rubric is built to assess hamburgers on qualities of the bun, condiments, cooking, and toppings.
Connettere le storie dei brand e le vite delle persone.
Presentazione di Flavia Rubino per Digitale Rosa, l'evento di formazione con le donne del Web Marketing italiano - Rimini 1 luglio 2016
This document discusses enhancing security in cloud storage using elliptic curve cryptography (ECC). It begins by outlining threats to data stored in the cloud, such as unauthorized access and reduced privacy. It then describes common security methods like encryption, authentication, and authorization. The document proceeds to explain the RSA algorithm for encryption and digital signatures. It subsequently provides details on how ECC generates cryptographic keys using elliptic curve theory, offering stronger security with smaller key sizes. ECC is thus more efficient for applications like mobile. The document concludes ECC is a secure and efficient alternative to RSA for key exchanges between certificate authorities and users.
Iot Conference Berlin M2M,IoT, device management: one protocol to rule them all?Julien Vermillard
M2M/IoT is rapidly growing and since its early days different “standard” protocols have emerged (e.g. OMA-DM, TR-069, MQTT, …) or are emerging (e.g. CoAP or Lightweight M2M). Understanding which protocol to use for which application can be intimidating, therefore we propose to give an overview of these protocols to help you understand their goals and characteristics. We’ll present common M2M use cases and why they usually require more than just one protocol ; we will also see whether CoAP associated with Lightweight M2M allows to forge “one protocol to rule them all”.
The document discusses the benefits of exercise for both physical and mental health. It notes that regular exercise can reduce the risk of diseases like heart disease and diabetes, improve mood, and reduce feelings of stress and anxiety. The document recommends that adults get at least 150 minutes of moderate exercise or 75 minutes of vigorous exercise per week to gain these benefits.
1) The document proposes a hybrid 128-bit key AES-DES algorithm to enhance data security and transmission security for next generation networks.
2) It discusses some weaknesses in the AES encryption algorithm against algebraic cryptanalysis and outlines a hybrid approach that combines AES and DES algorithms.
3) The hybrid approach integrates the AES encryption process within the Feistel network structure of DES, using AES transformations like byte substitution and shift rows within each round of the DES Feistel network. This is intended to strengthen security by combining the advantages of both algorithms while reducing individual weaknesses.
Novel Adaptive Hold Logic Circuit for the Multiplier using Add Round Key and ...IJMTST Journal
Digital multipliers are among the most critical arithmetic functional units in many applications, such as the Fourier transform, discrete cosine transforms, and digital filtering. The through put of these applications depends on multipliers, if the multipliers are too slow, the performance of entire circuits will be reduced. The negative bias temperature instability effect occurs when a PMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of a PMOS transistor and reducing the multiplier speed. Similarly, positive bias temperature instability occurs when an NMOS transistor is under positive bias. Both effects degrade the speed of the transistor and in the long term, the system may be fail due to timing violations. Therefore, it is required to design reliable high-performance multipliers. In this paper, we implement an aging aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide the higher throughput through the variable latency and can adjust the adaptive hold logic (AHL) circuit to lessen performance degradation that is due to the aging effect. The proposed design can be applied to the column bypass multiplier.
The document describes the implementation of the Advanced Encryption Standard (AES) algorithm in Matlab. It includes:
1) An introduction to AES that describes its motivation, definitions, requirements and overall processes.
2) A high-level design section explaining the AES algorithm, its overall structure consisting of key expansion, encryption and decryption processes using operations like SubBytes, ShiftRows, MixColumns and AddRoundKey.
3) A detailed design section describing the individual operations for both encryption and decryption, including pseudo-code. It also provides illustrations of the operations.
4) Sections on key expansion and results from implementing the AES algorithm in Matlab.
Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microbl...IJECEIAES
Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.
New modification on feistel DES algorithm based on multi-level keys IJECEIAES
The data encryption standard (DES) is one of the most common symmetric encryption algorithms, but it experiences many problems. For example, it uses only one function (XOR) in the encryption process, and the combination of data is finite because it occurs only twice and operates on bits. This paper presents a new modification of the DES to overcome these problems. This could be done through adding a new level of security by increasing the key space (using three keys) during the 16 rounds of the standard encryption algorithm and by replacing the predefined XOR operation with a new # operation. Our proposed algorithm uses three keys instead of one. The first key is the input key used for encrypting and decrypting operations. The second key is used for determining the number of bits, while the third key is used for determining the table numbers, which are from 0 to 255. Having evaluated the complexity of our proposed algorithm, the results show that it is the most complex compared with the well-known DES and other modified algorithms. Consequently, in our proposed algorithm, the attacker try a number of attempts 2 1173 at minimum to decrypt the message. This means that the proposed DES algorithm will increase the security level of the well-known DES.
An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithmijsrd.com
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S -box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
This document describes the implementation of the AES (Advanced Encryption Standard) algorithm using a fully pipelined design on an FPGA. It first provides background on the AES algorithm, including its key components and previous hardware implementations. It then details the proposed fully pipelined design, which implements each of AES's 10 rounds as separate pipeline stages to achieve high throughput. Key generation is also pipelined internally. Simulation results show the design achieves a throughput higher than previous reported implementations.
The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data also called Rijndael. The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data. Hardware-based cryptography is used for authentication of users and of software updates and installations. Software implementations can generally not be used for this, as the cryptographic keys are stored in the PC memory during execution, and are vulnerable to malicious codes. Hardware-based encryption products can also vary in the level of protection they provide against brute force rewind attacks, Offline parallel attacks, or other cryptanalysis attacks. The algorithm was implemented in FPGA due to its flexibility and reconfiguration capability. A reconfigurable device is very convenient for a cryptography algorithm since it allows cheap and quick alterations. The implementation of pipelined cryptography hardware was used to improve performance in order to achieve higher throughput and greater parallelism. The AES hardware was implemented in three modules contains of the encryption, the decryption and the key expansion module.
There is great research in the field of data security these days. Storing information digitally in the cloud and transferring it over the internet proposes risks of disclosure and unauthorized access, thus users, organizations and businesses are adapting new technology and methods to protect their data from breaches. In this paper, we introduce a method to provide higher security for data transferred over the internet, or information based in the cloud. The introduced method for the most part depends on the Advanced Encryption Standard (AES) algorithm. Which is currently the standard for secret key encryption. A standardized version of the algorithm was used by The Federal Information Processing Standard 197 called Rijndael for the Advanced Encryption Standard. The AES algorithm processes data through a combination of Exclusive-OR operations (XOR), octet substitution with an S-box, row and column rotations, and a MixColumn operations. The fact that the algorithm could be easily implemented and run on a regular computer in a reasonable amount of time made it highly favorable and successful.
In this paper, the proposed method provides a new dimension of security to the AES algorithm by securing the key itself such that even when the key is disclosed, the text cannot be deciphered. This is done by enciphering the key using Output Feedback Block Mode Operation. This introduces a new level of security to the key in a way in which deciphering the data requires prior knowledge of the key and the algorithm used to encipher the key for the purpose of deciphering the transferred text.
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An Efficient VLSI Design of AES Cryptography Based on DNA TRNG DesignIRJET Journal
This document describes an efficient VLSI design for AES cryptography using a true random number generator (TRNG) and DNA encoding. It aims to improve security and reduce area and delay compared to standard AES. The design generates random round keys using a TRNG instead of the standard key expansion process. It further encodes a partial key from the TRNG using DNA encoding to produce the full 128-bit key, strengthening security. Simulation and synthesis results show the TRNG-based AES has lower area and delay than standard AES. Combining the TRNG with DNA encoding further optimizes the design.
This document presents new software speed records for AES-128 encryption and decryption on various platforms including 8-bit AVR microcontrollers, NVIDIA GPUs, and the Cell broadband engine. The key findings are that the AVR implementation requires 124.6 and 181.3 cycles per byte for encryption and decryption respectively while using less than 2KB of code size. For the Cell, byte-sliced implementations achieve 11.7 and 14.4 cycles per byte. The fastest GPU implementation delivers throughputs of 0.17 and 0.19 cycles per byte for encryption and decryption handling multiple input streams in parallel.
An Efficient VLSI Architecture for AES and It's FPGA ImplementationIRJET Journal
This document discusses the design and FPGA implementation of an efficient VLSI architecture for the AES encryption algorithm. It begins with an introduction to cryptography and the AES algorithm. It then describes the key components of AES including the state array, substitution bytes, shift rows, mix columns, add round key transformations, and key expansion. The document proposes a pipelined design to reduce encryption delay by generating round keys in parallel with encryption rounds. Simulation results show this pipelined AES architecture can operate at higher clock frequencies, increasing encryption throughput for time-critical applications. In conclusion, the hardware implementation provides faster encryption speeds and higher throughput compared to a software solution.
IMPLEMENTATION OF AES AS A CUSTOM HARDWARE USING NIOS II PROCESSORacijjournal
This document describes the implementation of the Advanced Encryption Standard (AES) algorithm as a custom hardware accelerator connected to a Nios II processor system. AES was written in VHDL and connected to the Nios II system through GPIO pins. This allows AES operations to be controlled through C code in the Nios II IDE while running the AES algorithm in hardware, improving encryption speeds significantly compared to an all-software implementation. Synthesis results showed the hardware AES implementation reduced the number of clock cycles needed for encryption by over 99% compared to running AES solely in software on the Nios II processor.
The document discusses Feistel block ciphers and their structure. A Feistel cipher uses multiple rounds of processing on a plaintext block, with each round consisting of a substitution step followed by a permutation step. The block is divided into two halves, and in each round the left half is combined with the right half and key using a round function, while the right half remains unchanged. The halves are then swapped. Feistel ciphers like DES use different subkeys derived from the main key in each round. The decryption process follows the same structure but with subkeys used in reverse order.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
The document describes the design of a custom cryptographic processor for implementing symmetric key operations. The processor is implemented on an FPGA using Verilog. It includes instruction units to perform logical operations, arithmetic operations, and finite field arithmetic needed for symmetric key algorithms like AES, Blowfish, RC5, RC6, IDEA. The processor is pipelined for high speed and includes modules for an ALU, control unit, registers, and multiplexers. Experimental results showed the processor operates at high speed with low area and delay compared to a general purpose processor.
This document summarizes the key aspects of cryptanalysis and the Data Encryption Standard (DES) algorithm. It discusses the tasks of a cryptanalyst in breaking encryption systems and outlines the basic structure and operation of DES. DES encrypts 64-bit blocks using a 56-bit key and 16 rounds of encryption. Each round uses a 48-bit subkey and the Feistel network structure to provide diffusion and confusion. The document also notes concerns about the cryptographic strength of DES' 56-bit keys and 8 substitution boxes against attacks over time.
Welcome to International Journal of Engineering Research and Development (IJERD)IJERD Editor
The document compares the use of Tabu Search and Simulated Annealing algorithms for cryptanalysis of the Simplified Data Encryption Standard (S-DES) cipher. It provides background on S-DES encryption and describes how Tabu Search and Simulated Annealing work for solving combinatorial optimization problems like cryptanalysis. The paper analyzes the performance of each method on cryptanalyzing S-DES and finds that Tabu Search performs better than Simulated Annealing for this NP-Hard problem.
Arm recognition encryption by using aes algorithmeSAT Journals
Abstract To provide the security of the Military confidential data we use encryption algorithm which take over reward of superior encryption algorithm. The proposed implementation using encryption algorithm was implemented on ARM 7 to encrypt and decrypt the confidential data on data storage devices such as SD card or Pen drive. The main objective of proposed implementation is to provide protection for storage devices. The ARM and encryption algorithm protect the data accessibility, reliability and privacy successfully. Since (AES) Advanced Encryption Standard algorithm is widely used in an embedded system or fixed organization. These AES algorithms are used for proper designs in defense for security. Keywords: Plain text, Cipher text, Data security, AES, Embedded System.ARM, storage device.
High throughput FPGA Implementation of Advanced Encryption Standard AlgorithmTELKOMNIKA JOURNAL
The growth of computer systems and electronic communications and transactions has meant that the need for effective security and reliability of data communication, processing and storage is more important than ever. In this context, cryptography is a high priority research area in engineering. The Advanced Encryption Standard (AES) is a symmetric-key criptographic algorithm for protecting sensitive information and is one of the most widely secure and used algorithm today. High-throughput, low power and compactness have always been topic of interest for implementing this type of algorithm. In this paper, we are interested on the development of high throughput architecture and implementation of AES algorithm, using the least amount of hardware possible. We have adopted a pipeline approach in order to reduce the critical path and achieve competitive performances in terms of throughput and efficiency. This approach is effectively tested on the AES S-Box substitution. The latter is a complex transformation and the key point to improve architecture performances. Considering the high delay and hardware required for this transformation, we proposed 7-stage pipelined S-box by using composite field in order to deal with the critical path and the occupied area resources. In addition, efficient AES key expansion architecture suitable for our proposed pipelined AES is presented. The implementation had been successfully done on Virtex-5 XC5VLX85 and Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) devices using Xilinx ISE v14.7. Our AES design achieved a data encryption rate of 108.69 Gbps and used only 6361 slices ressource. Compared to the best previous work, this implementation improves data throughput by 5.6% and reduces the used slices to 77.69%.
High throughput FPGA Implementation of Advanced Encryption Standard Algorithm
Final report
1. EE260 Final Project P a g e | 1 Spring 2015
Lightweight Cryptography by Simplification of Hardware – A
comparison study
Jagbir Kalirai
Iswarya Muthu Kumar
RFID SYSTEMS
EE 260, Spring 2015
May 18, 2015
2. EE260 Final Project P a g e | 2 Spring 2015
ABSTRACT
Radio-frequency identification (RFID) system plays an important role for many applications.
Security comes into picture for a better system. As technology gets universal, the smart devices
are deployed in a huge spectrum of different fields, such as engineering structures, complex
organizations, handy and wearable purposes. The aspiration in such devices is openly analogous
to the tight budget and intrinsic in huge distributions, has partial sources for things like memory,
computing complexity, and power supply. The techniques for Lightweight Cryptography allow
us to deliver adequate security for the RFID tags while restricting the volume of essential sources
with the idea of Hardware Simplification. We studied methodologies to explore the lightweight
cryptographic techniques for block ciphers like DES, AES, Symmetric ciphers.
LIGHTWEIGHT CRYPTOGRAPHY
BACKGROUND
With the amount of resources limited on the tag, we must use algorithms which utilize fewer
resources, yet still provide sufficient security. Lightweight Security techniques enable us to
provide sufficient security for the tags while limiting the amount of required resources. The term
‘Lightweight’ does not imply ‘weak’, instead it is a term used for low-cost (in terms of on-tag
resources). And Lightweight Cryptography is designed specifically for use on constrained
platforms (such as an NFC or RFID tag). One way to implement Lightweight cryptography
within NFC or RFID tags is to use an existing standard that has been modified. In order to
understand the modification, we first must understand how the standard works.
Data Encryption Standard (DES)
We choose to look into Data Encryption Standard (DES) because of its’ ease to implement
within the hardware and that it’s a well-known standard that is used globally. DES was originally
published in 1977, and utilizes a 56 bit key and maps a 64-bit input block onto a 64-bit output
block. The key actually looks like 64-bits, but in each of its’ eight strings of 8 bit values; it uses
the 8th
bit as an odd parity bit. This leaves the key to be 56 bits. DES is efficient to implement in
hardware but performs slow when implemented in software.
The first step in DES encryption is to permutation the initial 64 bit data (shuffling input bits).
The 56 bit key is used to generate sixteen 48 bit keys. DES relies on shuffling the data for sixteen
rounds while using each of the sixteen 48 bit keys (one 48 bit key per round). The output after
the first round becomes the input for the second round, and so on. After the 16th
round, the first
32 bits of data are swapped with the last 32 bits, and the data is once again permutated. For
example, the 8th
bit in the initial permutation (numerical value ‘2’) implies the 2nd
bit holds a
numerical value of ‘8’ in the final permutation (IP-1
).
3. EE260 Final Project P a g e | 3 Spring 2015
During each round, the Mangler Function is used. The Mangler Function takes the 32 bit data
(Rn) and the 48 bit Kn and produces a 32 bit output which is XOR’d with the first half of the 64
bit data (Ln). Figure 2 shown below shows this procedure.
The Mangler Function takes the 32 bit data (Rn) and expands it to 48 bits. The original 32 bit
input is broken into eight blocks that are 4 bits each. The expansion is achieved by taking the last
bit of the first block of the 4 bit sequence and the first bit of the next 4 bit block and overlapping
those values as part of the 48 bit output. The new 48 bit sequence is then broken into eight 6 bit
blocks.
Now that the input data is expanded to 48 bits, it matches the 48 bit key. These values are then
XOR’d 6 bits at a time, and the S-Box outputs a 4 bit value for every 6 bits inputted. After the
process is completed, a 32 bit value is outputted which is them XOR’d with the first half of the
64 bit input.
In order to decrypt the data, we would simply reverse the process. As we can see, the process is
extensive and would require quite a bit of power to implement. Since the NFC and RFID tags we
are focusing on are passive, meaning they only get power when they are in the interrogation zone
of a reader, the DES algorithm would not be a suitable choice.
Lightweight DES (DESL)
There is a variation of DES that further reduce the amount of resources (DESL), it stems from
the original DES that is efficiently implemented and slightly modified. Efficiently implementing
DES can be used in a way that reduces the complexity of the gates, and makes the DES
algorithm lightweight as it reduces the amount of gates by 35% compared to the best AES
implementation that is known. (3) However, there is a drawback to this approach in that it has
uses less area at the cost of throughput.
In order to reduce the amount of gates we can modify the original DES implementation, this
makes the process lightweight. However, since the key will still be 56 bits, the amount of
security remains constant. There are two areas of the original DES flow where we can focus our
attention to begin reducing the amount of gates.
The first approach to making DES lightweight is to look at the initial and final permutations (IP
and IP-1
). These permutations are not needed as they do nothing for us in terms to encrypting the
data. Permutations simply shuffle the data that is already existent. Furthermore, the permutations
require additional wiring components when implemented through hardware.
The second method we can implement is to reduce the number of S-Boxes. If you recall, the
original DES approach was to expand the input data from 32 to 48 bits to match it with the key.
This data was then broken into eight blocks (6 bits each) and XOR’d to each of the eight S-
boxes. Eliminating the use of eight S-Boxes and using a single S-Box will reduce the gate
complexity.
4. EE260 Final Project P a g e | 4 Spring 2015
The following figure shown below highlights the architecture of the lightweight DES (DESL)
scheme. We can see the initial and final permutations have been eliminated as well as the
simplification of the S-Box (boxed in red).
Figure 1: Block diagram representation of one round within Lightweight DES (DESL)
It’s important to realize the security has not changed; DESL still utilizes the same 56-bit key as
DES. Brute force attacks have been reported to take a just a few months, and only a matter of
days when using specialized computers. DES or DESL should only be used for short term basis,
otherwise it too can be susceptible to security attacks.
Implementing DESL
A test was done by T. Eisenbarth, S. Kumar, C. Paar, A. Poschmann, and L. Uhsadel, where they
implemented DES and DESL into hardware to see what how many gates would be saved and
how it affects the efficiency. An ATMEL ATMega128 8-bit microcontroller was used to
demonstrate this. From Table 1 shown below Shows that a ~20% reduction of gates is possible,
while maintaining throughput and efficiency. This method also reduces the current required.
Table 1: Implementation of DES and DESL in hardware operating at 100 MHz
5. EE260 Final Project P a g e | 5 Spring 2015
Advanced Encryption Standard (AES)
The Advanced Encryption Standard (AES) also called as Rijndael is grounded on a design
called substitution-permutation network, as the name suggests, a blend of substitution and
permutation. The speed observed is both in software and hardware. It succeeds the above
mentioned design, Data Encryption Standard (DES). The Advanced Encryption Standard (AES)
postulates an appropriate Federal Information Processing Standard (FIPS) algorithm, which
involves cryptographic standards, which can be used to guard electronic data. In other words, it
can also be termed as an algorithm that employs a symmetric block cipher that can encipher and
decipher data. Encryption translates information to an incomprehensible procedure known as
cipher text; decoding the ciphered text translates the information to its original form, called plain
text. The algorithm is best suited for cryptographic keys of 128, 192, and 256 bits to encipher
and decipher information (data) into symmetric blocks of 128 bits.
As mentioned above, the size of the key for an AES code mentions the repetitions numbers of
alteration series that change the given input (plaintext) to the absolute output (cipher text)are as
follows: repetition in 10 cycles for 128-bit keys, repetition in 12 cycles for 192-bit keys,
repetition in 14 cycles for 256-bit keys.
The procedure for AES is described as follows. Every step contains many processing cycles.
Every cycle contains four or at most four alike but altered states, counting the one which hangs
on the encryption key. A group of converse rounds are employed to convert the cipher text back
into the unique plaintext with the original encryption key. These stages include Key Expansions,
Initial Round (Add Round Key), Rounds (Sub Bytes, Shift Rows, Mix Columns, and Add Round
Key), Final Round (Sub Bytes, Shift Rows, and Add Round Key).
Add Round Key – the stage in which every byte of the state is exlcusive-or’ed with a block of
the round key using bitwise exor. Sub Bytes – this stage is a non-linear substitution in which
every byte is substituted with another byte with the help of a lookup table. Shift Row – this stage
is where a reversal step in which the final three rows of the state are moved intermittently in a
definite number of steps. Mix Column – this stage is where integration process that functions on
the columns of the state, joining the four bytes in every column.
Cipher
The process of Ciphering is described as follows. Initially, the input is replicated to the state
array. After the Add Round Key, the state array is altered by applying a round function 10, 12, or
14 times, varying on the considered key length, with the last round varying somewhat from the
initial Nr -1 rounds. The last state is then replicated to the output. The round function is limited
using a key schedule that contains a 1-D array of four byte words resulted by the use of Key
Expansion. The Cipher is shown in the following code. The single alterations, that are
6. EE260 Final Project P a g e | 6 Spring 2015
SubBytes(), ShiftRows(), MixColumns(), and AddRoundKey() functions, process the given
State. The array described below w[ ] comprises of the key schedule. All Nr rounds are alike
with the exclusion of the last and final round, which does not contain the MixColumns()
transformation function.
Figure 2: The Pseudo Code for Cipher
Authenticated Lightweight Encryption (ALE)
A lightweight cryptography technique based on Advance Encryption Standard (AES) known as
Authenticated Lightweight Encryption (ALE) which is proficient in both hardware and software
implementations. The basic functioning of ALE is the AES round transformation with the
implementation of 128-bit key AES schedule. ALE is a single pass algorithm with authenticated
encryption. The operation is to accept a128 key K, a message m, associated data α and a 128
nonce ν, that is not equal to zero. A corresponding of at the most of 248 bits is permissible to be
authentication or sometimes simultaneously authentication and encryption with the help of
similar 128-bit master key. The process of either encryption or authentication yields the cipher
text γ of accurately the exact length as the message m and the verification tag τ of the length of
128 bits for the message m as well as the associated data α. The process of either decryption or
verification procedure consents the five important components, which are key K, cipher text γ,
associated data α, nonce ν and verification tag τ. Once the procedure is successful, it outputs the
decrypted message m if tag is correct. The encryption is performed in five steps that are Padding,
Initialization, Processing associated data, Processing message, Finalization.
7. EE260 Final Project P a g e | 7 Spring 2015
Ultra-Light Weight Block Cipher – PRESENT
PRESENT is an ultra-light weight block cipher algorithm developed university of Denmark in
2007. It is prominent for its compact size. When compared to AES, it is 2.5 times smaller. The
specifications of the PRESENT are the block size that is 64 bits in length and the key size can
either be 80 bit or 128 bit in size. It is example of a substitution-permutation network. It has a
non-linear layer which is based on a single 4-bit S-box that was aimed for hardware
simplification. The design was projected for low power and high efficiency results and was
achieved. Security is passable for applications that run on low-security requirement in tag-
centered utilizations.
Figure 3: Pseudo code for cipher with top level algorithm
The functioning of the PRESENT Algorithm is described as follows. It involves of 31 cycles.
Every cycle of the 31 cycles involves of an exclusive-or function to bring together a round key
Ki in the range 1 ≤ i ≤ 32. The key K32 is used for post whitening operation. Post whitening
operation comprises of a linear bitwise permutation and a nonlinear substitution layer. The non-
linear layer uses a single 4-bit S-box S which is applied 16 times in parallel in each round. The
cipher code is described in pseudo-code in figure above. The design is based in such a way that
the bits are numbered from zero and the bit zero is placed to the right most corner of the block
and the numbering goes by.
The above pseudo code comprises of the following functions. addRoundKey. The block size is of
64 bits in length with 31 rounds. Given round key Ki = Ki63 to Ki0 0 for 1 ≤ i ≤ 32 and existent
state b63 to b0, addRoundKey contains the operation for 0 ≤ j ≤ 63, bj → bj ⊕ K i j , performing
an exclusive-or operation.
sBoxlayer. The S-box employed in PRESENT is a 4 bit to 4 bit S-box. The action of this box in
hexadecimal representation is shown below.
8. EE260 Final Project P a g e | 8 Spring 2015
CONCLUSION
As NFC and RFID tags grow strength in popularity, the security threats within the tags continues
to grow. These contact less tags are used in an expanding markets related to defense,
entertainment, manufacturing, and retail. Security is a big topic within all of these areas.
The issue with implementing security within these tags is the amount of limited resources
available within them. Typically a tag will have between 1,000 to 10,000 gates while only ~20%
are reserved for security purposes. Simplification of Hardware is to be observed in order to
extend the security.
We decided to implement the DES, AES, PRESENT algorithms and see how we can begin to
make it lightweight – use fewer resources. DES was chosen because of the ease and efficiency of
implementing it within hardware. The DES flow was described and we found a few areas where
the process could be improved by reducing the wires and resources required to implement it.
AES implementation was chosen as it uses 2400 GE and is observed to do well, in terms of
speed, in both software and hardware. It is employed as a point of reference for upcoming
ciphers. Performance factors include high speed and low RAM, which benefits the overall
design. This helps in AES performance on a wide range of hardware.
PRESENT is an example of stream or state ciphers. It was considered as it is applied for ultra-
lightweight cryptography method. It is few of the primary ciphers that proposed a low level gate
count for constrained devices, which wasn’t the instance with AES. The ultra-light weight design
presents a scene of security with qualifications of a 64-bit block size and an 80-bit key.
Comparison table for Lightweight Cryptography Implementations
Algorithm Number of
Gates
Block
size
Key size Implementation Network Security
DESL
1,850 GE 64 bits 56 bits
(8 bits of
parity)
Fast on HW, Slow on
SW
Balanced Feistel
network
Low
Security
AES
2500 GE 128 bits 128, 192 or
256 bits
Fast on both HW and
SW
Substitution
Permutation
Network
Average to
Mid High
Security
PRESENT
1000 – 1500
GE
64 bits 80 or128
bits
Fast on HW Substitution
Permutation
Network
Adequate
Security
Table 2: Comparison table
9. EE260 Final Project P a g e | 9 Spring 2015
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