Cryptanalysis of block ciphers involves massive computations which are independent of each other and can
be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low
cost Field Programmable Gate Arrays (FPGA’s), building special purpose hardware for computationally
intensive applications has now become possible. For this the Data Encryption Standard (DES) is used as a
proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on
FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared
and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this
work is to make cryptanalysis faster and better.
With increasing technology development in field of communication and Electronic devices, there is a need for better security service for information transfer in Medical Sectors, Banking, Financial and in other IoT applications etc. Fight against security attacks is of prime importance. Through Cryptographic techniques we can provide Authenticity as well as Confidentiality for the user data. In this paper, hardware implementation has been described for a real-time application of speech data encryption and decryption using AES algorithm along with the speech recognition using cross correlation technique. Verilog programming environment is used for AES cryptography whereas MATLAB is used for Speech recognition. ASIC design on AES core is implemented using Cadence tools. Number of gates, area and power used by AES core design has been drastically reduced by specifying wide range of constraints during front end designing. In Backend designing, layout of AES design, which is the physical geometric representation is also developed.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
NEW ALGORITHM FOR WIRELESS NETWORK COMMUNICATION SECURITYijcisjournal
This paper evaluates the security of wireless communication network based on the fuzzy logic in Mat lab. A new algorithm is proposed and evaluated which is the hybrid algorithm. We highlight the valuable assets in designing of wireless network communication system based on network simulator (NS2), which is crucial to protect security of the systems. Block cipher algorithms are evaluated by using fuzzy logics and a hybrid
algorithm is proposed. Both algorithms are evaluated in term of the security level. Logic (AND) is used in the rules of modelling and Mamdani Style is used for the evaluations
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
New Technique Using Multiple Symmetric keys for Multilevel EncryptionIJERA Editor
In a world of accelerating communications, cryptography has become an essential component of the modern
means of communication systems. The emergence of the webas a reliable medium for commerce and
communication has made cryptography an essential component. Many algorithms or ciphers are in use
nowadays. The quality of the cipher is judged byits ability to prevent an unrelated party fromknowingthe
original content of the encrypted message. The proposed “Multilevel Encryption Model” is a cryptosystem that
adopts the basic principles of cryptography. It uses five symmetric keys (multiple)
in floating point numbers, plaintext, substitution techniques and key combinations with unintelligible
sequence to produce the ciphertext. The decryption process is also designed to reproduce the plaintext
With increasing technology development in field of communication and Electronic devices, there is a need for better security service for information transfer in Medical Sectors, Banking, Financial and in other IoT applications etc. Fight against security attacks is of prime importance. Through Cryptographic techniques we can provide Authenticity as well as Confidentiality for the user data. In this paper, hardware implementation has been described for a real-time application of speech data encryption and decryption using AES algorithm along with the speech recognition using cross correlation technique. Verilog programming environment is used for AES cryptography whereas MATLAB is used for Speech recognition. ASIC design on AES core is implemented using Cadence tools. Number of gates, area and power used by AES core design has been drastically reduced by specifying wide range of constraints during front end designing. In Backend designing, layout of AES design, which is the physical geometric representation is also developed.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
NEW ALGORITHM FOR WIRELESS NETWORK COMMUNICATION SECURITYijcisjournal
This paper evaluates the security of wireless communication network based on the fuzzy logic in Mat lab. A new algorithm is proposed and evaluated which is the hybrid algorithm. We highlight the valuable assets in designing of wireless network communication system based on network simulator (NS2), which is crucial to protect security of the systems. Block cipher algorithms are evaluated by using fuzzy logics and a hybrid
algorithm is proposed. Both algorithms are evaluated in term of the security level. Logic (AND) is used in the rules of modelling and Mamdani Style is used for the evaluations
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
New Technique Using Multiple Symmetric keys for Multilevel EncryptionIJERA Editor
In a world of accelerating communications, cryptography has become an essential component of the modern
means of communication systems. The emergence of the webas a reliable medium for commerce and
communication has made cryptography an essential component. Many algorithms or ciphers are in use
nowadays. The quality of the cipher is judged byits ability to prevent an unrelated party fromknowingthe
original content of the encrypted message. The proposed “Multilevel Encryption Model” is a cryptosystem that
adopts the basic principles of cryptography. It uses five symmetric keys (multiple)
in floating point numbers, plaintext, substitution techniques and key combinations with unintelligible
sequence to produce the ciphertext. The decryption process is also designed to reproduce the plaintext
Proposed Lightweight Block Cipher Algorithm for Securing Internet of ThingsSeddiq Q. Abd Al-Rahman
The presentation of paper is published in The 3rd International Conference on Computing, Communications, and Information Technology 24-25 April 2019, Organized by College of Computer Science and IT, University of Anbar, Ramadi, Iraq
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithmijsrd.com
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S -box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
PREDOMINANCE OF BLOWFISH OVER TRIPLE DATA ENCRYPTION STANDARD SYMMETRIC KEY A...IJNSA Journal
Computer data communication is the order of the day with Information Communication Technology (ICT) playing major role in everyone’s life, communicating with smart phones, tabs, laptops and desktops using internet. Security of the data transferred over the computer networks is most important as for as an organization is concerned. Hackers attempt hard to crack the software key and indulge in cyber crimes. In this paper, the main concern is not only to provide security to the data transferred at the software level but it provides the security at hardware level by the modified Blowfish Encryption and Decryption Algorithms. It results minimum delay, high speed, high throughput] and effective memory utilization compared to Blowfish (BF) and Triple Data Encryption Standard (TDES) algorithms. The implementation of Blowfish with modulo adder and Wave Dynamic Differential Logic (WDDL) is to provide security against Differential power analysis (DPA). In the proposed four implementations, BF with constant delay n-bit adder (BFCDNBA) yielded minimum delay, maximum frequency, high memory utilization and high throughput compared to BF with modulo adder and WDDL logic (BFMAWDDL), BF with modulo adder (BFMA) and TDES algorithms. The VLSI implementation of Blowfish and TDES algorithms is done using Verilog HDL.
Wireless Network Security Architecture with Blowfish Encryption ModelIOSR Journals
Abstract: In this research paper ,we developed a model for a large network, wireless nodes are interconnected and each can be considered as a node processor that offer services to other node processors connected to a specific network. A very high proportion of the nodes that offer services need to carry out an authentication process so as to make an access request to the node offering the service. In this context, an integrated reconfigurable network security architecture moved to the application layer has become the need of the day for secure wireless data sharing. The security schemes of the seven layer OSI architecture need to be placed intrinsically in the wireless node itself and should be capable of supporting the MAC layer, IP address based layer and the routing protocols of the network layer. This work focuses on the use of emulator and embedded hardware architectures for wireless network security. In this work, the individual nodes can have a unique security signature pattern maintained by respective wireless nodes using an encryption algorithm and this is made dynamic. The metrics includes latency, throughput, Scalability, Effects of data transfer operation on node processor and application data located in the processor Keywords:Wireless Network security, Embedded hardware, Reconfigurable architecture, blowfish algorithm
Simulated Analysis and Enhancement of Blowfish Algorithmiosrjce
This paper represents or analyzes the security of system based on Blowfish. Blowfish mainly focuses
on the encrypt and decrypt techniques and algorithms apply for cryptanalysis. It describe the algorithms for
encryption as well as decryption algorithms and also give the sufficient description of key generation, key
expansion, function and working principle of Blowfish cipher with proper explanations. Taking the current era,
Most of the famous systems which offer security for a network or web or to a data are vulnerability to attacks and
they are broken at some point of time by effective cryptanalysis methods, irrespective of its complex algorithmic
design. In the general, today’s cryptography world is bounded to an interpretive of following any one or multi
encryption scheme and that too for a single iteration on a single file only. This is evident in the maximum of the
encryption-decryption cases. It also describes the comparisons between older blowfish and enhances blowfish. It
also shows enhance Blowfish algorithm for encryption and decryption of data. It is also give the proper simulated
analysis of encryption and decryption time for different file formats using a windows application. It describe
feature of application and its process and efficiency as well as calculation of time and throughput.
COMPARATIVE ANALYSIS OF DIFFERENT ENCRYPTION TECHNIQUES IN MOBILE AD HOC NETW...IJCNCJournal
In this paper a detailed analysis of Data Encryption Standard (DES), Triple DES (3DES) and Advanced
Encryption Standard (AES) symmetric encryption algorithms in MANET was done using the Network
Simulator 2 (NS-2) in terms of energy consumption, data transfer time, End-to-End delay time and
throughput with varying data sizes. Two simulation models were adopted: the first simulates the network
performance assuming the availability of the common key, and the second simulates the network
performance including the use of the Diffie-Hellman Key Exchange (DHKE) protocol in the key
management phase. The obtained simulation results showed the superiority of AES over DES by 65%, 70%
and 83% in term of the energy consumption, data transfer time, and network throughput respectively. On
the other hand, the results showed that AES is better than 3DES by approximately 90% for all of the
performance metrics. Based on these results the AES was the recommended encryption scheme.
AES and DES are two different crypto algorithms having different features. This projects consists of integrating these algorithms to develop a new structure. Here, read and write of text files is employed. Thus, the text files listed should exist in the same folder as the project is in. Implementation is carried in VHDL on Modelsim.
DARE Algorithm: A New Security Protocol by Integration of Different Cryptogra...IJECEIAES
Exchange of information between computer networks requires a secure communications channel to prevent and monitor unauthorized access, modification and denial of the computer network. To address this growing problem, security experts sought ways to advance the integrity of data transmission. Security Attacks compromises the security and hence hybrid cryptographic algorithms have been proposed to achieve safe service in the proper manner, such as user authentication and data confidentiality. Data security and authenticity are achieved using these algorithms. Moreover, to improve the strength and cover each algorithm’s weaknesses, a new security algorithm can be designed using the combination of different cryptographic techniques. This design uses Digital Signature Algorithm (DSA) for authentic key generation, Data Encryption Standard (DES) for key scheduling, and Advanced Encryption Standard (AES) and Rivest–Schamir– Adleman Algorithm (RSA) in encrypting data. This new security algorithm has been proposed for improved security and integrity by integration of these cryptographic techniques.
A Technique by using Neuro-Fuzzy Inference System for Intrusion Detection and...IJMER
—This paper proposes a technique uses decision tree for dataset and to find the basic
parameters for creating the membership functions of fuzzy inference system for Intrusion Detection and
Forensics. Approach of generating rules using clustering methods is limited to the problems of
clustering techniques. To trait to solve this problem, several solutions have been proposed using
various Techniques. One such Technique is proposed to be applied here, for an analysis to Intrusion
Detection and Forensics. . Fuzzy Inference approach and decision algorithms are investigated in this
work. Decision tree is used to identify the parameters to create the fuzzy inference system. Fuzzy
inference system used as an input and the final ANFIS structure is generated for intrusion detection
and forensics. The experiments and evaluations of the proposed method were done with NSL-KDD
intrusion detection dataset.
Ciphering algorithms play a main role in information security systems. Therefore in this paper we are
considering the important performance of these algorithms like CPU time consumption, memory usage and
battery usage. This research tries to demonstrate a fair comparison between the most common algorithms
and with a novel method called Secured Watermark System (SWS) in data encryption field according to
CPU time, packet size and power consumption. It provides a comparison the most known algorithms used
in encryption: AES (Rijndael), DES, Blowfish, and Secured Watermark System (SWS).
For comparing these algorithms with each other variations of data block sizes, and a variation of
encryption-decryption speeds where used in this research.
In addition a comparison with different platforms such as Windows 8, Windows XP and Linux has been
conducted. Finally the results of the experimentation demonstrate the performance and efficiency of the
compared encryption algorithms with different parameters.
survey paper on object oriented cryptographic security for runtime entitiesINFOGAIN PUBLICATION
With the advent of complex systems the need for large data storage with less space utility & high performance have become the vital features. Another important concern of the data is the security which is assured via the cryptographic techniques implemented at all levels of data storage. In this survey paper we introduce the concept of security between two hierarchical data accesses and propose the concept of hierarchical cryptography between data of different classes of different hierarchies.
PERFORMANCE EVALUATION OF PARALLEL INTERNATIONAL DATA ENCRYPTION ALGORITHM ON...IJNSA Journal
Distributed security is an evolving sub-domain of information and network security. Security applications play a serious role when data exchanging, different volumes of data should be transferred from one site to another safely and at high speed. In this paper, the parallel International Data Encryption Algorithm (IDEA) which is one of the security applications is implemented and evaluated in terms of running time, speedup, and efficiency. The parallel IDEA has been implemented using message passing interface (MPI) library, and the results have been conducted using IMAN1 Supercomputer, where a set of simulation runs carried out on different data sizes to define the best number of processor which can be used to manipulate these data sizes and to build a visualization about the processor number that can be used while the size of data increased. The experimental results show a good performance by reducing the running time, and increasing speed up of encryption and decryption processes for parallel IDEA when the number of processors ranges from 2 to 8 with achieved efficiency 97% to 83% respectively.
A Novel Structure with Dynamic Operation Mode for Symmetric-Key Block CiphersIJNSA Journal
Modern Internet protocols support several modes of operation in encryption tasks for data confidentiality
to keep up with varied environments and provide the various choices, such as multi-mode IPSec support.
To begin with we will provide a brief background on the modes of operation for symmetric-key block
ciphers. Different block cipher modes of operation have distinct characteristics. For example, the cipher
block chaining (CBC) mode is suitable for operating environments that require self-synchronizing
capabilities, and the output feedback (OFB) mode requires encryption modules only. When using
symmetric-key block cipher algorithms such as the Advanced Encryption Standard (AES), users
performing information encryption often encounter difficulties selecting a suitable mode of operation.
This paper describes a structure for analyzing the block operation mode combination. This unified
operation structure (UOS) combines existing common and popular block modes of operation. UOS does
multi-mode of operation with most existing popular symmetric-key block ciphers and do not only consist
of encryption mode such as electronic codebook (ECB) mode, cipher block chaining (CBC) mode, cipher
feedback (CFB) mode and output feedback (OFB) mode, that provides confidentiality but also message
authentication mode such as the cipher block chaining message authentication code (CBC-MAC) in
cryptography. In Cloud Computing, information exchange frequently via the Internet and on-demand.
This research provides an overview and information useful for approaching low-resource hardware
implementation, which is proper to ubiquitous computing devices such as a sensor mote or an RFID tag.
The use of the method is discussed and an example is given. This provides a common solution for multimode and this is very suitable for ubiquitous computing with several resources and environments. This
study indicates a more effectively organized structure for symmetric-key block ciphers to improve their
application scenarios. We can get that it is flexible in modern communication applications.
An efficient algorithm for sequence generation in data miningijcisjournal
Data mining is the method or the activity of analyzing data from different perspectives and summarizing it
into useful information. There are several major data mining techniques that have been developed and are
used in the data mining projects which include association, classification, clustering, sequential patterns,
prediction and decision tree. Among different tasks in data mining, sequential pattern mining is one of the
most important tasks. Sequential pattern mining involves the mining of the subsequences that appear
frequently in a set of sequences. It has a variety of applications in several domains such as the analysis of
customer purchase patterns, protein sequence analysis, DNA analysis, gene sequence analysis, web access
patterns, seismologic data and weather observations. Various models and algorithms have been developed
for the efficient mining of sequential patterns in large amount of data. This research paper analyzes the
efficiency of three sequence generation algorithms namely GSP, SPADE and PrefixSpan on a retail dataset
by applying various performance factors. From the experimental results, it is observed that the PrefixSpan
algorithm is more efficient than other two algorithms.
Proposed Lightweight Block Cipher Algorithm for Securing Internet of ThingsSeddiq Q. Abd Al-Rahman
The presentation of paper is published in The 3rd International Conference on Computing, Communications, and Information Technology 24-25 April 2019, Organized by College of Computer Science and IT, University of Anbar, Ramadi, Iraq
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithmijsrd.com
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S -box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
PREDOMINANCE OF BLOWFISH OVER TRIPLE DATA ENCRYPTION STANDARD SYMMETRIC KEY A...IJNSA Journal
Computer data communication is the order of the day with Information Communication Technology (ICT) playing major role in everyone’s life, communicating with smart phones, tabs, laptops and desktops using internet. Security of the data transferred over the computer networks is most important as for as an organization is concerned. Hackers attempt hard to crack the software key and indulge in cyber crimes. In this paper, the main concern is not only to provide security to the data transferred at the software level but it provides the security at hardware level by the modified Blowfish Encryption and Decryption Algorithms. It results minimum delay, high speed, high throughput] and effective memory utilization compared to Blowfish (BF) and Triple Data Encryption Standard (TDES) algorithms. The implementation of Blowfish with modulo adder and Wave Dynamic Differential Logic (WDDL) is to provide security against Differential power analysis (DPA). In the proposed four implementations, BF with constant delay n-bit adder (BFCDNBA) yielded minimum delay, maximum frequency, high memory utilization and high throughput compared to BF with modulo adder and WDDL logic (BFMAWDDL), BF with modulo adder (BFMA) and TDES algorithms. The VLSI implementation of Blowfish and TDES algorithms is done using Verilog HDL.
Wireless Network Security Architecture with Blowfish Encryption ModelIOSR Journals
Abstract: In this research paper ,we developed a model for a large network, wireless nodes are interconnected and each can be considered as a node processor that offer services to other node processors connected to a specific network. A very high proportion of the nodes that offer services need to carry out an authentication process so as to make an access request to the node offering the service. In this context, an integrated reconfigurable network security architecture moved to the application layer has become the need of the day for secure wireless data sharing. The security schemes of the seven layer OSI architecture need to be placed intrinsically in the wireless node itself and should be capable of supporting the MAC layer, IP address based layer and the routing protocols of the network layer. This work focuses on the use of emulator and embedded hardware architectures for wireless network security. In this work, the individual nodes can have a unique security signature pattern maintained by respective wireless nodes using an encryption algorithm and this is made dynamic. The metrics includes latency, throughput, Scalability, Effects of data transfer operation on node processor and application data located in the processor Keywords:Wireless Network security, Embedded hardware, Reconfigurable architecture, blowfish algorithm
Simulated Analysis and Enhancement of Blowfish Algorithmiosrjce
This paper represents or analyzes the security of system based on Blowfish. Blowfish mainly focuses
on the encrypt and decrypt techniques and algorithms apply for cryptanalysis. It describe the algorithms for
encryption as well as decryption algorithms and also give the sufficient description of key generation, key
expansion, function and working principle of Blowfish cipher with proper explanations. Taking the current era,
Most of the famous systems which offer security for a network or web or to a data are vulnerability to attacks and
they are broken at some point of time by effective cryptanalysis methods, irrespective of its complex algorithmic
design. In the general, today’s cryptography world is bounded to an interpretive of following any one or multi
encryption scheme and that too for a single iteration on a single file only. This is evident in the maximum of the
encryption-decryption cases. It also describes the comparisons between older blowfish and enhances blowfish. It
also shows enhance Blowfish algorithm for encryption and decryption of data. It is also give the proper simulated
analysis of encryption and decryption time for different file formats using a windows application. It describe
feature of application and its process and efficiency as well as calculation of time and throughput.
COMPARATIVE ANALYSIS OF DIFFERENT ENCRYPTION TECHNIQUES IN MOBILE AD HOC NETW...IJCNCJournal
In this paper a detailed analysis of Data Encryption Standard (DES), Triple DES (3DES) and Advanced
Encryption Standard (AES) symmetric encryption algorithms in MANET was done using the Network
Simulator 2 (NS-2) in terms of energy consumption, data transfer time, End-to-End delay time and
throughput with varying data sizes. Two simulation models were adopted: the first simulates the network
performance assuming the availability of the common key, and the second simulates the network
performance including the use of the Diffie-Hellman Key Exchange (DHKE) protocol in the key
management phase. The obtained simulation results showed the superiority of AES over DES by 65%, 70%
and 83% in term of the energy consumption, data transfer time, and network throughput respectively. On
the other hand, the results showed that AES is better than 3DES by approximately 90% for all of the
performance metrics. Based on these results the AES was the recommended encryption scheme.
AES and DES are two different crypto algorithms having different features. This projects consists of integrating these algorithms to develop a new structure. Here, read and write of text files is employed. Thus, the text files listed should exist in the same folder as the project is in. Implementation is carried in VHDL on Modelsim.
DARE Algorithm: A New Security Protocol by Integration of Different Cryptogra...IJECEIAES
Exchange of information between computer networks requires a secure communications channel to prevent and monitor unauthorized access, modification and denial of the computer network. To address this growing problem, security experts sought ways to advance the integrity of data transmission. Security Attacks compromises the security and hence hybrid cryptographic algorithms have been proposed to achieve safe service in the proper manner, such as user authentication and data confidentiality. Data security and authenticity are achieved using these algorithms. Moreover, to improve the strength and cover each algorithm’s weaknesses, a new security algorithm can be designed using the combination of different cryptographic techniques. This design uses Digital Signature Algorithm (DSA) for authentic key generation, Data Encryption Standard (DES) for key scheduling, and Advanced Encryption Standard (AES) and Rivest–Schamir– Adleman Algorithm (RSA) in encrypting data. This new security algorithm has been proposed for improved security and integrity by integration of these cryptographic techniques.
A Technique by using Neuro-Fuzzy Inference System for Intrusion Detection and...IJMER
—This paper proposes a technique uses decision tree for dataset and to find the basic
parameters for creating the membership functions of fuzzy inference system for Intrusion Detection and
Forensics. Approach of generating rules using clustering methods is limited to the problems of
clustering techniques. To trait to solve this problem, several solutions have been proposed using
various Techniques. One such Technique is proposed to be applied here, for an analysis to Intrusion
Detection and Forensics. . Fuzzy Inference approach and decision algorithms are investigated in this
work. Decision tree is used to identify the parameters to create the fuzzy inference system. Fuzzy
inference system used as an input and the final ANFIS structure is generated for intrusion detection
and forensics. The experiments and evaluations of the proposed method were done with NSL-KDD
intrusion detection dataset.
Ciphering algorithms play a main role in information security systems. Therefore in this paper we are
considering the important performance of these algorithms like CPU time consumption, memory usage and
battery usage. This research tries to demonstrate a fair comparison between the most common algorithms
and with a novel method called Secured Watermark System (SWS) in data encryption field according to
CPU time, packet size and power consumption. It provides a comparison the most known algorithms used
in encryption: AES (Rijndael), DES, Blowfish, and Secured Watermark System (SWS).
For comparing these algorithms with each other variations of data block sizes, and a variation of
encryption-decryption speeds where used in this research.
In addition a comparison with different platforms such as Windows 8, Windows XP and Linux has been
conducted. Finally the results of the experimentation demonstrate the performance and efficiency of the
compared encryption algorithms with different parameters.
survey paper on object oriented cryptographic security for runtime entitiesINFOGAIN PUBLICATION
With the advent of complex systems the need for large data storage with less space utility & high performance have become the vital features. Another important concern of the data is the security which is assured via the cryptographic techniques implemented at all levels of data storage. In this survey paper we introduce the concept of security between two hierarchical data accesses and propose the concept of hierarchical cryptography between data of different classes of different hierarchies.
PERFORMANCE EVALUATION OF PARALLEL INTERNATIONAL DATA ENCRYPTION ALGORITHM ON...IJNSA Journal
Distributed security is an evolving sub-domain of information and network security. Security applications play a serious role when data exchanging, different volumes of data should be transferred from one site to another safely and at high speed. In this paper, the parallel International Data Encryption Algorithm (IDEA) which is one of the security applications is implemented and evaluated in terms of running time, speedup, and efficiency. The parallel IDEA has been implemented using message passing interface (MPI) library, and the results have been conducted using IMAN1 Supercomputer, where a set of simulation runs carried out on different data sizes to define the best number of processor which can be used to manipulate these data sizes and to build a visualization about the processor number that can be used while the size of data increased. The experimental results show a good performance by reducing the running time, and increasing speed up of encryption and decryption processes for parallel IDEA when the number of processors ranges from 2 to 8 with achieved efficiency 97% to 83% respectively.
A Novel Structure with Dynamic Operation Mode for Symmetric-Key Block CiphersIJNSA Journal
Modern Internet protocols support several modes of operation in encryption tasks for data confidentiality
to keep up with varied environments and provide the various choices, such as multi-mode IPSec support.
To begin with we will provide a brief background on the modes of operation for symmetric-key block
ciphers. Different block cipher modes of operation have distinct characteristics. For example, the cipher
block chaining (CBC) mode is suitable for operating environments that require self-synchronizing
capabilities, and the output feedback (OFB) mode requires encryption modules only. When using
symmetric-key block cipher algorithms such as the Advanced Encryption Standard (AES), users
performing information encryption often encounter difficulties selecting a suitable mode of operation.
This paper describes a structure for analyzing the block operation mode combination. This unified
operation structure (UOS) combines existing common and popular block modes of operation. UOS does
multi-mode of operation with most existing popular symmetric-key block ciphers and do not only consist
of encryption mode such as electronic codebook (ECB) mode, cipher block chaining (CBC) mode, cipher
feedback (CFB) mode and output feedback (OFB) mode, that provides confidentiality but also message
authentication mode such as the cipher block chaining message authentication code (CBC-MAC) in
cryptography. In Cloud Computing, information exchange frequently via the Internet and on-demand.
This research provides an overview and information useful for approaching low-resource hardware
implementation, which is proper to ubiquitous computing devices such as a sensor mote or an RFID tag.
The use of the method is discussed and an example is given. This provides a common solution for multimode and this is very suitable for ubiquitous computing with several resources and environments. This
study indicates a more effectively organized structure for symmetric-key block ciphers to improve their
application scenarios. We can get that it is flexible in modern communication applications.
An efficient algorithm for sequence generation in data miningijcisjournal
Data mining is the method or the activity of analyzing data from different perspectives and summarizing it
into useful information. There are several major data mining techniques that have been developed and are
used in the data mining projects which include association, classification, clustering, sequential patterns,
prediction and decision tree. Among different tasks in data mining, sequential pattern mining is one of the
most important tasks. Sequential pattern mining involves the mining of the subsequences that appear
frequently in a set of sequences. It has a variety of applications in several domains such as the analysis of
customer purchase patterns, protein sequence analysis, DNA analysis, gene sequence analysis, web access
patterns, seismologic data and weather observations. Various models and algorithms have been developed
for the efficient mining of sequential patterns in large amount of data. This research paper analyzes the
efficiency of three sequence generation algorithms namely GSP, SPADE and PrefixSpan on a retail dataset
by applying various performance factors. From the experimental results, it is observed that the PrefixSpan
algorithm is more efficient than other two algorithms.
A 130-NM CMOS 400 MHZ 8-Bit Low Power Binary Weighted Current Steering DAC ijcisjournal
A low power low voltage 8-bit Digital to Analog Converter consisting of different current sources in binary
weighted array architecture is designed. The weights of current sources are depending on the binary
weights of the bits. This current steering DAC is suitable for high speed applications. The proposed DAC in
this paper has DNL, INL of ±0.04, ±0.05 respectively and the power consumption of 16.67mw.
This binary array architecture is implemented in CMOS 0.13µm 1P2M technology has good performances
in DNL, INL and area compared with other researches.
Wavelet Based on the Finding of Hard and Soft Faults in Analog and Digital Si...ijcisjournal
In this paper methods for testing both software and hardware faults are implemented in analog and digital
signal circuits are presented. They are based on the wavelet transform (WT). The limit which affected by
faults detect ability, for the reference circuits is set by statistical processing data obtained from a set of
faults free circuits .In wavelet analysis it has two algorithm one is based on a discrimination factor using
Euclidean distances and the other mahalanobis distances, are introduced both methods on wavelet energy
calculation. Simulation result from proposed test methods in the testing known analog and digital signal
circuit benchmark are given. The results shows that effectiveness of existing methods two test metrics
against three other test methods, namely a test method based on rms value of the measured signal, a test
method utilizing the harmonic magnitude component of the measured signal waveform
Blind Image Quality Assessment with Local Contrast Features ijcisjournal
The aim of this research is to create a tool to evaluate distortion in images without the information about
original image. Work is to extract the statistical information of the edges and boundaries in the image and
to study the correlation between the extracted features. Change in the structural information like shape and
amount of edges of the image derives quality prediction of the image. Local contrast features are effectively
detected from the responses of Gradient Magnitude (G) and Laplacian of Gaussian (L) operations. Using
the joint adaptive normalisation, G and L are normalised. Normalised values are quantized into M and N
levels respectively. For these quantised M levels of G and N levels of L, Probability (P) and conditional
probability(C) are calculated. Four sets of values namely marginal distributions of gradient magnitude Pg,
marginal distributions of Laplacian of Gaussian Pl, conditional probability of gradient magnitude Cg and
probability of Laplacian of Gaussian Cl are formed. These four segments or models are Pg, Pl, Cg and Cl.
The assumption is that the dependencies between features of gradient magnitude and Laplacian of
Gaussian can formulate the level of distortion in the image. To find out them, Spearman and Pearson
correlations between Pg, Pl and Cg, Cl are calculated. Four different correlation values of each image are
the area of interest. Results are also compared with classical tool Structural Similarity Index Measure
DWT Based Audio Watermarking Schemes : A Comparative Study ijcisjournal
The main problem encountered during multimedia transmission is its protection against illegal distribution
and copying. One of the possible solutions for this is digital watermarking. Digital audio watermarking is
the technique of embedding watermark content to the audio signal to protect the owner copyrights. In this
paper, we used three wavelet transforms i.e. Discrete Wavelet Transform (DWT), Double Density DWT
(DDDWT) and Dual Tree DWT (DTDWT) for audio watermarking and the performance analysis of each
transform is presented. The key idea of the basic algorithm is to segment the audio signal into two parts,
one is for synchronization code insertion and other one is for watermark embedding. Initially, binary
watermark image is scrambled using chaotic technique to provide secrecy. By using QuantizationIndex
Modulation (QIM), this method works as a blind technique. The comparative analysis of the three methods
is made by conducting robustness and imperceptibility tests are conducted on five benchmark audio
signals.
SECURITY ANALYSIS OF THE MULTI-PHOTON THREE-STAGE QUANTUM KEY DISTRIBUTIONijcisjournal
This paper presents a multi-stage, multi-photon quantum key distribution protocol based on the double-lock
cryptography. It exploits the asymmetry in the detection strategies between the legitimate users and the
eavesdropper. The security analysis of the protocol is presented with coherent states under the interceptresend
attack, the photon number splitting attack, and the man-in-the-middle attack. It is found that the mean photon number can be much larger 1. This complements the recent interest in multi-photon quantum communication protocols that require a pre-shared key between the legitimate users.
High Capacity Image Steganography Using Adjunctive Numerical Representations ...ijcisjournal
LSB steganography is a one of the most widely used methods for implementing covert data channels in
image file exchanges [1][2]. The low computational complexity and implementation simplicity of the algorithm are significant factors for its popularity with the primary reason being low image distortion. Many attempts have been made to increase the embedding capacity of LSB algorithms by expanding into the second or third binary layers of the image while maintaining a low probability of detection with minimal distortive effects [2][3][4]. In this paper,we introduce an advanced technique for covertly embedding data within images using redundant number system decomposition over non -standard digital bit planes. Both grayscale and bit-mapped images are equally effective as cover files. It will be shown that this unique steganography method has minimal visual distortive affects while also preserving the cover file statistics, making it less susceptible to most general steganography detection algorithms.
Performance Analsis of Clipping Technique for Papr Reduction of MB-OFDM UWB S...ijcisjournal
Multiband Orthogonal Frequency Division Multiplexing (MB-OFDM) is used as efficacious procedure for
ultra-wideband (UWB) wireless communication applications, which divides the spectrum into various subbands,
whose bandwidth is approximately 500MHz. Major arduousness in multiband-OFDM is ,it have
very large peak to average power ratio value which causes the signal to enter into dynamic region that
consequence in the loss of orthogonal properties and results in the interference of the carrier signals which
crops the amplifier saturation and finally limits the capacity of the system. Many PAPR amortize
algorithms have reported in the survey and pre-coding is PAPR reduction which is inserted after
modulation in the OFDM system. The Existing work presents the reduction of that value by different
clipping techniques namely Classical-Clipping (CC), Heavy side-Clipping (HC), Deep-Clipping (DC) and
Smooth-Clipping (SC) and their comparison analysis is done. Every clipping method is best at its own
level .The proficiency of these strategies are evaluated in locutions of average power disparity, complete
system decadence and PAPR reduction. Finally results show the MB OFDM yields better performance to
reduce PAPR in effective way.
Cryptography is an art and science of secure communication. Here the sender and receiver are guaranteed
the security through encryption of their data, with the help of a common key. Both the parties should agree
on this key prior to communication. The cryptographic systems which perform these tasks are designed to
keep the key secret while assuming that the algorithm used for encryption and decryption is public. Thus
key exchange is a very sensitive issue. In modern cryptographic algorithms this security is based on the
mathematical complexity of the algorithm. But quantum computation is expected to revolutionize computing
paradigm in near future. This presents a challenge amongst the researchers to develop new cryptographic
techniques that can survive the quantum computing era. This paper reviews the radical use of quantum
mechanics for cryptography
Copy Move Forgery Detection Using GLCM Based Statistical Features ijcisjournal
The features Gray Level Co-occurrence Matrix (GLCM) are mostly explored in Face Recognition and
CBIR. GLCM technique is explored here for Copy-Move Forgery Detection. GLCMs are extracted from all
the images in the database and statistics such as contrast, correlation, homogeneity and energy are
derived. These statistics form the feature vector. Support Vector Machine (SVM) is trained on all these
features and the authenticity of the image is decided by SVM classifier. The proposed work is evaluated on
CoMoFoD database, on a whole 1200 forged and processed images are tested. The performance analysis
of the present work is evaluated with the recent methods.
General Kalman Filter & Speech Enhancement for Speaker Identificationijcisjournal
Presence of noise increases the dimension of the information. A noise suppression algorithm is developed
with an idea of combining the General Kalman Filter and Estimate Maximization (EM) frame work.This
combination is helpful and effective in identifying noise characteristics of an acoustic environment.
Recursion between Estimate step and Maximization step enabled the algorithm to deal any model of noise.
The same Speech enhancement procedure in applied in the pre-processing stage of a conventional Speaker
identification method. Due to the non-stationary nature of noise and speech adaptive algorithms are
required. Algorithm is first applied for Speech enhancement problem and then extended to using it in the
pre-processing step of the Speaker identification. The present work is compared in terms of significant
metrics with existing and popular algorithms and results show that the developed algorithm is dominant
over them.
Gait Based Person Recognition Using Partial Least Squares Selection Scheme ijcisjournal
The variations of viewing angle and intra-class of human beings have great impact on gait recognition
systems. This work represents an Arbitrary View Transformation Model (AVTM) for recognizing the gait.
Gait energy image (GEI) based gait authentication is effective approach to address the above problem, the
method establishes an AVTM based on principle component analysis (PCA). Feature selection (FS) is
performed using Partial least squares (PLS) method. The comparison of the AVTM PLS method with the
existing methods shows significant advantages in terms of observing angle variation, carrying and attire
changes. Experiments evaluated over CASIA gait database, shows that the proposed method improves the
accuracy of recognition compared to the other existing methods.
To the networks rfwkidea32 16, 32-8, 32-4, 32-2 and rfwkidea32-1, based on th...ijcisjournal
In this article, based on a network IDEA32-16, we have developed 5 new networks:RFWKIDEA32-16,RFWKIDEA32-8,
RFWKIDEA32-4, RFWKIDEA32-2, RFWKIDEA32, that do
not use round keys in round functions. It shows that in offered networks such Feistel network,
encryption and decryption using the same algorithm as a round function can be used any
transformation.
An Optimized Approach for Fake Currency Detection Using Discrete Wavelet Tran...ijcisjournal
With the increase of modest technology, copy-move forgery detection has grown in a rapid rate that new
era of forged images came true which has the same resemblance as the old ones i.e. difficult to find out
with naked human perception. Fake currency detection is one in the effect that currency note is tampered in
a way such it has the similar resemblance as the original one. So in order to find out the duplicate or
forged portion of the image we go for different splicing algorithms using different techniques. Image
forgery results to various security issues. Hence an efficient algorithm is required to detect the forgery in
images. By using DCT algorithm blocks of the image are represented by DCT coefficients. Presence of
blocking articrafts in DCT makes the method to be a drawback. Hence we propose DWT for segmentation
of image. Lexicographical sorting is utilized to find out the cloned image blocks. Finally normalization is
applied to find the distance in between similar vectors. In DWT provides better resolution and
segmentation compared with DCT. In this paper, due to DWT, Image Forgery detection is done on lowlevel
image representation. By using DWT better accuracy in finding out the forgery is achieved in a less
time which gradually reduces complexity.
Agile development methods are commonly used to iteratively develop the information systems and they can
easily handle ever-changing business requirements. Scrum is one of the most popular agile software
development frameworks. The popularity is caused by the simplified process framework and its focus on
teamwork. The objective of Scrum is to deliver working software and demonstrate it to the customer faster
and more frequent during the software development project. However the security requirements for the
developing information systems have often a low priority. This requirements prioritization issue results in
the situations where the solution meets all the business requirements but it is vulnerable to potential
security threats.
The major benefit of the Scrum framework is the iterative development approach and the opportunity to
automate penetration tests. Therefore the security vulnerabilities can be discovered and solved more often
which will positively contribute to the overall information system protection against potential hackers.
In this research paper the authors propose how the agile software development framework Scrum can be
enriched by considering the penetration tests and related security requirements during the software
development lifecycle. Authors apply in this paper the knowledge and expertise from their previous work
focused on development of the new information system penetration tests methodology PETA with focus on
using COBIT 4.1 as the framework for management of these tests, and on previous work focused on
tailoring the project management framework PRINCE2 with Scrum.
The outcomes of this paper can be used primarily by the security managers, users, developers and auditors.
The security managers may benefit from the iterative software development approach and penetration tests
automation. The developers and users will better understand the importance of the penetration tests and
they will learn how to effectively embed the tests into the agile development lifecycle. Last but not least the
auditors may use the outcomes of this paper as recommendations for companies struggling with
penetrations testing embedded in the agile software development process.
DEVELOPMENT OF SECURE CLOUD TRANSMISSION PROTOCOL (SCTP) ENGINEERING PHASES :...ijcisjournal
Cloud computing technology provides various internet-based services. Many cloud computing vendors are offering cloud services through their own service mechanism. These mechanisms consist of various service parameters such as authentication, security, performance, availability, etc. Customer can access these cloud services through web browsers using http protocols. Each protocol has its own way of achieving the request-response services, authentication, confidentiality and etc. Cloud computing is an internet-based technology, which provides Infrastructure, Storage, Platform services on demand through a browser using HTTP protocols. These protocol features can be enhanced using cloud specific protocol, which provides strong authentication, confidentiality, security, integrity, availability and accessibility. We are proposing and presenting the secure cloud transmission protocol (SCTP) engineering phases which sits on top of existing http protocols to provide strong authentication security and confidentiality using multi-models. SCTP has multi-level and multi-dimensional approach to achieve strong authentication and multi-level security technique to achieve secure channel. This protocol can add on to existing http protocols. It can be used in any cloud services. This paper presents proposed Protocol engineering phases such as Service Specification, Synthesis, Analysis, Modelling, and Implementation model with test suites. This paper is represents complete integration of our earlier proposed and published multilevel techniques
Fault Detection in Mobile Communication Networks Using Data Mining Techniques...ijcisjournal
A collection of datasets is Big data so that it to be To process huge and complex datasets becomes difficult.
so that using big data analytics the process of applying huge amount of datasets consists of many data
types is the big data on-hand theoretical models and technique tools. The technology of mobile
communication introduced low power ,low price and multi functional devices. A ground for data mining
research is analysis of data pertaining to mobile communication is used. theses mining frequent patterns
and clusters on data streams collaborative filtering and analysis of social network. The data analysis of
mobile communication has been often used as a background application to motivate many technical
problem in data mining research. This paper refers in mobile communication networking to find the fault
nodes between source to destination transmission using data mining techniques and detect the faults using
outliers. outlier detection can be used to find outliers in multivariate data in a simple ensemble way.
Network analysis with R to build a network.
HARDWARE IMPLEMENTATION OF ALGORITHM FOR CRYPTANALYSISijcisjournal
Cryptanalysis of block ciphers involves massive computations which are independent of each other and can be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low cost Field Programmable Gate Arrays (FPGA’s), building special purpose hardware for computationally intensive applications has now become possible. For this the Data Encryption Standard (DES) is used as a proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this work is to make cryptanalysis faster and better.
Implementation of Cryptography Architecture with High Secure CoreIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
A Modified Technique For Performing Data Encryption & Data DecryptionIJERA Editor
In this age of universal electronic connectivity of viruses and hackers of electronic eavesdropping and electronic fraud, there is indeed needed to store the information securely. This, in turn, led to a heightened awareness to protect data and resources from disclosure, to guarantee the authenticity of data and messages and to protect systems from network-based attacks. Information security via encryption decryption techniques is a very popular research area for many people’s over the years. This paper elaborates the basic concept of the cryptography, specially public and private cryptography. It also contains a review of some popular encryption decryption algorithms. A modified method is also proposed. This method is fast in comparison to the existing methods.
Wireless communication systems, multi-input multi-output (MIMO) technology has been recognized as the key ingredient to support higher data rate as well as better transmission quality after using this algorithm of a XTEA or MTEA scheme. Modified TEA is used for encryption of the text. Then decryption unit for decrypting the cipher text and convert that to plain text. Key generation unit is to generate 128bit key and these keys are send along with cipher text. Encryption and decryption system ensures the original data are send and received by the users in secured environment. The Received data are retrieving by the authorized users by providing key generation like private keys this Key Pattern generations provide more security to the messages. Extended tiny encryption algorithm or modified tiny encryption algorithm and tiny encryption algorithm are used to enhance the size, speed and security in the system. These algorithms are better compared to configurable joint detection decoding algorithm (CJDD) and valid symbol finder algorithm.
A Comparative Study of RSA and ECC and Implementation of ECC on Embedded SystemsAM Publications
A large share of embedded applications are wireless, which makes the communication channel especially vulnerable. The research in the field of ECC is mostly focused on its implementation on application specific systems, which have restricted resources like storage, processing speed and domain specific CPU architecture. The focus of this research is on the implementation of ECC in an embedded iOS application to compare the performance measures obtained in the wireless environment or embedded systems by using elliptic curve cryptography (ECC), with a traditional cryptosystem like RSA.
In today’s network-based cloud computing era, software applications are playing big role. The security of these software applications is paramount to the successful use of these applications. These applications utilize cryptographic algorithms to secure the data over the network through encryption and decryption
processes. The use of parallel processors is now common in both mobile and cloud computing scenarios.
Cryptographic algorithms are compute intensive and can significantly benefit from parallelism. This paper
introduces a parallel approach to symmetric stream cipher security algorithm known as RC4A, which is
one of the strong variants of RC4. We present an efficient parallel implementation to the compute intensive
PRGA that is pseudo-random generation algorithm portion of the RC4A algorithm and the resulted
algorithm will be named as PARC4-I. We have added some functionality in terms of lookup tables.
Modified algorithm is having four lookup tables instead of two and is capable of returning four distinct
output bytes at each iteration. Further, with the help of Parallel Additive Stream Cipher Structure and loop
unrolling method, encryption/decryption is being done on multi core machine. Finally, the results shows
that PARC4-I is a time efficient algorithm.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
LOW AREA FPGA IMPLEMENTATION OF DROMCSLA-QTL ARCHITECTURE FOR CRYPTOGRAPHIC A...IJNSA Journal
Nowadays, several techniques are implemented for the cryptosystems to provide security in communication systems. The major issues detected in conventional methods are the weakness against different attack, unacceptable data expansion, and slow performance speed. In this paper, a method Dual-port Read Only Memory-Carry Select Adder-Quantitative Trait Loci (DROM-CSLA-QTL) is introduced, which utilizes lower area than the existing method. The proposed system is implemented using DROM-CSLA, which occupies less area. The DROM-CLSA-QTL algorithm is implemented using tools such as MATLAB and Model Sim. Further for FPGA implementation, Virtex 4, Virtex 5 and Virtex 6 devices are used to determine the number of Lookup Tables (LUTs), slices, flip-flops, area and frequency. Mean, Variance and Covariance are evaluated in the MATLAB.
LOW AREA FPGA IMPLEMENTATION OF DROMCSLA-QTL ARCHITECTURE FOR CRYPTOGRAPHIC A...IJNSA Journal
Nowadays, several techniques are implemented for the cryptosystems to provide security in communication
systems. The major issues detected in conventional methods are the weakness against different attack,
unacceptable data expansion, and slow performance speed. In this paper, a method Dual-port Read Only
Memory-Carry Select Adder-Quantitative Trait Loci (DROM-CSLA-QTL) is introduced, which utilizes
lower area than the existing method. The proposed system is implemented using DROM-CSLA, which
occupies less area. The DROM-CLSA-QTL algorithm is implemented using tools such as MATLAB and
Model Sim. Further for FPGA implementation, Virtex 4, Virtex 5 and Virtex 6 devices are used to
determine the number of Lookup Tables (LUTs), slices, flip-flops, area and frequency. Mean, Variance and
Covariance are evaluated in the MATLAB.
Presently on a daily basis sharing the information over web is becoming a significant issue due to security problems. Thus lots of techniques are needed to protect the shared info in academic degree unsecured channel. The present work target cryptography to secure the data whereas causing inside the network. Encryption has come up as a solution, and plays an awfully necessary role in data security. This security mechanism uses some algorithms to scramble info into unclear text which can be exclusively being decrypted by party those possesses the associated key. This paper is expounded the varied forms of algorithmic rule for encryption & decryption: DES, AES, RSA, and Blowfish. It helps to hunt out the best algorithmic rule.
Design and implementation of proposed 320 bit RC6-cascaded encryption/decrypt...IJECEIAES
This paper attempts to build up a simple, strong and secure cryptographic algorithm. The result of such an attempt is “RC6-Cascade” which is 320-bits RC6 like block cipher. The key can be any length up to 256 bytes. It is a secret-key block cipher with precise characteristics of RC6 algorithm using another overall structure design. In RC6-Cascade, cascading of F-functions will be used instead of rounds. Moreover, the paper investigates a hardware design to efficiently implement the proposed RC6-Cascade block cipher core on field programmable gate array (FPGA). An efficient compact iterative architecture will be designed for the F-function of the above algorithm. The goal is to design a more secure algorithm and present a very fast encryption core for low cost and small size applications.
A PERFORMANCE EVALUATION OF COMMON ENCRYPTION TECHNIQUES WITH SECURE WATERMAR...IJNSA Journal
Ciphering algorithms play a main role in information security systems. Therefore in this paper we are considering the important performance of these algorithms like CPU time consumption, memory usage and battery usage. This research tries to demonstrate a fair comparison between the most common algorithms and with a novel method called Secured Watermark System (SWS) in data encryption field according to CPU time, packet size and power consumption. It provides a comparison the most known algorithms used in encryption: AES (Rijndael), DES, Blowfish, and Secured Watermark System (SWS).
For comparing these algorithms with each other variations of data block sizes, and a variation of encryption-decryption speeds where used in this research.
In addition a comparison with different platforms such as Windows 8, Windows XP and Linux has been conducted. Finally the results of the experimentation demonstrate the performance and efficiency of the compared encryption algorithms with different parameters.
Similar to Hardware Implementation of Algorithm for Cryptanalysis (20)
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
Builder.ai Founder Sachin Dev Duggal's Strategic Approach to Create an Innova...Ramesh Iyer
In today's fast-changing business world, Companies that adapt and embrace new ideas often need help to keep up with the competition. However, fostering a culture of innovation takes much work. It takes vision, leadership and willingness to take risks in the right proportion. Sachin Dev Duggal, co-founder of Builder.ai, has perfected the art of this balance, creating a company culture where creativity and growth are nurtured at each stage.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Knowledge engineering: from people to machines and back
Hardware Implementation of Algorithm for Cryptanalysis
1. International Journal on Cryptography and Information Security (IJCIS), Vol.3, No.1, March 2013
HARDWARE IMPLEMENTATION OF
ALGORITHM FOR CRYPTANALYSIS
Harshali Zodpe1 , Prakash Wani2 , Rakesh Mehta3
1
Department of Electronics and Telecommunication Engineering, Maharashtra Institute
of Technology, Pune, India
harshaliz1982@gmail.com
2
Department of Electronics and Telecommunication Engineering, College of Engineer-
ing, Pune, India
pwwani@gmail.com
3
Mechatronics Test Equipments (I) Pvt. Ltd., Pune, India
rakesh.mehta57@gmail.com
ABSTRACT
Cryptanalysis of block ciphers involves massive computations which are independent of each other and can
be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low
cost Field Programmable Gate Arrays (FPGA’s), building special purpose hardware for computationally
intensive applications has now become possible. For this the Data Encryption Standard (DES) is used as a
proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on
FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are com-
pared and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this
work is to make cryptanalysis faster and better.
KEYWORDS
Cryptanalysis, FPGA’s, DES, Rolled and Unrolled DES architectures
1. INTRODUCTION
The extensive use of computers and electronic data storage and transmission with the exponential
growth of internet has generated strong demand for a robust security mechanism, and they in turn
depend critically on cryptographic protection. The computer power is also increasing fast with the
change in technology and it is important to assess the strength of deployed cryptographic algo-
rithm.
Cryptanalysis is the science of revealing the hidden data of a cryptographic algorithm or system,
either to get at the data for the own sake or to test the strength of the cryptographic algorithm be-
ing used. Cryptanalysis of ciphers (encrypted information) usually involves massive and parallel
computations. The security parameter (in particular the key length) of almost all practical crypto
algorithms is chosen such that attacks with conventional computers are computationally infeasi-
ble. Such parallel functionality can be realized by special purpose hardware blocks that can be
operated simultaneously, improving the time complexity of the overall computations. But the
high non-recurring engineering cost for Application Specific Integrated Circuits (ASIC’s) had put
most projects for building special purpose hardware for cryptanalysis out of the reach for com-
mercial or research institutions.
DOI:10.5121/ijcis.2013.3102 7
2. International Journal on Cryptography and Information Security (IJCIS), Vol.3, No.1, March 2013
However, Reconfigurable Computing offers advantages over traditional software and hardware
implementations of computationally intensive algorithms. Reconfigurable computing is based on
using low cost FPGA’s which can be configured after fabrication to take advantage of a hardware
design but still maintain the flexibility of software. Thus Cryptanalytic hardware has now become
a possibility outside government agencies.
Depending on what information the adversary can obtain the different attack scenarios can be
distinguished as Ciphertext-Only attack, Known-Plaintext attack, Chosen-Plaintext attack, Cho-
sen-ciphertext attack, Adaptive Chosen-Plaintext/Ciphertext attack as published in [1].
This paper presents a FPGA based hardware design for cryptanalysis of DES based on known-
plaintext attack using brute force technique. The DES algorithm is chosen for implementation as
it is basic cryptographic algorithm and is used by academicians as a test unit for experimentation.
The idea is to create multiple instances of the key search engine in an FPGA chip to make the
cryptanalysis process faster and provide a better cost performance ratio.
2. HISTORICAL BACKGROUND
Cryptanalysis has a historical background. Cryptanalysis is practiced by a broad range of organi-
zations to test the strength of the cryptosystem being used. The first exhaustive DES key search
machine estimation was proposed by Diffie and Hellman in 1977 [2]. It contained 106 chips, with
an estimated cost of US$ 20 million and a 12 hour expected search time. After few years, a first
detailed hardware design description for a brute force attack was presented by Michael Wiener at
CRYPTO’93 [3]. It was estimated that the machine could be built for less than a million US dol-
lars. The proposed machine consisted of 57, 000 DES chips that could recover a key every
three and half hours. In 1997, a detailed cost estimate for three different approaches for DES key
search, distributed computing, FPGAs and custom ASIC designs, was presented by M. Blaze [4].
In 1998, the Electronic Frontier Foundation (EFF) finally built a DES hardware cracker called
Deep Crack which could perform an exhaustive key search within 56 hours [5]. Their DES crack-
er consisted of 1, 536 custom designed ASIC chips at the material cost of around US$ 250,000
and could search 88 billion keys per second. In 2006, the Cost Optimal Parallel Code Breaker
(COPACOBANA) for DES brute-force attack was built for less than US$ 10,000 [6].
COPACOBANA hosts 120 low-cost FPGAs and is the latest developed cryptanalysis hardware
capable of breaking DES in less than one week on average. With the emergence of newer and
powerful devices, continuous efforts are being made to make cryptanalysis faster and better.
3. DESCRIPTION OF DES ALGORITHM
The Data Encryption Standard (DES) is one of the first commercially developed ciphers. DES
was published as a U.S. Federal Information Processing Standard, FIPS-46 [7]. DES is a block
cipher operating on 64-bit data blocks. The encryption transformation depends on a 56-bit secret
key and consists of sixteen rounds surrounded by two permutation layers. The decryption process
is the same as encryption, except the order of the round keys is reversed as compared to the en-
cryption process as shown in Figure 1.
As seen in Figure1, the first block is initial permutation. It changes the order of the input bits ac-
cording to a fixed permutation. The result is then divided into two equal halves of 32-bit each i.e.
Li and Ri where ‘i’ denotes the round number. In each round, the previous word Ri is fed to a
round function ‘f’ and the result is then XORed to the previous word Li. Both the words are then
swapped and the algorithm proceeds to the next iteration. The round function ‘f’ is key dependent
and involves the following steps. The first step is expansion. Here the 32-bit input word is ex-
panded to 48-bits by duplicating and reordering the right half of the bits. This input is then
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3. International Journal on Cryptography and Information Security (IJCIS), Vol.3, No.1, March 2013
XORed with the required key depending on the round number in the second step. In the third step,
the 48-bits output from previous step is split into eight 6-bits words which are substituted in eight
parallel 6x4 bit S-boxes. This substitution increases the strength of the cryptosystem. The last step
is permutation. In this step the 32-bit output from previous step is reordered according to a fixed
permutation.
Figure 1- DES Decryption Process
The subkeys (keys generated from the given input key) required for the 16-rounds are calculated
by the key schedule algorithm. Figure 2 shows the key schedule algorithm. The block PC1 of the
key schedule algorithm discards the 8 parity bits from the input 64-bit key and divides the resul-
tant 56-bits into two halves of 28-bit each i.e., Ci and Di. These are cyclically rotated over one
position to the left after rounds 1, 2, 9, 16 and over two positions after all other rounds. The round
keys are then constructed by repeatedly extracting 48-bits from Ci and Di at 48 fixed positions
determined by block PC2. Thus the keys generated are Key1 to Key16 for the 16-rounds. For
decryption process the subkeys have to be applied in reverse order. Hence SRL16 block is used to
reverse the order of subkeys. The SRL16 is an alternative mode for the look-up tables where they
are used as 16-bit shift registers. These shift registers enable delay or latency compensation.
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4. International Journal on Cryptography and Information Security (IJCIS), Vol.3, No.1, March 2013
Figure 2 – Key Schedule Algorithm
4. ARCHITECTURAL CONSIDERATIONS FOR HARDWARE
IMPLEMENTATION
The design is implemented considering architecture options for speed area optimization. For cryp-
tanalysis the ciphertext is deciphered under each key and the result is compared with the known
plaintext. If they are equal, then it is possible that the key tried is the correct key. Thus for crypta-
nalysis first decryption has to be performed with each key. The decryption takes 16-rounds to
decipher the ciphertext. DES algorithm contains an iterative structure. Data is passed through the
same set of steps called ‘round’ 16 times, each time with a different sub-key from the key trans-
formation. The first architecture is implemented using Rolled technique where only one round is
design and using a multiplexer, the same round is used 16 times with different sub-key for each
round as shown in Figure 3. This architecture is area efficient but with lesser throughput.
As seen from Figure 3, the incoming data is passed through the initial permutation. The output
from IP block is then passed 16-times through the round along with the 16 sub-keys generated by
the ‘subkey gen’ block. In order to loop the output back to the input multiplexer is used. The mul-
tiplexer switches the input’s of the data from the previous round and the new input data. The sec-
ond architecture that is implemented is the Unrolled architecture as shown in Figure 4. Unrolling
an iterative loop increases throughput. Here 16 instances are created for 16-rounds. In this design
better throughput can be achieved at the cost of increased area utilization. The throughput can be
further improved by using pipelining.
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5. International Journal on Cryptography and Information Security (IJCIS), Vol.3, No.1, March 2013
Figure 3 - DES Decryption using Rolled architecture
For pipelining registers are inserted between each step. In a pipelined design the new data can
begin processing before the prior data has finished processing. However, there exists a degree of
pipelining that maximizes the throughput per unit area.
Figure 4 - DES Decryption using Unrolled architecture with pipelining
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6. International Journal on Cryptography and Information Security (IJCIS), Vol.3, No.1, March 2013
5. Cryptanalysis of DES
Figure 5 – Block Diagram for Cryptanalysis of DES
This paper presents a FPGA based hardware design for cryptanalysis of DES based on known-
plaintext attack using brute force technique. A known-plaintext attack requires the adversary to
have access to (part of) the plaintext corresponding to the captured ciphertext blocks. In the pro-
posed design using brute force technique, the captured ciphertext block is decrypted with all poss-
ible keys and the resultant plaintext is compared with the know-plaintext. As shown in Figure 5,
the DES Decryption block decrypts the ciphertext and the resultant plaintext is compared with the
known-plaintext. The key for which the resultant plaintext matches with the known plaintext is
considered to be the correct key.
Each DES Decryption block decrypts the ciphertext with different key. Thus with ‘n’ nos. of DES
Decryption blocks ‘n’ different keys can be searched in one clock cycle thereby reducing the time
required for key search by a factor of ‘n’. The no. of DES Decryption blocks ‘n’ depends on the
available logic resources in an FPGA and the logic utilization of one DES Decryption block.
6. IMPLEMENTATION OF DES CRYPTANALYSIS
The aim of the hardware is the probable key search to be accomplished by partitioning the solu-
tion space on the FPGA chip and instantiating multiple instances of the design in parallel. As the
solution space is independent and inter-process communication is hardly required, the key search
time can be reduced by ‘n’ fold for ‘n’ instances of the design in single a FPGA chip.
We have implemented the design in Virtex-4 FPGA chip (xc4vlx100-12ff1148) using Xilinx 13.1
development platform. The design is implemented using both Rolled and Unrolled architecture.
After synthesis of the design incorporating key search engines in a single FPGA along with the
additional logic required for finding the correct key, the device utilization and throughput for both
the architectures are as shown below.
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7. International Journal on Cryptography and Information Security (IJCIS), Vol.3, No.1, March 2013
6.1. Using Rolled Architecture
The usage of 1,662 slices, 892 slice flip-flops (FF) and 3,187 Look up Tables (LUTs) is reported
by the tool. (3% slices, 0% slice FF and 3% LUT utilization of the xc4vlx100-12ff1148 device
respectively). The throughput achieved for the design is 0.817GBPS with maximum frequency of
230.063MHz.
6.2. Using Unrolled Architecture
The usage of 9,019 slices, 7,614 slice flip-flops and 16,954 LUTs is reported by the tool. (18%
slices, 7% slice FF and 17% LUT utilization of the xc4vlx100-12ff1148 device respectively). The
throughput achieved for the design is 0.874GBPS with maximum frequency of 245.874MHz.
From the above experimental results, the device utilization for design using Rolled architecture is
considerably less as compared to design using Unrolled architecture. Hence the Rolled architec-
ture was selected for implementation. 256 key search instances for the Rolled architecture could
be fit in a single FPGA with a clock frequency of 323.515MHz. With the clock frequency
achieved, the entire key space can be searched in approximately 5 days. A comparative summary
is shown in Table 1 with the results obtained in [6].
Ours [6]
No. of FPGA’s 01 120
No. of instances per FPGA 256 04
Device utilization per FPGA 25% Slice registers and 96% Slice LUT’s ---
Operating Frequency per 323.515MHz 100MHz
FPGA
Time for Exhaustive Key Approximately 5 days Approx.
search 8.7 days
Table 1. Implementation Results
7. RESULTS
7.1. Using Rolled Architecture
I/P- plaintext<=x"12cf4d587bf4eb08";
I/P- ciphertext<=x"b6060c26730925bc";
O/P- Key<= x"00000000000001";
Figure 6. Simulation result for key= x"00000000000001"
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8. International Journal on Cryptography and Information Security (IJCIS), Vol.3, No.1, March 2013
I/P- plaintext<=x"12cf4d587bf4eb08";
I/P- ciphertext<=x" 91dbf8a0e3f63324";
O/P- Key<= x"f0000000000011";
Figure 7 - Simulation result for key= x"f0000000000011"
Referring to Figures 6-7, using the Rolled architecture with the given plaintext-cipher text pair,
the correct key x"00000000000001" and x"f0000000000011" is obtained at 7,300 ns and 58,500
ns respectively. Using single instance of the key search engine would take months to search the
correct key x"f0000000000011". By running four instances in parallel the search time has consi-
derably reduced.
8. CONCLUSION
This work presents the design for cryptanalysis of DES algorithm based on Rolled architecture
using FPGA. Based on the experimental results it is found that the Rolled architecture requires
less area and can search the entire solution space in less time as compared to the Unrolled archi-
tecture. In this work we could fit 256 instances of key search in a single FPGA, such that the ex-
haustive key search on DES Algorithm can be done in approximately 5 days. Expanding the con-
cept for AES Algorithm to fit maximum instances of the key search engine in a single FPGA and
implementing the design in FPGA is the future work of this paper.
ACKNOWLEDGEMENTS
We would like to thank the entire team from Mechatronics Test Equipments (I) Pvt Ltd, Pune for their val-
uable guidance and support.
9. REFERENCES
[1] Christophe De Canniere, Alex Biryukov and Bart Preneel, “An introduction to block cipher cryp-
tanalysis,” Proceedings of The IEEE, Vol. 94, No. 2, pp. 346-356,February 2006.
[2] W. Diffe and M. Hellman, “Exhaustive cryptanalysis of the NBS Data Encryption Standard,”
COMPUTER, Vol. 10, No. 6, pp.74-84, June 1977.
[3] M. J. Wiener, “Efficient DES Key Search,” Crypto ’93, Santa Barbara, California, USA, August
1993. Reprinted in Practical Cryptography for Data Internetworks, W. Stallings editor, IEEE Com-
puter Society Press, 1996, pp. 31-79.
[4] M. Blaze, W. Diffie, R. L. Rivest, B. Schneier, T. Shimomura, E. Thompson, and M. Wiener, “Mi-
nimal Key Lengths for Symmetric Ciphers to Provide Adequate Commercial Security,” Tech-nical
report, Security Protocols Workshop, Cambridge, UK, January 1996. Available at
http://www.counterpane.com/keylength.html.
[5] Electronic Frontier Foundation, Cracking DES: Secrets of Encryption Research, Wiretap Politics &
Chip Design. O’Reilly & Associates Inc., July 1998.
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9. International Journal on Cryptography and Information Security (IJCIS), Vol.3, No.1, March 2013
[6] S. Kumar, C. Paar, J. Pelzl, G. Pfeiffer, and M. Schimmler, “Breaking Ciphers with COPACOBANA
- A Cost-Optimized Parallel Code Breaker”. In L. Goubin and M. Matsui, editors, Proceedings of the
Workshop on Cryptograpic Hardware and Embedded Systems (CHES 2006), volume 4249 of LNCS,
pages 101–118. Springer-Verlag,2006. Available at
http://www.copacobana.org/paper/copacobana_CHES2006.pdf
[7] National Bureau of Standards, FIPS PUB 46, The Data Encryption Standard, Federal Information
Processing Standard, NIST, U.S. Dept. of Commerce, Jan. 1977.
[8] B.Schneier, Applied Cryptography, second ed. John Wiley and Sons, 1996.
Authors
Ms.Harshali Zodpe completed her B.E. in Electronics and Communication Engineering from
Visvesvaraya National Institute of Technology, Nagpur, M.E in VLSI Design from Ramdeo-
baba Kamla Nehru College of Engineering, Nagpur University, Nagpur. Her areas of inter-
ests are VLSI, cryptography & Embedded Systems. Currently she is pursuing her Ph.D from
College of Engineering, Pune.
Dr. P.W.Wani has received his M.E. and Ph.D in Electroncis and Telecommunication
from College of Engineering, Pune. His areas of interest are VLSI, Microelectronics and
parallel Processing. He was the dean academics of Pune University. Currently he is
working as a professor in the department of Electroncis and Telecommunication from
College of Engineering, Pune.
Mr. Rakesh Mehta received his B.E from College of Engineering Pune and M.Tech from
IIT, Madras. He has been an entrepreneur for the past 25 years and his areas of expertise
are Digital Design and FPGA based High Speed designs. Currently he is the Director,
Mechatronics Test Equipment and Bitmapper Integration Technologies, Pune.
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