This document summarizes a seminar presentation on implementing cryptography algorithms with high throughput on GPUs and FPGAs. It introduces tiny encryption algorithm (TEA) and an extended version of TEA (XTEA) as lightweight cryptography algorithms suitable for hardware acceleration. It describes implementing TEA and XTEA on GPUs and FPGAs using cryptographic co-processors and hardware acceleration tools. Results show that FPGAs perform better for smaller plaintext sizes while GPUs achieve higher throughput for larger plaintext sizes.

1. Seminar on
High Throughput Implementations
of Cryptography algorithms on
GPU and FPGA
Presented by :
Mr. Nitin Uttam Shete
Guided By :
Prof.Jameer Kotwal
1
High throughput implementation of
cryptography algorithms on GPU and FPGANMET

2. Table of content
 Introduction.
 Problem statement.
 Light weight cryptography algorithm.
 Cryptographic co-processors.
 Cryptographic hardware acceleration and
analysis tool(CHAAT).
 Results.
 Throughput calculation.
 Conclusion.
 References.
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High throughput implementation of
cryptography algorithms on GPU and
FPGA

3. INTRODUCTION
Cryptography
CPU Vs GPU
High throughput implementation of
cryptography algorithms on GPU and
FPGA 3

4. Cryptography:
High throughput implementation of
cryptography algorithms on GPU and
FPGA 4

5. CPU VS GPU:
High throughput implementation of
cryptography algorithms on GPU and
FPGA 5

6. Problem Statement
 High power.
 Large response time.
 Poor performance
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High throughput implementation of
cryptography algorithms on GPU and
FPGA

7. Light Weight Cryptography Algorithm
A. Tiny encryption algorithm
B. Extended version of tea
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High throughput implementation of
cryptography algorithms on GPU and
FPGA

8. Tiny Encryption Algorithm
Pseudo-code for TEA
for i = 0 to N do
sum+ = delta
v0+ = ((v1 << 4)+k0) (v1+sum) ((v1 >> 5)+k1)
v1+ = ((v0 << 4)+k2) (v0+sum) ((v0 >> 5)+k3)
end for
High throughput implementation of
cryptography algorithms on GPU and
FPGA 8

9. Extended Version of TEA
Pseudo-code for XTEA
for i = 0 to N do
v0+ = ((v1 << 4) (v1 >> 5) + v1) (sum +
key[sum&3])
sum+ = delta
v1+ = ((v0 << 4) (v0 >> 5) + v0) (sum +
key[sum&3])
end for
High throughput implementation of
cryptography algorithms on GPU and
FPGANMIET 9

10. CRYPTOGRAPHIC CO-PROCESSORS
A. GPU IMPLEMENTATION
B. FPGA IMPLEMENTATION
10
High throughput implementation of
cryptography algorithms on GPU and
FPGA

11. A.GPU Implementation
GPU implementation flowchart of TEA
and XTEA
High throughput implementation of
cryptography algorithms on GPU and
FPGA 11

12. B.FPGA implementation
 Hardware block diagram of single round in
TEA
High throughput implementation of
cryptography algorithms on GPU and
FPGA 12

13. •Hardware block diagram of single round in XTEA
High throughput implementation of
cryptography algorithms on GPU and
FPGA 13

14. RESULTS
High throughput implementation of
cryptography algorithms on GPU and
FPGA 14

15. High throughput implementation of
cryptography algorithms on GPU and
FPGA 15

16. Throughput calculation
Throughput = Plaintext
latency*( plaintext – 1 ) *tclock
8
16
High throughput implementation of
cryptography algorithms on GPU and
FPGA

17. Conclusion
GPUs and FPGAs provide better throughput for
both TEA and XTEA as compared to CPUs.
FPGAs perform better for smaller plaintext sizes
whereas GPUs are better for larger plaintext
sizes.
 In terms of development time and cost, GPUs
are better suited as embedded cryptography co
processors as compared to FPGAs.
Future research efforts may address the use of
Zynq platform as a complete, low-cost
cryptographic co-processor.
High throughput implementation of
cryptography algorithms on GPU and
FPGA 17

18. REFERENCES
1) D. J. Wheeler and R. M. Needham. TEA, a tiny encryption algorithm,1995.
2)D. J. Wheeler and R. M. Needham. TEA extensions. Technical report, Cambridge
University, England, October 1997.
3) T. Eisenbarth, S. Kumar, C. Paar, A. Poschmann, and L. Uhsadel. A
survey of lightweight-cryptography implementations. IEEE Des. Test,
24(6):522–533, Nov. 2007.
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High throughput implementation of
cryptography algorithms on GPU and
FPGA