With increasing technology development in field of communication and Electronic devices, there is a need for better security service for information transfer in Medical Sectors, Banking, Financial and in other IoT applications etc. Fight against security attacks is of prime importance. Through Cryptographic techniques we can provide Authenticity as well as Confidentiality for the user data. In this paper, hardware implementation has been described for a real-time application of speech data encryption and decryption using AES algorithm along with the speech recognition using cross correlation technique. Verilog programming environment is used for AES cryptography whereas MATLAB is used for Speech recognition. ASIC design on AES core is implemented using Cadence tools. Number of gates, area and power used by AES core design has been drastically reduced by specifying wide range of constraints during front end designing. In Backend designing, layout of AES design, which is the physical geometric representation is also developed.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
New Technique Using Multiple Symmetric keys for Multilevel EncryptionIJERA Editor
In a world of accelerating communications, cryptography has become an essential component of the modern
means of communication systems. The emergence of the webas a reliable medium for commerce and
communication has made cryptography an essential component. Many algorithms or ciphers are in use
nowadays. The quality of the cipher is judged byits ability to prevent an unrelated party fromknowingthe
original content of the encrypted message. The proposed “Multilevel Encryption Model” is a cryptosystem that
adopts the basic principles of cryptography. It uses five symmetric keys (multiple)
in floating point numbers, plaintext, substitution techniques and key combinations with unintelligible
sequence to produce the ciphertext. The decryption process is also designed to reproduce the plaintext
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Wireless Network Security Architecture with Blowfish Encryption ModelIOSR Journals
Abstract: In this research paper ,we developed a model for a large network, wireless nodes are interconnected and each can be considered as a node processor that offer services to other node processors connected to a specific network. A very high proportion of the nodes that offer services need to carry out an authentication process so as to make an access request to the node offering the service. In this context, an integrated reconfigurable network security architecture moved to the application layer has become the need of the day for secure wireless data sharing. The security schemes of the seven layer OSI architecture need to be placed intrinsically in the wireless node itself and should be capable of supporting the MAC layer, IP address based layer and the routing protocols of the network layer. This work focuses on the use of emulator and embedded hardware architectures for wireless network security. In this work, the individual nodes can have a unique security signature pattern maintained by respective wireless nodes using an encryption algorithm and this is made dynamic. The metrics includes latency, throughput, Scalability, Effects of data transfer operation on node processor and application data located in the processor Keywords:Wireless Network security, Embedded hardware, Reconfigurable architecture, blowfish algorithm
Hardware Implementation of Algorithm for Cryptanalysisijcisjournal
Cryptanalysis of block ciphers involves massive computations which are independent of each other and can
be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low
cost Field Programmable Gate Arrays (FPGA’s), building special purpose hardware for computationally
intensive applications has now become possible. For this the Data Encryption Standard (DES) is used as a
proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on
FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared
and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this
work is to make cryptanalysis faster and better.
Features of genetic algorithm for plain text encryption IJECEIAES
The data communication has been growing in present day. Therefore, the data encryption became very essential in secured data transmission and storage and protecting data contents from intruder and unauthorized persons. In this paper, a fast technique for text encryption depending on genetic algorithm is presented. The encryption approach is achieved by the genetic operators Crossover and mutation. The encryption proposal technique based on dividing the plain text characters into pairs, and applying the crossover operation between them, followed by the mutation operation to get the encrypted text. The experimental results show that the proposal provides an important improvement in encryption rate with comparatively high-speed processing.
hardware implementation of aes encryption and decryption for low area & low p...Kumar Goud
Abstract-An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilinx tool.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
New Technique Using Multiple Symmetric keys for Multilevel EncryptionIJERA Editor
In a world of accelerating communications, cryptography has become an essential component of the modern
means of communication systems. The emergence of the webas a reliable medium for commerce and
communication has made cryptography an essential component. Many algorithms or ciphers are in use
nowadays. The quality of the cipher is judged byits ability to prevent an unrelated party fromknowingthe
original content of the encrypted message. The proposed “Multilevel Encryption Model” is a cryptosystem that
adopts the basic principles of cryptography. It uses five symmetric keys (multiple)
in floating point numbers, plaintext, substitution techniques and key combinations with unintelligible
sequence to produce the ciphertext. The decryption process is also designed to reproduce the plaintext
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Wireless Network Security Architecture with Blowfish Encryption ModelIOSR Journals
Abstract: In this research paper ,we developed a model for a large network, wireless nodes are interconnected and each can be considered as a node processor that offer services to other node processors connected to a specific network. A very high proportion of the nodes that offer services need to carry out an authentication process so as to make an access request to the node offering the service. In this context, an integrated reconfigurable network security architecture moved to the application layer has become the need of the day for secure wireless data sharing. The security schemes of the seven layer OSI architecture need to be placed intrinsically in the wireless node itself and should be capable of supporting the MAC layer, IP address based layer and the routing protocols of the network layer. This work focuses on the use of emulator and embedded hardware architectures for wireless network security. In this work, the individual nodes can have a unique security signature pattern maintained by respective wireless nodes using an encryption algorithm and this is made dynamic. The metrics includes latency, throughput, Scalability, Effects of data transfer operation on node processor and application data located in the processor Keywords:Wireless Network security, Embedded hardware, Reconfigurable architecture, blowfish algorithm
Hardware Implementation of Algorithm for Cryptanalysisijcisjournal
Cryptanalysis of block ciphers involves massive computations which are independent of each other and can
be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low
cost Field Programmable Gate Arrays (FPGA’s), building special purpose hardware for computationally
intensive applications has now become possible. For this the Data Encryption Standard (DES) is used as a
proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on
FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared
and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this
work is to make cryptanalysis faster and better.
Features of genetic algorithm for plain text encryption IJECEIAES
The data communication has been growing in present day. Therefore, the data encryption became very essential in secured data transmission and storage and protecting data contents from intruder and unauthorized persons. In this paper, a fast technique for text encryption depending on genetic algorithm is presented. The encryption approach is achieved by the genetic operators Crossover and mutation. The encryption proposal technique based on dividing the plain text characters into pairs, and applying the crossover operation between them, followed by the mutation operation to get the encrypted text. The experimental results show that the proposal provides an important improvement in encryption rate with comparatively high-speed processing.
hardware implementation of aes encryption and decryption for low area & low p...Kumar Goud
Abstract-An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilinx tool.
Hardware implementation of aes encryption and decryption for low area & power...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Fault Detection Scheme for AES Using Composite FieldAJAL A J
The cipher Rijndael is one of the five finalists of the Advanced Encryption Standard (AES)
The algorithm has been designed by Joan Daemen and Vincent Rijmen
It is a Block cipher.
The hardware implementation with 128-bit blocks and 128-bit keys is presented.
VLSI optimizations of the Rijndael algorithm are discussed and several hardware design modifications and techniques are used, such as memory sharing and parallelism.
PREDOMINANCE OF BLOWFISH OVER TRIPLE DATA ENCRYPTION STANDARD SYMMETRIC KEY A...IJNSA Journal
Computer data communication is the order of the day with Information Communication Technology (ICT) playing major role in everyone’s life, communicating with smart phones, tabs, laptops and desktops using internet. Security of the data transferred over the computer networks is most important as for as an organization is concerned. Hackers attempt hard to crack the software key and indulge in cyber crimes. In this paper, the main concern is not only to provide security to the data transferred at the software level but it provides the security at hardware level by the modified Blowfish Encryption and Decryption Algorithms. It results minimum delay, high speed, high throughput] and effective memory utilization compared to Blowfish (BF) and Triple Data Encryption Standard (TDES) algorithms. The implementation of Blowfish with modulo adder and Wave Dynamic Differential Logic (WDDL) is to provide security against Differential power analysis (DPA). In the proposed four implementations, BF with constant delay n-bit adder (BFCDNBA) yielded minimum delay, maximum frequency, high memory utilization and high throughput compared to BF with modulo adder and WDDL logic (BFMAWDDL), BF with modulo adder (BFMA) and TDES algorithms. The VLSI implementation of Blowfish and TDES algorithms is done using Verilog HDL.
Comparative Analysis of Cryptographic Algorithms and Advanced Cryptographic A...editor1knowledgecuddle
Today is the era of Internet and networks applications. So,Information security is a challenging issue in today’s technological world. There is a demand for a stronger encryption which is very hard to crack. The role of Cryptography is most important in the field of network security. There is a broad range of cryptographic algorithms that are used for securing networks and presently continuous researches on the new cryptographic algorithms are going on for evolving more advanced techniques for secures
communication. In this study is made for the cryptography algorithms, particularly algorithms- AES, DES, RSA, Blowfishare compared and performance is evaluated. Also some enhanced algorithms are described and compared with the enhanced algorithms.
Keywords - AES, DES, BLOWFISH, Decryption, Encryption, Security
Efficient two-stage cryptography scheme for secure distributed data storage i...IJECEIAES
Cloud computing environment requires secure access for data from the cloud server, small execution time, and low time complexity. Existing traditional cryptography algorithms are not suitable for cloud storage. In this paper, an efficient two-stage cryptography scheme is proposed to access and store data into cloud safely. It comprises both user authentication and encryption processes. First, a two-factor authentication scheme one-time password is proposed. It overcomes the weaknesses in the existing authentication schemes. The proposed authentication method does not require specific extra hardware or additional processing time to identity the user. Second, the plaintext is divided into two parts which are encrypted separately using a unique key for each. This division increases the security of the proposed scheme and in addition decreases the encryption time. The keys are generated using logistic chaos model theory. Chaos equation generates different values of keys which are very sensitive to initial condition and control parameter values entered by the user. This scheme achieves high-security level by introducing different security processes with different stages. The simulation results demonstrate that the proposed scheme reduces the size of the ciphertext and both encryption and decryption times than competing schemes without adding any complexity.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
PERFORMANCE EVALUATION OF BLOWFISH ALGORITHM ON SUPERCOMPUTER IMAN1 IJCNCJournal
Cryptographic applications are becoming increasingly more important in today’s world of data exchange,
big volumes of data need to be transferred safely from one location to another at high speed. In this paper,
the parallel implementation of blowfish cryptography algorithm is evaluated and compared in terms of
running time, speed up and parallel efficiency. The parallel implementation of blowfish is implemented
using message passing interface (MPI) library, and the results have been conducted using IMAN1
Supercomputer. The experimental results show that the runtime of blowfish algorithm is decreased as the
number of processors is increased. Moreover, when the number of processors is 2, 4, and 8, parallel
efficiency achieves up to 99%, 98%, and 66%, respectively.
Encryption and Compression of Audio-Video Data Using Enhanced AES and J-Bit A...ijsrd.com
AES is considered a good encryption algorithm in terms of providing security to a network in passing information (data) in form of audio, string, and video and in any other form. However it yields a low throughput resulting in slowness and increasing energy dispensation of server or an application. The Enhanced AES algorithm is proposed in this paper which works by using sequence counters and provides improved throughput as compare to conventional AES algorithm. The J-Bit Encoding is being a compression algorithm in lossless category which doesn't decrease the quality but reduce the size of data to some extent. It has been observed that the proposed encryption algorithm integrated to J-Bit Encoding algorithm will provide the effective security measures as well as increased throughput as a parameter and less bandwidth usage as the actual size of data shall not be sent along the network.
Design and implementation of proposed 320 bit RC6-cascaded encryption/decrypt...IJECEIAES
This paper attempts to build up a simple, strong and secure cryptographic algorithm. The result of such an attempt is “RC6-Cascade” which is 320-bits RC6 like block cipher. The key can be any length up to 256 bytes. It is a secret-key block cipher with precise characteristics of RC6 algorithm using another overall structure design. In RC6-Cascade, cascading of F-functions will be used instead of rounds. Moreover, the paper investigates a hardware design to efficiently implement the proposed RC6-Cascade block cipher core on field programmable gate array (FPGA). An efficient compact iterative architecture will be designed for the F-function of the above algorithm. The goal is to design a more secure algorithm and present a very fast encryption core for low cost and small size applications.
The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data also called Rijndael. The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data. Hardware-based cryptography is used for authentication of users and of software updates and installations. Software implementations can generally not be used for this, as the cryptographic keys are stored in the PC memory during execution, and are vulnerable to malicious codes. Hardware-based encryption products can also vary in the level of protection they provide against brute force rewind attacks, Offline parallel attacks, or other cryptanalysis attacks. The algorithm was implemented in FPGA due to its flexibility and reconfiguration capability. A reconfigurable device is very convenient for a cryptography algorithm since it allows cheap and quick alterations. The implementation of pipelined cryptography hardware was used to improve performance in order to achieve higher throughput and greater parallelism. The AES hardware was implemented in three modules contains of the encryption, the decryption and the key expansion module.
Hardware implementation of aes encryption and decryption for low area & power...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Fault Detection Scheme for AES Using Composite FieldAJAL A J
The cipher Rijndael is one of the five finalists of the Advanced Encryption Standard (AES)
The algorithm has been designed by Joan Daemen and Vincent Rijmen
It is a Block cipher.
The hardware implementation with 128-bit blocks and 128-bit keys is presented.
VLSI optimizations of the Rijndael algorithm are discussed and several hardware design modifications and techniques are used, such as memory sharing and parallelism.
PREDOMINANCE OF BLOWFISH OVER TRIPLE DATA ENCRYPTION STANDARD SYMMETRIC KEY A...IJNSA Journal
Computer data communication is the order of the day with Information Communication Technology (ICT) playing major role in everyone’s life, communicating with smart phones, tabs, laptops and desktops using internet. Security of the data transferred over the computer networks is most important as for as an organization is concerned. Hackers attempt hard to crack the software key and indulge in cyber crimes. In this paper, the main concern is not only to provide security to the data transferred at the software level but it provides the security at hardware level by the modified Blowfish Encryption and Decryption Algorithms. It results minimum delay, high speed, high throughput] and effective memory utilization compared to Blowfish (BF) and Triple Data Encryption Standard (TDES) algorithms. The implementation of Blowfish with modulo adder and Wave Dynamic Differential Logic (WDDL) is to provide security against Differential power analysis (DPA). In the proposed four implementations, BF with constant delay n-bit adder (BFCDNBA) yielded minimum delay, maximum frequency, high memory utilization and high throughput compared to BF with modulo adder and WDDL logic (BFMAWDDL), BF with modulo adder (BFMA) and TDES algorithms. The VLSI implementation of Blowfish and TDES algorithms is done using Verilog HDL.
Comparative Analysis of Cryptographic Algorithms and Advanced Cryptographic A...editor1knowledgecuddle
Today is the era of Internet and networks applications. So,Information security is a challenging issue in today’s technological world. There is a demand for a stronger encryption which is very hard to crack. The role of Cryptography is most important in the field of network security. There is a broad range of cryptographic algorithms that are used for securing networks and presently continuous researches on the new cryptographic algorithms are going on for evolving more advanced techniques for secures
communication. In this study is made for the cryptography algorithms, particularly algorithms- AES, DES, RSA, Blowfishare compared and performance is evaluated. Also some enhanced algorithms are described and compared with the enhanced algorithms.
Keywords - AES, DES, BLOWFISH, Decryption, Encryption, Security
Efficient two-stage cryptography scheme for secure distributed data storage i...IJECEIAES
Cloud computing environment requires secure access for data from the cloud server, small execution time, and low time complexity. Existing traditional cryptography algorithms are not suitable for cloud storage. In this paper, an efficient two-stage cryptography scheme is proposed to access and store data into cloud safely. It comprises both user authentication and encryption processes. First, a two-factor authentication scheme one-time password is proposed. It overcomes the weaknesses in the existing authentication schemes. The proposed authentication method does not require specific extra hardware or additional processing time to identity the user. Second, the plaintext is divided into two parts which are encrypted separately using a unique key for each. This division increases the security of the proposed scheme and in addition decreases the encryption time. The keys are generated using logistic chaos model theory. Chaos equation generates different values of keys which are very sensitive to initial condition and control parameter values entered by the user. This scheme achieves high-security level by introducing different security processes with different stages. The simulation results demonstrate that the proposed scheme reduces the size of the ciphertext and both encryption and decryption times than competing schemes without adding any complexity.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
PERFORMANCE EVALUATION OF BLOWFISH ALGORITHM ON SUPERCOMPUTER IMAN1 IJCNCJournal
Cryptographic applications are becoming increasingly more important in today’s world of data exchange,
big volumes of data need to be transferred safely from one location to another at high speed. In this paper,
the parallel implementation of blowfish cryptography algorithm is evaluated and compared in terms of
running time, speed up and parallel efficiency. The parallel implementation of blowfish is implemented
using message passing interface (MPI) library, and the results have been conducted using IMAN1
Supercomputer. The experimental results show that the runtime of blowfish algorithm is decreased as the
number of processors is increased. Moreover, when the number of processors is 2, 4, and 8, parallel
efficiency achieves up to 99%, 98%, and 66%, respectively.
Encryption and Compression of Audio-Video Data Using Enhanced AES and J-Bit A...ijsrd.com
AES is considered a good encryption algorithm in terms of providing security to a network in passing information (data) in form of audio, string, and video and in any other form. However it yields a low throughput resulting in slowness and increasing energy dispensation of server or an application. The Enhanced AES algorithm is proposed in this paper which works by using sequence counters and provides improved throughput as compare to conventional AES algorithm. The J-Bit Encoding is being a compression algorithm in lossless category which doesn't decrease the quality but reduce the size of data to some extent. It has been observed that the proposed encryption algorithm integrated to J-Bit Encoding algorithm will provide the effective security measures as well as increased throughput as a parameter and less bandwidth usage as the actual size of data shall not be sent along the network.
Design and implementation of proposed 320 bit RC6-cascaded encryption/decrypt...IJECEIAES
This paper attempts to build up a simple, strong and secure cryptographic algorithm. The result of such an attempt is “RC6-Cascade” which is 320-bits RC6 like block cipher. The key can be any length up to 256 bytes. It is a secret-key block cipher with precise characteristics of RC6 algorithm using another overall structure design. In RC6-Cascade, cascading of F-functions will be used instead of rounds. Moreover, the paper investigates a hardware design to efficiently implement the proposed RC6-Cascade block cipher core on field programmable gate array (FPGA). An efficient compact iterative architecture will be designed for the F-function of the above algorithm. The goal is to design a more secure algorithm and present a very fast encryption core for low cost and small size applications.
The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data also called Rijndael. The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data. Hardware-based cryptography is used for authentication of users and of software updates and installations. Software implementations can generally not be used for this, as the cryptographic keys are stored in the PC memory during execution, and are vulnerable to malicious codes. Hardware-based encryption products can also vary in the level of protection they provide against brute force rewind attacks, Offline parallel attacks, or other cryptanalysis attacks. The algorithm was implemented in FPGA due to its flexibility and reconfiguration capability. A reconfigurable device is very convenient for a cryptography algorithm since it allows cheap and quick alterations. The implementation of pipelined cryptography hardware was used to improve performance in order to achieve higher throughput and greater parallelism. The AES hardware was implemented in three modules contains of the encryption, the decryption and the key expansion module.
IMPLEMENTATION OF AES AS A CUSTOM HARDWARE USING NIOS II PROCESSORacijjournal
In this paper Advanced Encryption Standard (AES) algorithm has been designed and implemented as custom hardware. The algorithm is controlled through C-code written in NIOS II IDE. AES as a custom hardware is interfaced with the system designed around NIOS II Processor using SOPC builder tool. AES is written in hardware in VHDL language and the interface is through GPIO (General Purpose Input / Output Port). AES implemented using data size of 128 bits, while the length of the key used is of 128 bits. The key size of AES used is of 128 bits, as it is secure from the different attacks in existence. The FPGA used is CYCLONE II from Altera. AES as a custom hardware increases the speed of encryption and serves as an accelerator and hence improves the performance of the system.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Hybrid Cryptography security in public cloud using TwoFish and ECC algorithmIJECEIAES
Cloud computing is a structure for rendering service to the user for free or paid basis through internet facility where we can access to a bulk of shared resources which results in saving managing cost and time for large companies, The data which are stored in the data center may incur various security, damage and threat issues which may result in data leakage, insecure interface and inside attacks. This paper will demonstrate the implementation of hybrid cryptography security in public cloud by a combination of Elliptical Curve Cryptography and Twofish algorithm, which provides an innovative solution to enhance the security features of the cloud so that we can improve the service thus results in increasing the trust over the technology.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
The papers for publication in The International Journal of Engineering& Science are selected through rigorous peer reviews to ensure originality, timeliness, relevance, and readability.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Today information security is a challenging factor that touches a lot of areas, including computers and communications. Message communication is kept secure through cryptography so that an eavesdropper is not able to decipher a transmitted message. One of the oldest and simplest known algorithms for cryptography is the Caesar cipher algorithm. In this paper, three programs based on Java, C++, and Python languages have been developed to implement the Caesar cipher algorithm to aid information security students and help them understand this fundamental algorithm. A code flow chart is used for each program to describe the code’s flow. It also reveals the sequence of steps for the code’s main methods, as well as the relationships between them. Furthermore, various technical descriptions are presented in detail for each of the methods used in both the encoding and the decoding of the messages.
A NOVEL STRUCTURE WITH DYNAMIC OPERATION MODE FOR SYMMETRIC-KEY BLOCK CIPHERSIJNSA Journal
Modern Internet protocols support several modes of operation in encryption tasks for data confidentiality to keep up with varied environments and provide the various choices, such as multi-mode IPSec support. To begin with we will provide a brief background on the modes of operation for symmetric-key block ciphers. Different block cipher modes of operation have distinct characteristics. For example, the cipher block chaining (CBC) mode is suitable for operating environments that require self-synchronizing capabilities, and the output feedback (OFB) mode requires encryption modules only. When using symmetric-key block cipher algorithms such as the Advanced Encryption Standard (AES), users performing information encryption often encounter difficulties selecting a suitable mode of operation. This paper describes a structure for analyzing the block operation mode combination. This unified operation structure (UOS) combines existing common and popular block modes of operation. UOS does multi-mode of operation with most existing popular symmetric-key block ciphers and do not only consist of encryption mode such as electronic codebook (ECB) mode, cipher block chaining (CBC) mode, cipher feedback (CFB) mode and output feedback (OFB) mode, that provides confidentiality but also message authentication mode such as the cipher block chaining message authentication code (CBC-MAC) in cryptography. In Cloud Computing, information exchange frequently via the Internet and on-demand. This research provides an overview and information useful for approaching low-resource hardware implementation, which is proper to ubiquitous computing devices such as a sensor mote or an RFID tag. The use of the method is discussed and an example is given. This provides a common solution for multimode and this is very suitable for ubiquitous computing with several resources and environments. This study indicates a more effectively organized structure for symmetric-key block ciphers to improve their application scenarios. We can get that it is flexible in modern communication applications.
Wireless communication systems, multi-input multi-output (MIMO) technology has been recognized as the key ingredient to support higher data rate as well as better transmission quality after using this algorithm of a XTEA or MTEA scheme. Modified TEA is used for encryption of the text. Then decryption unit for decrypting the cipher text and convert that to plain text. Key generation unit is to generate 128bit key and these keys are send along with cipher text. Encryption and decryption system ensures the original data are send and received by the users in secured environment. The Received data are retrieving by the authorized users by providing key generation like private keys this Key Pattern generations provide more security to the messages. Extended tiny encryption algorithm or modified tiny encryption algorithm and tiny encryption algorithm are used to enhance the size, speed and security in the system. These algorithms are better compared to configurable joint detection decoding algorithm (CJDD) and valid symbol finder algorithm.
Implementation of Cryptography Architecture with High Secure CoreIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
32 9139 it rtl modelling for the cipher blcok ((edit lafi)IAESIJEECS
The demand of satellite communication, the security algorithms are to be designed in the board. The information from the satellite to the ground is required the data security with the cryptographic algorithms. Advanced encryption standard (AES) is one of the promising cryptographic algorithms for the terrestrial communication. In this paper, the encryption and decryption is mainly focused on the cipher block chaining (CBC) mode for achieving the high secured data transmission. For efficient data transmission, the AES algorithm is implemented by using CBC mode. The proposed work is designed by using RTL modeling and also the minimum numbers of logical elements are used for implementation.
A PERFORMANCE EVALUATION OF COMMON ENCRYPTION TECHNIQUES WITH SECURE WATERMAR...IJNSA Journal
Ciphering algorithms play a main role in information security systems. Therefore in this paper we are considering the important performance of these algorithms like CPU time consumption, memory usage and battery usage. This research tries to demonstrate a fair comparison between the most common algorithms and with a novel method called Secured Watermark System (SWS) in data encryption field according to CPU time, packet size and power consumption. It provides a comparison the most known algorithms used in encryption: AES (Rijndael), DES, Blowfish, and Secured Watermark System (SWS).
For comparing these algorithms with each other variations of data block sizes, and a variation of encryption-decryption speeds where used in this research.
In addition a comparison with different platforms such as Windows 8, Windows XP and Linux has been conducted. Finally the results of the experimentation demonstrate the performance and efficiency of the compared encryption algorithms with different parameters.
Ciphering algorithms play a main role in information security systems. Therefore in this paper we are
considering the important performance of these algorithms like CPU time consumption, memory usage and
battery usage. This research tries to demonstrate a fair comparison between the most common algorithms
and with a novel method called Secured Watermark System (SWS) in data encryption field according to
CPU time, packet size and power consumption. It provides a comparison the most known algorithms used
in encryption: AES (Rijndael), DES, Blowfish, and Secured Watermark System (SWS).
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FPGA and ASIC Implementation of Speech Encryption and Decryption using AES Algorithm with Speech Recognition
1. FPGA and ASIC Implementation of Speech
Encryption and Decryption using AES Algorithm with
Speech Recognition
Jagannatha K.B, Yogesh Y.L, Vadiraja Desai H.S, Shreyas G.S, Shivananad Hachadad
Department of ECE, BMSIT&M
Bangalore-560064, India
Email id: jagan@bmsit.in
Abstract - With increasing technology development in field of communication and Electronic devices, there is a need for better
security service for information transfer in Medical Sectors, Banking, Financial and in other IoT applications etc. Fight against security
attacks is of prime importance. Through Cryptographic techniques we can provide Authenticity as well as Confidentiality for the user
data. In this paper, hardware implementation has been described for a real-time application of speech data encryption and decryption
using AES algorithm along with the speech recognition using cross correlation technique. Verilog programming environment is used
for AES cryptography whereas MATLAB is used for Speech recognition. ASIC design on AES core is implemented using Cadence
tools. Number of gates, area and power used by AES core design has been drastically reduced by specifying wide range of constraints
during front end designing. In Backend designing, layout of AES design, which is the physical geometric representation is also
developed.
Keywords— Advanced Encryption Standard (AES), Field programmable gate-array (FPGA), Application specific integrated circuit
(ASIC), Speech Recognition, Cross-Correlation
I. INTRODUCTION
Security and privacy happens to be the two major aspects of ever-growing speech communication system. Shadow
Brokers, WannaCry, Goldeneye, Cloudbleed are some of the Biggest Cybersecurity Disasters so far. Speech cryptography is
the method of sending information which has been spoken in a masked way by carrying out encryption of data at transmitter
end and decryption at receiver end. Cryptography is a method used to detect the masked messages. Encryption involves
scrambling of the original data, and the reverse process constitutes decryption [2].
Speech recognition comes under the field of computing language which is used to develop methods and technology
which can be used for enabling the recognition and translation of spoken language into text by the computer [6]. The speech file
obtained will be encrypted on an FPGA. Then the encrypted file will be transferred to another FPGA for decryption which is in
turn transferred to a computer in which original speech is recovered using the MATLAB. Cross correlation technique can also be
used to carry out speech recognition through MATLAB [7].
Block diagram which describes the functionality of the system is as shown in figure 1. Samples of Speech signal is
acquired using MATLAB and are stored in .txt file. These samples are passed on to an FPGA module(NEXYS 4 DDR fpga) to
carry out the encryption. Receiver side represents the FPGA decryption module(NEXYS 4 DDR fpga) to which the encrypted
samples are sent. Both fpga modules can be connected through RS232 communication link [4]. Decrypted samples represents are
the original speech samples. If these samples are read through MATLAB at specified bit rate, user speech is obtained. Cross
correlation technique is used to pass this user speech through speech recognition system .
This paper is organized as follows where Section II gives a brief introduction of Cryptography, AES and Speech
Recognition. Section III describes the simulation results obtained with respect to MATLAB and FPGA. The ASIC implementation
is discussed in section IV. The paper is concluded in section V.
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2. Figure 1. Block diagram of the proposed system
II. DESIGN
A. Cryptography
Cryptography is defined as the method of creating codes which allow the information to be hidden. It converts the
original data of the user into a unreadable format for an unauthorized user, due to which the unauthorized readers cannot decode it
.Information security field makes use of cryptography in different aspects. A key is very essential to decrypt the user
information. Integrity and privacy of the information is conserved both during transmission and storage. Symmetric and
Asymmetric Cryptography happens to be the two types of cryptography.
Asymmetric cryptography or public key cryptography, uses both public and private keys for encryption and decryption
of data. Encryption of plain text and decryption of cipher text is done using the same symmetric key algorithms. AES happens to
be a Symmetric Key cryptographic algorithm.
B. AES algorithm
AES works on a 4 × 4 column-major order matrix of bytes, which are called "state". Depending on the version used to
convert the plain text into the cipher text,the key size varies. The number of rounds constituting repetition are as follows:
Ten rounds for 128-bit keys.
Twelve rounds for 192-bit keys.
Fourteen rounds for 256-bit keys.
Each round contains several processing steps, where each step contains four similar but different stages which includes
one that depends on the key for encryption . Reverse set of rounds are applied to convert cipher text back to the plain text by using
the same encryption key [5].
Four steps of AES are as follows:-
1. SubBytes—It is a substitution step, where each byte is replaced with an another byte based on the predefined S-box.
2. ShiftRows—Here four rows will be left shifted cyclically by 0 ,1 ,2 and 3 bytes respectively .
3. MixColumns—It is a mixing operation, galois field multiplication takes place on each column of the state, generating a
new state as output .
4. AddRoundKey—In this step, Bitwise xor operation is carried out between each byte of the state and the round key.
Since, AES-128 bit version is used here, initial 128 bit key is expanded to 1408 bits needed for 10 rounds of operation using
Key expansion algorithm.AES utilizes key expansion process in which all round keys are generated from single 128-bit cipher key
to create round key for each round. The keys that are generated are of 128-bits length each. All the rounds are symmetric in nature
and key expansion process is used to eliminate the symmetry by having round dependent round constants. The possibility of
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3. equivalent keys is eliminated by nonlinearity of key expansion. There is no need for the mixing transformation in the last round of
encryption. The Last round of encryption module outputs a 128-bit cipher text.
Decryption happens to be the inverse process of encryption which involves inverse round transformations which are
applied to cipher text in order to get back the original data. Flow is described in the Figure 2 below.
Figure 2. AES-128 bit Encryption and Decryption Flow
C. Speech Recognition
Speech Recognition is defined as the method of capturing the spoken words using a microphone and hence converting
the voice signal into a digitally stored set of data. Speech recognition is used widely in most of the security project where there is
a need to tell your password to devices like computer to provide access to system applications.
The measure of similarity of two series as a function of displacement of one relative to the other is called as Cross
correlation [8]. It can also be called as the sliding dot-product or the sliding inner-product. It is commonly utilized for searching a
long signal for a shorter one. Pattern recognition for single particle analysis also finds applications in cross correlation. The xcorr
function of MATLAB happens to be a Cross-correlation function for a random process which includes autocorrelation. Syntax
for Correlation in MATLAB can be written as r = xcorr(x,y)
where r = xcorr(x,y) returns the cross-correlation of two discrete-time sequences which are named x and y.
D. Algorithm describing Speech Recognition using Cross- Correlation technique
Consider sample as voice where x=voice Read and compute x and store in y1. Consider total of 4 samples containing
different voice data [8].
1) z1=xcorr(x.y1), m1=max(z1)
2) Repeat steps 1 for all 4 samples.
3) Consider a=[m1 m2 m3 m4 m5] where m5=300 ,m5 is the threshold.
4) Compute m=max(a)
5) If m<=m1 read 1st file
6) elseif m<=mi, read ith file where 1<i<5
7) else read denied file
8) End
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4. III. RESULTS AND DISCUSSION
The functional design code was written using Verilog HDL (Hardware Description Language)and synthesised in Vivado
Design Suite. The proposed design has been implemented on NEXYS 4 DDR (XC7A100T-CSG324) boards [1] & [3]. VIO
(Virtual Input Output) debugging tools were used in implementation.
Simulation results of encryption module and decryption module are as shown in Figure 3. and Figure 4. respectively. The
resource utilization details of FPGA by encryption system and decryption system are mentioned in Table 1.
A. AES ENCRYPTION
Figure. 3 Simulation Results of AES Encryption on NEXYS 4 DDR
B. AES DECRYPTION
Figure. 4 Simulation Results of AES Decryption on NEXYS 4 DDR.
Resource Estimation Available Utilization
LUT 2365 63400 3.73%
FF 1548 12080 1.22%
IO 1 210 0.48%
BUFG 1 32 3.13%
Table 1 - Resource Utilization Table with respect to NEXYS 4 DDR fpga
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5. C. Speech Recognition Results
The graphs for comparison between the test and the sample audio files is derived using MATLAB [8]. Two of the test
files and four of the sample files which has speech (Spoken word) of one to four are considered. One of the test file will have a
match from four sample files and another test file has no match with any of the stored sample files. The loop starts which takes
test file as input cross correlated with other samples and the output graph is displayed using MATLAB. So, after cross correlatiing
with 4 other samples we will have four output graphs as shown below
) MATLAB.The results
have been described in figure 5(a) below.
Test.wav vs One.wav Test.wav vs Second.wav Test.wav vs Third.wav Test.wav vs Fourth.wav
Figure 5(a). Speech Recognition Test Case 1
N ) y W
MATLAB command prompt, the comparison will start and it will tell denied which means the file is not matching with any of the
sample files.Results for this case is described in below figure 5(b).
.
Ten.wav vs one.wav Ten.wav vs second.wav Ten.wav vs third.wav Ten.wav vs fourth.wav
Figure 5(b). Speech Recognition Test Case 2
Cross correlation technique works on pattern matching and is not the ideal solution for speech recognition. If two different signals
with similar pattern undergo cross correlation it may give wrong results. So enhanced speech recognition system should be
implemented [6].
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6. IV. ASIC IMPLEMENTATION
ASIC can be optimized for requiring low power, speed, design flexibility with small form factor. Clock gating, power
gating, pipeline etc. are available in ASIC which are not in FPGA. In ASIC you can implement analogue circuit and mixed signal
designs which are not possible in FPGA. Rather than implementing for general purpose ASIC can be customized for a particular
use.
A. Front End Design
It is the first part of ASIC designing. Designer will describe system specifications,which is converted into a VHDL or
Verilog language. Functional verification or behavioral simulation is performed to ensure the RTL design done is working
according to the specifications. Next step is Synthesis.
Synthesis converts the verilog or VHDL code into gate level netlist. according to specified constraints It takes into
account power, speed, size and hence the results may vary much from each other. Verification is done to find out whether
generated netlist specifies the logic. Table 2 describes the before and after synthesis results for the functional code written. The
HDL code to RTL synthesis is influenced by constraints. Wide range of synthesis constraints are available which basically
depends upon the tool used. Specific Input/output pins are assigned signals using I/O constraints. Timing requirements of a design
are used to specify a timing constraints. Internal timing connections like delays through logic, LUTs and between flip-flops or
registers are influenced by these constraints. Area constraints maps wide range of resources in an ASIC. Location constraints
describes location of an element with respect to specific or relative designs within ASIC. Constraints used in our design is shown
in the figure 6.
Figure 6. Constraints used to optimize design Table 2 - Synthesis Result for AES
B. Back End Design
The gate level netlist is mapped to a complete physical geometric representation in the back end design. The first step
involves floor-planning where we place various blocks and I/O pads across the core design area based on the constraints given.
Then physical elements are placed within the core area ,tool may place the cells close to each other or at a far distance to help
meet timing requirements After placing all the elements, clock tree synthesis and detailed routing is done to connect all of the
elements together and also to supply voltage. All the above process is shown in Figure 7. After this phase, a requirement arises to
complete simulation to ensure the layout phase is properly done.
Parameter Before Synthesis After Synthesis
Gates 21829 16559
Area 841091 sq. microns 95291sq. microns
Leakage Power 1662527 nW 355483 nW
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7. (i) Floor Planning (ii) Placement (iii) Clock Tree Synthesis (iv) Routing
Figure 7. Backend design
GDSII (GDS2) file is produced as the end result of the Layout, it i used by the foundry to fabricate the silicon. The layout
should be done according to the silicon foundry design rules.
V. CONCLUSION
In this paper, Speech data obtained through MATLAB has been encrypted and decrypted successfully using AES
algorithm in verilog programming environment. Decrypted speech is recognised using cross correlation technique. AES has never
been cracked and is considered most secure against any kind of brute force attacks. In ASIC designing, the constraints given for
synthesis have reduced gates, area and leakage power by 24%,88% and 78% respectively, as described in table 2.So we need
comparatively lesser amount of resources to implement the design, which makes the design smaller, faster as well as energy
efficient. Layout of AES design is also developed in Backend design. In future we wish to develop more accurate speech
recognition system and further optimization can be done for minimizing the required area, gates and power on ASIC for high end
applications.
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Impact Factor : 3.468
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