Kyeong Soo Kim, Invited talk, 2016 International Conference on Internet of Things and 5G Mobile Technologies (2016 ICIOT-5GMT), Guangzhou University, Guangzhou, Nov. 27-28, 2016.
Accelerating Dynamic Time Warping Subsequence Search with GPUDavide Nardone
Many time series data mining problems require
subsequence similarity search as a subroutine. While this can
be performed with any distance measure, and dozens of
distance measures have been proposed in the last decade, there
is increasing evidence that Dynamic Time Warping (DTW) is
the best measure across a wide range of domains. Given
DTW’s usefulness and ubiquity, there has been a large
community-wide effort to mitigate its relative lethargy.
Proposed speedup techniques include early abandoning
strategies, lower-bound based pruning, indexing and
embedding. In this work we argue that we are now close to
exhausting all possible speedup from software, and that we
must turn to hardware-based solutions if we are to tackle the
many problems that are currently untenable even with stateof-
the-art algorithms running on high-end desktops. With this
motivation, we investigate both GPU (Graphics Processing
Unit) and FPGA (Field Programmable Gate Array) based
acceleration of subsequence similarity search under the DTW
measure. As we shall show, our novel algorithms allow GPUs,
which are typically bundled with standard desktops, to achieve
two orders of magnitude speedup. For problem domains which
require even greater scale up, we show that FPGAs costing just
a few thousand dollars can be used to produce four orders of
magnitude speedup. We conduct detailed case studies on the
classification of astronomical observations and similarity
search in commercial agriculture, and demonstrate that our
ideas allow us to tackle problems that would be simply
untenable otherwise.
Ajay Kumar.Ph.D Research scholar at National Institute of Technology my mail id:-- ajaymodaliger@gmail.com
In this presentation slide i have Explained how to reducing Computational time complexity of Discrete Fourier transform(DFT) from O(n^2 ) to nlogn through Radix-2 .FFT Algorithm in this work i have also introduced how we can use Radix-2 FFT in encrypted signal processing application by considering homomarphic properties(RSA) of Paillier cryptosystem.
Digital Signal Processing[ECEG-3171]-Ch1_L05Rediet Moges
This Digital Signal Processing Lecture material is the property of the author (Rediet M.) . It is not for publication,nor is it to be sold or reproduced.
#Africa#Ethiopia
Accelerating Dynamic Time Warping Subsequence Search with GPUDavide Nardone
Many time series data mining problems require
subsequence similarity search as a subroutine. While this can
be performed with any distance measure, and dozens of
distance measures have been proposed in the last decade, there
is increasing evidence that Dynamic Time Warping (DTW) is
the best measure across a wide range of domains. Given
DTW’s usefulness and ubiquity, there has been a large
community-wide effort to mitigate its relative lethargy.
Proposed speedup techniques include early abandoning
strategies, lower-bound based pruning, indexing and
embedding. In this work we argue that we are now close to
exhausting all possible speedup from software, and that we
must turn to hardware-based solutions if we are to tackle the
many problems that are currently untenable even with stateof-
the-art algorithms running on high-end desktops. With this
motivation, we investigate both GPU (Graphics Processing
Unit) and FPGA (Field Programmable Gate Array) based
acceleration of subsequence similarity search under the DTW
measure. As we shall show, our novel algorithms allow GPUs,
which are typically bundled with standard desktops, to achieve
two orders of magnitude speedup. For problem domains which
require even greater scale up, we show that FPGAs costing just
a few thousand dollars can be used to produce four orders of
magnitude speedup. We conduct detailed case studies on the
classification of astronomical observations and similarity
search in commercial agriculture, and demonstrate that our
ideas allow us to tackle problems that would be simply
untenable otherwise.
Ajay Kumar.Ph.D Research scholar at National Institute of Technology my mail id:-- ajaymodaliger@gmail.com
In this presentation slide i have Explained how to reducing Computational time complexity of Discrete Fourier transform(DFT) from O(n^2 ) to nlogn through Radix-2 .FFT Algorithm in this work i have also introduced how we can use Radix-2 FFT in encrypted signal processing application by considering homomarphic properties(RSA) of Paillier cryptosystem.
Digital Signal Processing[ECEG-3171]-Ch1_L05Rediet Moges
This Digital Signal Processing Lecture material is the property of the author (Rediet M.) . It is not for publication,nor is it to be sold or reproduced.
#Africa#Ethiopia
Digital Signal Processing[ECEG-3171]-Ch1_L03Rediet Moges
This Digital Signal Processing Lecture material is the property of the author (Rediet M.) . It is not for publication,nor is it to be sold or reproduced.
#Africa#Ethiopia
Radio Signal Classification with Deep Neural NetworksKachi Odoemene
6th place solution to 2018 Army Signal Classification Challenge.
Radio Signal Modulation Recognition.
Competition hosted by Army Rapid Capabilities Office and MITRE.
Digital Signal Processing[ECEG-3171]-Ch1_L04Rediet Moges
This Digital Signal Processing Lecture material is the property of the author (Rediet M.) . It is not for publication,nor is it to be sold or reproduced.
#Africa#Ethiopia
Cyclostationary analysis of polytime coded signals for lpi radarseSAT Journals
Abstract In Radars, an electromagnetic waveform will be sent, and an echo of the same signal will be received by the receiver. From this received signal, by extracting various parameters such as round trip delay, doppler frequency it is possible to find distance, speed, altitude, etc. However, nowadays as the technology increases, intruders are intercepting transmitted signal as it reaches them, and they will be extracting the characteristics and trying to modify them. So there is a need to develop a system whose signal cannot be identified by no cooperative intercept receivers. That is why LPI radars came into existence. In this paper a brief discussion on LPI radar and its modulation (Polytime code (PT1)), detection (Cyclostationary (DFSM & FAM) techniques such as DFSM, FAM are presented and compared with respect to computational complexity.
Keywords—LPI Radar, Polytime codes, Cyclostationary DFSM, and FAM
Digital Signal Processing[ECEG-3171]-Ch1_L06Rediet Moges
This Digital Signal Processing Lecture material is the property of the author (Rediet M.) . It is not for publication,nor is it to be sold or reproduced.
#Africa#Ethiopia
The discrete Fourier transform has many applications in science and engineering. For example, it is often used in digital signal processing applications such as voice recognition and image processing.
Area efficient parallel LFSR for cyclic redundancy check IJECEIAES
Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.
Kyeong Soo Kim, "Energy-efficient time synchronization in wireless sensor networks," Invited talk, 2019 Distinguished Lecture and International Interdisciplinary Workshop, Chungnam National University (CNU), Daejeon, Korea, August 5-9, 2019.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Digital Signal Processing[ECEG-3171]-Ch1_L03Rediet Moges
This Digital Signal Processing Lecture material is the property of the author (Rediet M.) . It is not for publication,nor is it to be sold or reproduced.
#Africa#Ethiopia
Radio Signal Classification with Deep Neural NetworksKachi Odoemene
6th place solution to 2018 Army Signal Classification Challenge.
Radio Signal Modulation Recognition.
Competition hosted by Army Rapid Capabilities Office and MITRE.
Digital Signal Processing[ECEG-3171]-Ch1_L04Rediet Moges
This Digital Signal Processing Lecture material is the property of the author (Rediet M.) . It is not for publication,nor is it to be sold or reproduced.
#Africa#Ethiopia
Cyclostationary analysis of polytime coded signals for lpi radarseSAT Journals
Abstract In Radars, an electromagnetic waveform will be sent, and an echo of the same signal will be received by the receiver. From this received signal, by extracting various parameters such as round trip delay, doppler frequency it is possible to find distance, speed, altitude, etc. However, nowadays as the technology increases, intruders are intercepting transmitted signal as it reaches them, and they will be extracting the characteristics and trying to modify them. So there is a need to develop a system whose signal cannot be identified by no cooperative intercept receivers. That is why LPI radars came into existence. In this paper a brief discussion on LPI radar and its modulation (Polytime code (PT1)), detection (Cyclostationary (DFSM & FAM) techniques such as DFSM, FAM are presented and compared with respect to computational complexity.
Keywords—LPI Radar, Polytime codes, Cyclostationary DFSM, and FAM
Digital Signal Processing[ECEG-3171]-Ch1_L06Rediet Moges
This Digital Signal Processing Lecture material is the property of the author (Rediet M.) . It is not for publication,nor is it to be sold or reproduced.
#Africa#Ethiopia
The discrete Fourier transform has many applications in science and engineering. For example, it is often used in digital signal processing applications such as voice recognition and image processing.
Area efficient parallel LFSR for cyclic redundancy check IJECEIAES
Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.
Kyeong Soo Kim, "Energy-efficient time synchronization in wireless sensor networks," Invited talk, 2019 Distinguished Lecture and International Interdisciplinary Workshop, Chungnam National University (CNU), Daejeon, Korea, August 5-9, 2019.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Kyeong Soo Kim, "Clock skew compensation algorithm immune to floating-point precision loss," Invited talk, to be delivered at 2022 International Workshop on Mathematics and Its Applications, Chungnam National University (CNU), Daejoen, Korea, August 4-5, 2022.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design and analysis of dual-mode numerically controlled oscillators based co...IJECEIAES
In this paper, the design and analysis of dual-mode numerically controlled oscillators (NCO) based controlled oscillator frequency Modulation is implemented. Initially, input is given to the analog to digital converter (ADC) converter. This will change the input from analog to digital converter. After that, the pulse skipping mode (PSM) logic and proportional integral (PI) are applied to the converted data. After applying PSM logic, data is directly transferred to the connection block. The proportional and integral block will transfer the data will be decoded using the decoder. After decoding the values, it is saved using a modulo accumulator. After that, it is converted from one hot residue (OHR) to binary converter. The converted data is saved in the register. Now both data will pass through the gate driver circuit and output will be obtained finally. From simulation results, it can observe that the usage of metal oxide semiconductor field effect transistors (MOSFETs) and total nodes are very less in dual-mode NCO-based controlled oscillator frequency modulation.
Frequency domain behavior of S-parameters piecewise-linear fitting in a digit...Piero Belforte
This paper describes PWLFIT+, an extension to the frequency domain ofPWLFIT, a new paradigm in time-domain macromodel ing for linear multiportsystems, based on a piecewise-linea r (PWL) behavioral representation of the S-parameters step response.
An identification of the tolerable time-interleaved analog-todigital convert...IJECEIAES
High-speed Terahertz communication systems has recently employed orthogonal frequency division multiplexing approach as it provides high spectral efficiency and avoids inter-symbol interference caused by dispersive channels. Such high-speed systems require extremely high-sampling time-interleaved analog-to-digital converters at the receiver. However, timing mismatch of time-interleaved analog-to-digital converters significantly causes system performance degradation. In this paper, to avoid such performance degradation induced by timing mismatch, we theoretically determine maximum tolerable mismatch levels for orthogonal frequency division multiplexing communication systems. To obtain these levels, we first propose an analytical method to derive the bit error rate formula for quadrature and pulse amplitude modulations in Rayleigh fading channels, assuming binary reflected gray code (BRGC) mapping. Further, from the derived bit error rate (BER) expressions, we reveal a threshold of timing mismatch level for which error floors produced by the mismatch will be smaller than a given BER. Simulation results demonstrate that if we preserve mismatch level smaller than 25% of this obtained threshold, the BER performance degradation is smaller than 0.5 dB as compared to the case without timing mismatch.
Osc mac duty cycle with multi helpers ct mode wi-lem technology in wireless s...ijwmn
Recently, Wireless Sensor Networks (WSNs) grow to be one of the dominant technology trends; new needs
are continuously emerging and demanding more complex constraints in a duty cycle, such as extend the life
time communication . The MAC layer plays a crucial role in these networks; it controls the communication
module and manages the medium sharing. In this work we use OSC-MAC tackles combining with the
performance of cooperative transmission (CT) in multi-hop WSN and the Wi-Lem technology
computer networks module 1 . fundamentals of networking and data communicationNishaJaiswal34
this pdf gives you information regarding fundamentals of networks and data communication . here various network topologies are disscused such as star topolgy, bus topology, tree topology etc. various network architecture are discussed such as client server architecture. it explains different models such as TCP/IP model. It explains the different layers of these models such as Application Layer:
The top layer in the TCP/IP model.
It deals with high-level protocols used for communication between applications, such as HTTP for web browsing, SMTP for email, FTP for file transfer, etc.
This layer is where user processes and applications interact with the network. Data is formatted, encrypted, and prepared for transmission here.Transport Layer:
The second layer in the TCP/IP model.
Responsible for end-to-end communication and ensures that data is delivered reliably and error-free.
Two main protocols operate at this layer: TCP and UDP.
TCP (Transmission Control Protocol): Provides reliable, connection-oriented communication with features such as error checking, sequencing, and flow control. Suitable for applications that require data integrity, such as web browsing, email, file transfer, etc.
UDP (User Datagram Protocol): Provides connectionless communication without reliability guarantees. Suitable for applications where speed and efficiency are more critical than data integrity, such as streaming media, online gaming, VoIP, etc.
Internet Layer:
The third layer in the TCP/IP model.
Responsible for addressing, routing, and packaging data for transmission over the network.
Uses Internet Protocol (IP) for logical addressing of devices (IPv4 and IPv6).
This layer enables packets to be routed across multiple networks to reach their destination.
Link Layer (also known as Network Access Layer):
The bottom layer in the TCP/IP model.
Deals with the physical transmission of data over the network medium.
It encompasses protocols and hardware components (e.g., Ethernet, Wi-Fi, PPP) that define how data is framed, addressed, transmitted, and received within a local network.
This layer is responsible for establishing and maintaining direct communication between devices on the same local network segment.
The TCP/IP model is widely used as the basis for the design and implementation of the Internet and many other networks. It provides a flexible and scalable framework for building complex network architectures and enables interoperability among different network devices and technologies. it also explains ethernet standards.Ethernet is a family of networking technologies commonly used in local area networks (LANs) to connect devices within a limited geographical area such as an office, campus, or home. Over the years, several Ethernet standards have been developed, each specifying different aspects of network communication including data rates, media types, and physical characteristics. Here are some of the key Ethernet standards:
Ethernet (IEEE 802.3):
thankyou
An Efficient Construction of Online Testable Circuits using Reversible Logic ...ijsrd.com
The vital for many safety critical applications is the testable fault tolerant system. Due to its less heat dissipating characteristics, the reversible logic gaining interest in the recent times. Any Boolean logic function can be implemented using reversible gates. The credential part of the paper proposes a technique to convert any reversible logic gate to a testable gate that is also reversible. The resultant reversible testable gate can detect online any single bit errors that include Single Stuck Faults and Single Event Upsets S. Karp et.al. The proposed technique is illustrated using an example that converts a reversible decoder circuit to an online testable reversible decoder circuit.
A Review: Compensation of Mismatches in Time Interleaved Analog to Digital Co...IJERA Editor
The execution of today's correspondence frameworks is exceedingly subject to the utilized Analog-to-Digital converters (ADCs), and with a specific end goal to give more flexibility and exactness to the developing correspondence innovations, superior-ADCs are needed. In this respect, the time-interleaved operation of an exhibit of ADCs (TI-ADC) might be a sensible result. A TI-ADC can build its throughput by utilizing M channel ADCs or sub converters in parallel and examining the data motion in a period-interleaved way. In any case, the execution of a TI-ADC gravely suffers from the bungles around the channel ADCs. In this paper we survey the advancement in the configuration of low-intricacy advanced remedy structures and calculations for time-interleaved ADCs in the course of the most recent five years. We devise a discrete-time model, state the outline issue, and finally infer the calculations and structures. Specifically, we examine proficient calculations to outline time-differing remedy filters and additionally iterative structures using polynomial based filters. Thusly, the remuneration structure may be utilized to repay time-differing recurrence reaction befuddles in time-interleaved ADCs, and in addition to remake uniform examples from nonuniformly tested indicators. We examine the recompense structure, research its execution, and exhibit requisition zones of the structure through various illustrations. At long last, we give a standpoint to future examination questions.
Analysis of Space Time Codes Using Modulation TechniquesIOSR Journals
Abstract: In this Paper, Analysis of channel codes for improving the data rate and reliability of communication over fading channels using multiple transmit antennas has been considered. The codes, namely ’Space Time Codes’ render full diversity and amend coding gain. Performance criteria for designing such codes, under this assumption that the fading is slow and nonselective frequency, is also analysed. Under this research, Study of Frame Error Rate(FER) and outage capacity is compared for different no. Of transmit and receive antennas as well as for different modulation techniques. According to theoretical results FER decreases with increasing SNR and No. Of receiving antennas. Numerical and practical result shows that FER decreases with increasing SNR and no. Of receiving antennas. Keywords: Space time Block Codes ,Space time trellis Codes,Frame Error Rate(FER),Outage capacity,Pairwise Error Probability
Similar to Energy-Efficient Time Synchronization Achieving Nanosecond Accuracy in Wireless Networks (20)
Kyeong Soo Kim, "Theoretical and Practical Bounds on the Initial Value of Skew-Compensated Clock for Clock Skew Compensation Algorithm Immune to Floating-Point Precision Loss (Extended Version)," Special lecture, Department of Mathematics, Chungnam National University (CNU), Daejoen, Korea, January 25, 2023.
Kyeong Soo Kim, "Theoretical and practical bounds on the initial value of skew-compensated clock for clock skew compensation algorithm immune to floating-point precision loss," Invited talk, 2023 International Conference
for Mathematics and Its Applications, Chungnam National University (CNU), Daejoen, Korea, Jan. 16-18, 2023.
Kyeong Soo Kim, "Atomic scheduling of appliance energy consumption in residential smart grid," Invited talk, CNU International Workshop on Industrial Mathematics, Chungnam National University (CNU), Daejeon, Korea, Oct. 7, 2016.
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Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
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A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
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This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
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When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
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Energy-Efficient Time Synchronization Achieving Nanosecond Accuracy in Wireless Networks
1. Energy-Efficient Time Synchronization
Achieving Nanosecond Accuracy
in Wireless Networks
Kyeong Soo (Joseph) Kim
(With S. Lee and E. G. Lim@XJTLU)
Department of Electrical and Electronic Engineering
Xi’an Jiaotong-Liverpool University
2016 ICIOT-5GMT
Guangzhou University
27-28 November, 2016
1 / 49
2.
3. Outline
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Simulation Results
Next Steps: Extension to Multi-Hop Time Synchronization
Conclusions
3 / 49
4. Next . . .
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Hardware and Logical Clock Models
Effect of Clock Skew on Measurement Time Estimation
Asynchronous Source Clock Frequency Recovery at
Sensor Nodes: One-Way Clock Skew Estimation
Simulation Results
Performance of One-Way Clock Skew Estimation
Performance of Measurement Time Estimation and
Energy Efficiency
Effect of Bundling of Measurement Data
Next Steps: Extension to Multi-Hop Time Synchronization
Conclusions
4 / 49
6. Head Node
A base station that serves as a
gateway between wired and
wireless networks.
A center for fusion of data
from distributed sensors.
Equipped with a powerful
processor and supplied power
from outlet.
6 / 49
7. Head Node
A base station that serves as a
gateway between wired and
wireless networks.
A center for fusion of data
from distributed sensors.
Equipped with a powerful
processor and supplied power
from outlet.
6 / 49
8. Head Node
A base station that serves as a
gateway between wired and
wireless networks.
A center for fusion of data
from distributed sensors.
Equipped with a powerful
processor and supplied power
from outlet.
6 / 49
9. Sensor Node
Measuring data and/or detect
events with sensors and
connected to a WSN only
through wireless channels.
Limited in processing and
battery-powered.
7 / 49
10. Sensor Node
Measuring data and/or detect
events with sensors and
connected to a WSN only
through wireless channels.
Limited in processing and
battery-powered.
7 / 49
11. Design Goals
Achieving sub-microsecond time synchronization
accuracy
Through propagation delay compensation.
With higher energy efficiency at battery-powered
sensor nodes
Minimize the number of packet transmissions and the
amount of computation at sensor nodes.
8 / 49
12. Next . . .
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Hardware and Logical Clock Models
Effect of Clock Skew on Measurement Time Estimation
Asynchronous Source Clock Frequency Recovery at
Sensor Nodes: One-Way Clock Skew Estimation
Simulation Results
Performance of One-Way Clock Skew Estimation
Performance of Measurement Time Estimation and
Energy Efficiency
Effect of Bundling of Measurement Data
Next Steps: Extension to Multi-Hop Time Synchronization
Conclusions
9 / 49
13. Effects of Time and Space
The effects of time and space are so closely related that
they cannot be easily separated from each other as in the
following examples:
Synchronization and localization accuracies.
In time-based localization.
e.g. Time of arrival (TOA).
Clock offset and propagation delay.
In one-way synchronization.
e.g. Flooding time synchronization protocol (FTSP).
10 / 49
14. Synchronization and Localization Accuracies
Accuracies
1 ms ↔ 300 km
1 µs ↔ 300 m
1 ns ↔ 30 cm
1 ps ↔ 0.3 mm
Time-based localization schemes
Time of arrival (TOA)
Time difference of arrival (TDOA)
A special variation of TDOA with virtual anchors does
not require synchronization among devices.
⇒ See the next slide.
11 / 49
15. TDOA with Virtual Anchors 1
Anchor
Agent
Virtual
Anchors
1
E. Leitinger et al., IEEE J. Sel. Areas Commun., vol. 33, no. 11, pp.
2313–2328, Nov. 2015.
12 / 49
16. Clock Offset and Propagation Delay
Can the receiver distinguish between the following two
cases if θ = d?
Packet with
Timestamp T vs. Packet with
Timestamp T
TX
RX
TX
RX
• : Clock offset
• : Propagation delay
Answer is “No”.
Two-way message exchanges needed for delay
compensation.
13 / 49
17. Next . . .
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Hardware and Logical Clock Models
Effect of Clock Skew on Measurement Time Estimation
Asynchronous Source Clock Frequency Recovery at
Sensor Nodes: One-Way Clock Skew Estimation
Simulation Results
Performance of One-Way Clock Skew Estimation
Performance of Measurement Time Estimation and
Energy Efficiency
Effect of Bundling of Measurement Data
Next Steps: Extension to Multi-Hop Time Synchronization
Conclusions
14 / 49
18. Conventional Two-Way Message Exchanges I
Master
sHead Node)
Slave
sSensor Node)Measurement
Interval of Time Sync. si.e., 2-Way Message Exchange)
……
Report
Request
Response
Report
Measurement
T1
T2
T4
T3
Sensor nodes transmit “Request” messages for
synchronization.
In addition to measurement data packets.
15 / 49
19. Conventional Two-Way Message Exchanges
II
The sensor node can estimate its clock offset w.r.t. the
head node and synchronize its clock to that of the
head node:
Clock offset: ˆθ =
(T2 − T1) − (T4 − T3)
2
.
Propagation delay: ˆd =
(T2 − T1) + (T4 − T3)
2
.
16 / 49
20. Reverse Two-Way Message Exchanges I
Master
sHead Node)
Slave
sSensor Node)
Beacon/
Request
sMeasurement)
Report/
Response
T1 T4
T3T2
d
tm
Sensor nodes do not transmit any other messages
except “Request/Response” messages.
If there are no measurement data, sensor nodes just
receive messages.
17 / 49
21. Reverse Two-Way Message Exchanges II
The head node can estimate the clock offset of the
sensor node, but the sensor node cannot.
As a result, the information of all sensor node clocks
is centrally managed at the head node.
“Response” (synchronization) and “Report”
(measurement data) messages can be combined to
save the number of message transmissions from the
sensor node.
Optionally measurement data and corresponding
timestamps can be bundled together in a
“Report/Response” message when there are no strict
timing requirements.
18 / 49
22. Next . . .
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Hardware and Logical Clock Models
Effect of Clock Skew on Measurement Time Estimation
Asynchronous Source Clock Frequency Recovery at
Sensor Nodes: One-Way Clock Skew Estimation
Simulation Results
Next Steps: Extension to Multi-Hop Time Synchronization
19 / 49
23. Hardware Clock Model
Time Ti of the hardware clock of the ith sensor node at the
reference time t is modeled as a first-order affine function:
Ti(t) = (1 + i)t + θi,
where
(1 + i) ∈ R+: Clock frequency ratio.2
θi ∈ R: Clock offset.
2
i is called a clock skew in the literature.
20 / 49
24. Logical Clock Model
Time Ti of the logical clock of the ith sensor node at
hardware clock time Ti(t) is modeled as a piecewise linear
function: For tk<t≤tk+1 (k=0, 1, . . .),
Ti Ti(t) = Ti Ti(tk) +
Ti(t) − Ti(tk)
1 + ˆi,k
− ˆθi,k,
where
tk: Reference time when a kth synchronization occurs.
ˆi,k: Estimated clock skew from the kth
synchronization.
ˆθi,k: Estimated clock offset from the kth
synchronization.
21 / 49
25. Next . . .
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Hardware and Logical Clock Models
Effect of Clock Skew on Measurement Time Estimation
Asynchronous Source Clock Frequency Recovery at
Sensor Nodes: One-Way Clock Skew Estimation
Simulation Results
Next Steps: Extension to Multi-Hop Time Synchronization
22 / 49
26. Measurement Time Estimation Error:
Conventional Two-Way Message Exchanges
Master
sHead Node)
Slave
sSensor Node)
Measurement
Request
Response
Report
s1
s2≈s3
s4
d
tm
When Tm d,
∆ˆtConv.
m ∼ Tm × ∆ˆi,
where ∆ˆi is the clock skew estimation error.
23 / 49
27. Measurement Time Estimation Error:
Reverse Two-Way Message Exchanges
Master
sHead Node)
Slave
sSensor Node)
Beacon/
Request
sMeasurement)
Report/
Response
T1 T4
T3T2
d
tm
When Tm d,
∆ˆtRev.
m ∼
Tm
2
× ∆ˆi.
24 / 49
28. Next . . .
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Hardware and Logical Clock Models
Effect of Clock Skew on Measurement Time Estimation
Asynchronous Source Clock Frequency Recovery at
Sensor Nodes: One-Way Clock Skew Estimation
Simulation Results
Next Steps: Extension to Multi-Hop Time Synchronization
25 / 49
29. Message Departure and Arrival Times
Let td(k) (k=0, 1, . . .) be the reference time for the kth
message’s departure from the head node.
td(k) also denotes the value of the timestamp carried
by the kth message.
Then the arrival time of the kth message with respect
to the ith sensor node’s hardware clock is given by
ta,i(k) = Ti (td(k)) + d(k) = (1 + i)td(k) + θi + d(k),
where
d(k): One-way propagation delay in terms of the ith
sensor node’s hardware clock.
26 / 49
30. Joint Maximum Likelihood Estimators
For a white Gaussian delay d(k) with known mean d and
variance σ2
,
ˆθML
i (k) =
t2
d
· ta,i − td · tdta,i
t2
d
− td
2
− d,
ˆRML
i (k) =
tdta,i − td · ta,i
t2
d
− td
2
,
where
x k
j=0
x(j)
k
,
xy k
j=0
x(j)y(j)
k
.
27 / 49
31. Regression through The Origin (RTO) Model
The problem of asynchronous source clock frequency
recovery (SCFR) can be formulated as a linear RTO model
as follows: For k = 1, 2, . . .,
˜ta,i(k) = (1 + i)˜td(k) + ˜d(k),
where
˜ta,i(k) ta,i(k)−ta,i(0),
˜td(k) td(k)−td(0),
˜d(k) d(k)−d(0).
28 / 49
32. Cumulative Ratio (CR) Estimator
ˆRCR
i (k) =
˜ta,i(k)
˜td(k)
= Ri +
˜d(k)
˜ts(k)
,
where
Ri: Ratio of the ith sensor node hardware clock
frequency to that of the reference clock (i.e., 1+ i).
29 / 49
33. Next . . .
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Hardware and Logical Clock Models
Effect of Clock Skew on Measurement Time Estimation
Asynchronous Source Clock Frequency Recovery at
Sensor Nodes: One-Way Clock Skew Estimation
Simulation Results
Performance of One-Way Clock Skew Estimation
Performance of Measurement Time Estimation and
Energy Efficiency
Effect of Bundling of Measurement Data
Next Steps: Extension to Multi-Hop Time Synchronization
Conclusions
30 / 49
34. Next . . .
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Simulation Results
Performance of One-Way Clock Skew Estimation
Performance of Measurement Time Estimation and
Energy Efficiency
Effect of Bundling of Measurement Data
Next Steps: Extension to Multi-Hop Time Synchronization
31 / 49
35. Estimated Clock Skews with Gaussian Delays: σ=1 ns
5 10 15 20 25 30 35 40 45 50
Number of Messages
10−21
10−20
10−19
10−18
10−17
10−16
10−15
MSE
RLS
CR
Joint MLE
GMLLE (Two-Way)
LB for CR
CRLB for Joint MLE
LB for GMLLE
32 / 49
36. Estimated Clock Skews with Gaussian Delays: σ=1 µs
5 10 15 20 25 30 35 40 45 50
Number of Messages
10−15
10−14
10−13
10−12
10−11
10−10
10−9
MSE
RLS
CR
Joint MLE
GMLLE (Two-Way)
LB for CR
CRLB for Joint MLE
LB for GMLLE
33 / 49
38. Estimated Clock Skews with AR(1) Delays: σ=1 ms
5 10 15 20 25 30 35 40 45 50
Number of Messages
10−8
10−7
10−6
10−5
10−4
MSE
RLS
CR
Joint MLE
GMLLE (Two-Way)
35 / 49
39. Next . . .
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Simulation Results
Performance of One-Way Clock Skew Estimation
Performance of Measurement Time Estimation and
Energy Efficiency
Effect of Bundling of Measurement Data
Next Steps: Extension to Multi-Hop Time Synchronization
36 / 49
40. Estimated Frequency Ratio (Sensor Node) and
Measurement Time (Head Node): SI=100 s
-4E-11
-2E-11
0E+00
2E-11
4E-11
FrequencyDifference[ppm]
Proposed (w/ CR)
Two-Way (w/ GMLLE)
0 500 1000 1500 2000 2500 3000 3500
Time [s]
-1E-02
-8E-03
-6E-03
-4E-03
-2E-03
0E+00
2E-03
4E-03
MeasurementTimeError[s]
Proposed (w/ CR)
Two-Way (w/ GMLLE)
Two-Way
37 / 49
41. Estimated Frequency Ratio (Sensor Node) and
Measurement Time (Head Node): SI=1 s
-4E-11
-2E-11
0E+00
2E-11
4E-11
FrequencyDifference[ppm]
Proposed (w/ CR)
Two-Way (w/ GMLLE)
0 500 1000 1500 2000 2500 3000 3500
Time [s]
-1E-04
-8E-05
-6E-05
-4E-05
-2E-05
0E+00
2E-05
4E-05
MeasurementTimeError[s]
Proposed (w/ CR)
Two-Way (w/ GMLLE)
Two-Way
38 / 49
42. Estimated Frequency Ratio (Sensor Node) and
Measurement Time (Head Node): SI=1 ms
-4E-11
-2E-11
0E+00
2E-11
4E-11
FrequencyDifference[ppm]
Proposed (w/ CR)
Two-Way (w/ GMLLE)
0 500 1000 1500 2000 2500 3000 3500
Time [s]
-1E-06
-8E-07
-6E-07
-4E-07
-2E-07
0E+00
2E-07
4E-07
MeasurementTimeError[s]
Proposed (w/ CR)
Two-Way (w/ GMLLE)
Two-Way
39 / 49
43. Effect of SI on Time Synchronization and
Energy Consumption4
Synchronization Skew Estimation Measurement Time
NTX NRX
Scheme MSE Estimation MSE
Proposed
SI=100 s 8.8811E-25 5.8990E-19 100 36
SI=1 s 9.1748E-25 5.4210E-19 100 3600
SI=10 ms 1.0887E-24 4.7684E-19 100 360100
Two-Way with GMLLE
SI=100 s 1.9021E-24 4.7784E-19 136 36
SI=1 s 1.7034E-24 6.1452E-19 3700 3600
SI=10 ms 9.0992E-25 4.0485E-19 360100 360000
Two-Way
SI=100 s
N/A
3.4900E-05 136 36
SI=1 s 3.4564E-09 3700 3600
SI=10 ms 3.3638E-13 360100 360000
4
Estimations are for the samples taken after 360 s (i.e., one tenth of
the observation period) to avoid the effect of a transient period.
40 / 49
44. Next . . .
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Simulation Results
Performance of One-Way Clock Skew Estimation
Performance of Measurement Time Estimation and
Energy Efficiency
Effect of Bundling of Measurement Data
Next Steps: Extension to Multi-Hop Time Synchronization
41 / 49
45. Effect of Bundling on Measurement Time Estimation5
0 500 1000 1500 2000 2500 3000 3500
Time [s]
-2.0E-09
-1.0E-09
0.0E+00
1.0E-09
2.0E-09
MeasurementTimeError[s]
NBM=1
NBM=2
NBM=5
NBM=10
5
SI = 1 s.
42 / 49
46. Effect of Bundling on Time Synchronization and
Energy Consumption
Synchronization Scheme
Measurement Time
NTX NRX
Estimation MSE
Proposed
NBM = 1 5.4210E-19 100 3600
NBM = 2 5.1116E-19 50 3600
NBM = 5 3.7504E-19 20 3600
NBM = 10 2.6468E-19 10 3600
In interpreting the results, the following should be
taken into account:
The bundling increases the length of message
payload.
The increased message payload also can affect the
frame errors and the number of retransmissions.
43 / 49
47. Next . . .
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Hardware and Logical Clock Models
Effect of Clock Skew on Measurement Time Estimation
Asynchronous Source Clock Frequency Recovery at
Sensor Nodes: One-Way Clock Skew Estimation
Simulation Results
Performance of One-Way Clock Skew Estimation
Performance of Measurement Time Estimation and
Energy Efficiency
Effect of Bundling of Measurement Data
Next Steps: Extension to Multi-Hop Time Synchronization
Conclusions
44 / 49
49. Challenges and Opportunities
Tradeoff between time-translating and
packet-relaying gateways..
The multi-hop extension should be implemented
together with a routing protocol.
As in LEACH protocol6 and its many variations, the
energy efficiency is also critical in the formation of a
hierarchy and the selection of cluster heads (i.e., the
gateway nodes in the multi-hop extension of the
proposed scheme).
6
W. R. Heinzelman et al., Proc. HICSS’00, Jan. 2000, pp. 1–10.
46 / 49
50. Challenges and Opportunities
Tradeoff between time-translating and
packet-relaying gateways..
The multi-hop extension should be implemented
together with a routing protocol.
As in LEACH protocol6 and its many variations, the
energy efficiency is also critical in the formation of a
hierarchy and the selection of cluster heads (i.e., the
gateway nodes in the multi-hop extension of the
proposed scheme).
6
W. R. Heinzelman et al., Proc. HICSS’00, Jan. 2000, pp. 1–10.
46 / 49
51. Challenges and Opportunities
Tradeoff between time-translating and
packet-relaying gateways..
The multi-hop extension should be implemented
together with a routing protocol.
As in LEACH protocol6 and its many variations, the
energy efficiency is also critical in the formation of a
hierarchy and the selection of cluster heads (i.e., the
gateway nodes in the multi-hop extension of the
proposed scheme).
6
W. R. Heinzelman et al., Proc. HICSS’00, Jan. 2000, pp. 1–10.
46 / 49
53. Next . . .
Introduction
Time and Space in Synchronization
Energy-Efficient Time Synchronization for Asymmetric
Wireless Networks
Hardware and Logical Clock Models
Effect of Clock Skew on Measurement Time Estimation
Asynchronous Source Clock Frequency Recovery at
Sensor Nodes: One-Way Clock Skew Estimation
Simulation Results
Performance of One-Way Clock Skew Estimation
Performance of Measurement Time Estimation and
Energy Efficiency
Effect of Bundling of Measurement Data
Next Steps: Extension to Multi-Hop Time Synchronization
Conclusions
48 / 49
54. Conclusions
Propose an energy-efficient time synchronization
scheme for asymmetric wireless networks achieving
sub-microsecond time synchronization accuracy.
Also, discuss the optional bundling of measurement
data in a “Report/Response” message.
Topics for further study include
Extension to multi-hop synchronization through
packet-relaying or time-translating gateway nodes;
Energy-delay tradeoff and the effect of frame errors
and retransmissions in bundling of measurement
data.
49 / 49
55. Conclusions
Propose an energy-efficient time synchronization
scheme for asymmetric wireless networks achieving
sub-microsecond time synchronization accuracy.
Also, discuss the optional bundling of measurement
data in a “Report/Response” message.
Topics for further study include
Extension to multi-hop synchronization through
packet-relaying or time-translating gateway nodes;
Energy-delay tradeoff and the effect of frame errors
and retransmissions in bundling of measurement
data.
49 / 49
56. Conclusions
Propose an energy-efficient time synchronization
scheme for asymmetric wireless networks achieving
sub-microsecond time synchronization accuracy.
Also, discuss the optional bundling of measurement
data in a “Report/Response” message.
Topics for further study include
Extension to multi-hop synchronization through
packet-relaying or time-translating gateway nodes;
Energy-delay tradeoff and the effect of frame errors
and retransmissions in bundling of measurement
data.
49 / 49
57. Conclusions
Propose an energy-efficient time synchronization
scheme for asymmetric wireless networks achieving
sub-microsecond time synchronization accuracy.
Also, discuss the optional bundling of measurement
data in a “Report/Response” message.
Topics for further study include
Extension to multi-hop synchronization through
packet-relaying or time-translating gateway nodes;
Energy-delay tradeoff and the effect of frame errors
and retransmissions in bundling of measurement
data.
49 / 49
58. Conclusions
Propose an energy-efficient time synchronization
scheme for asymmetric wireless networks achieving
sub-microsecond time synchronization accuracy.
Also, discuss the optional bundling of measurement
data in a “Report/Response” message.
Topics for further study include
Extension to multi-hop synchronization through
packet-relaying or time-translating gateway nodes;
Energy-delay tradeoff and the effect of frame errors
and retransmissions in bundling of measurement
data.
49 / 49