Discussion of solutions for SDI to PCIe that enables up to 4 bi-directional channels of 1080p Video. Including an examination of applications, challenges and benefits associated with implementing PCIe-based systems, and a discussion of a video framework that simplifies hardware design for video systems with a PCIe-based design.
Learn about the new 28-nm Stratix V FPGA family from Altera. Built for bandwidth, this family includes 28-Gbps transceivers, embedded HardCopy blocks, and variable-precision DSP blocks.
Next Generation Campus Switching: Are You ReadyCisco Canada
We will review the latest evolution within the Cisco Catalyst switching product portfolio including the latest Cisco Catalyst 6800 switches and Cisco Instant Access. For more information please visit our website here: http://www.cisco.com/web/CA/index.html
Altera is now shipping our Cyclone® IV FPGAs, the market's lowest cost, lowest power FPGAs, with an integrated 3.125-Gbps transceiver variant. Learn how to meet increasing bandwidth requirements while lowering costs in high-volume applications in this presentation. http://www.altera.com/b/cyclone-iv-fpga-shipping.html
Software Defined Network (SDN) using ASR9000 :: BRKSPG-2722 | San Diego 2015Bruno Teixeira
With the changing paradigm of network programmability using Software Defined Network (SDN), we are seeing new ways for monitoring, scaling and configuring network devices. With new network programability capabilities utilizing NETCONF, OpenFlow, BGP-LS, and PCEP it is vital for network architects and operations engineers to understand how these SDN related technologies can be leveraged to streamline the way we view, design, and operate our networks today. This session introduces these concepts and focuses on the use cases, implementation, and troubleshooting of these technologies on the ASR9000 platform.
Learn about the new 28-nm Stratix V FPGA family from Altera. Built for bandwidth, this family includes 28-Gbps transceivers, embedded HardCopy blocks, and variable-precision DSP blocks.
Next Generation Campus Switching: Are You ReadyCisco Canada
We will review the latest evolution within the Cisco Catalyst switching product portfolio including the latest Cisco Catalyst 6800 switches and Cisco Instant Access. For more information please visit our website here: http://www.cisco.com/web/CA/index.html
Altera is now shipping our Cyclone® IV FPGAs, the market's lowest cost, lowest power FPGAs, with an integrated 3.125-Gbps transceiver variant. Learn how to meet increasing bandwidth requirements while lowering costs in high-volume applications in this presentation. http://www.altera.com/b/cyclone-iv-fpga-shipping.html
Software Defined Network (SDN) using ASR9000 :: BRKSPG-2722 | San Diego 2015Bruno Teixeira
With the changing paradigm of network programmability using Software Defined Network (SDN), we are seeing new ways for monitoring, scaling and configuring network devices. With new network programability capabilities utilizing NETCONF, OpenFlow, BGP-LS, and PCEP it is vital for network architects and operations engineers to understand how these SDN related technologies can be leveraged to streamline the way we view, design, and operate our networks today. This session introduces these concepts and focuses on the use cases, implementation, and troubleshooting of these technologies on the ASR9000 platform.
MIPI DevCon 2020 | Snapshot of MIPI RFFE v3.0 from a System-Architecture Per...MIPI Alliance
Lalan Mishra, vice-chair of the MIPI RFFE Working Group, presents the new features of MIPI RFFE v3.0 to help architecture and design engineers understand how the triggering features in the latest version work together to improve performance and to switch quickly among the various bands and band combinations in a 5G system.
Here is a corporate overview of Spectrum and some of our latest products. It includes our SDR-4000 SDR Radio modem, our RF-4902 rugged, frequency agile RF tuner, our SDR-2010 server-based signal processing platform, and our line of 3u VPX signal processing modems.
DPDK Summit 2015 - Intro - Tim O'DriscollJim St. Leger
DPDK Summit 2015 in San Francisco.
Introductory comments and kick-off by Tim O'Driscoll, Intel.
For additional details and the video recording please visit www.dpdksummit.com.
IGS-10020MT is a fully-managed Gigabit fiber switch usually designed for the industrial network. It features 8 10/100/1000BASE-T copper ports, 2 100/1000/2500BASE-X SFP ports and redundant power system in an IP30 rugged but compact-sized case that can be installed in any difficult environment without space limitation. Within such favorable enclosure, it provides user-friendly yet advanced IPv6/IPv4 management interfaces, abundant L2/L4 switching functions and Layer 3 static routing capability.
Contact us
Tel: +91-7875432180 Email: sales@bbcpl.in
Website: https://bbcpl.in
"Morphology of Modern Data Center Networks: Overview". Dinesh Dutt, Cumulus N...Yandex
Form follows function is a modern architectural principle that has been used to design and understand the workings of organisms and buildings. Computer networks are also an example of this principle. The classical networking topology (or form) inside an enterprise (and data center) has been the access-aggregation-core model that was designed to serve the needs of the applications then vogue in the enterprise. Enter the 21st century: companies like Google and Amazon, and applications based on cloud, big data and web 2.0 are redefining the fundamental morphology of data center networks.
This talk introduces the fundamental form of modern data center networking and discusses how form follows function in this brave new world. The talk will range from the application needs of the modern data center and how they redefine the network requirements to the most common topology in modern data centers to the protocols used and new technologies.
The Pug is a breed of dog with a wrinkly, short-muzzled face, and curled tail. The breed has a fine, glossy coat that comes in a variety of colours, most often fawn or black, and a compact square body with well-developed muscles.
Pugs were brought from China to Europe in the sixteenth century and were popularized in Western Europe by the House of Orange of the Netherlands, and the House of Stuart.In the United Kingdom, in the nineteenth century, Queen Victoria developed a passion for pugs which she passed on to other members of the Royal family. Pugs are known for being sociable and gentle companion dogs.[3] The breed remains popular into the twenty-first century, with some famous celebrity owners. A pug was judged Best in Show at the World Dog Show in 2004.
Donald J. Trump For President, Inc. –– Why Now?
On November 8, 2016, the American People delivered a historic victory and took our country back. This victory was the result of a Movement to put America first, to save the American economy, and to make America once again a shining city on the hill. But our Movement cannot stop now - we still have much work to do.
This is why our Campaign Committee, Donald J. Trump for President, Inc., is still here.
We will provide a beacon for this historic Movement as our lights continue to shine brightly for you - the hardworking patriots who have paid the price for our freedom. While Washington flourished, our American jobs were shipped overseas, our families struggled, and our factories closed - that all ended on January 20, 2017.
This Campaign will be a voice for all Americans, in every city near and far, who support a more prosperous, safe and strong America. That’s why our Campaign cannot stop now - our Movement is just getting started.
Together, we will Make America Great Again!
Cisco Live! :: Deploying SIP Trunks with Cisco Unified Border Element (CUBE/v...Bruno Teixeira
This session will provide an in-depth understanding on how to design and implement SIP Trunks with Cisco's Enterprise SBC and Cisco Unified Border Element (CUBE/vCUBE). It will familiarise participants with CUBE architecture, deployment options, and sizing guidelines. Differences between various CUBE and vCUBE platform options will also be discussed along with certain key elements of CUBE/vCUBE like Interworking, Media Manipulation, SIP Normalisation, Simplified Call Routing, Call Recording Architectures (ORA, NBR and SIPREC), Multi-tenancy and High Availability.
MIPI DevCon 2020 | Snapshot of MIPI RFFE v3.0 from a System-Architecture Per...MIPI Alliance
Lalan Mishra, vice-chair of the MIPI RFFE Working Group, presents the new features of MIPI RFFE v3.0 to help architecture and design engineers understand how the triggering features in the latest version work together to improve performance and to switch quickly among the various bands and band combinations in a 5G system.
Here is a corporate overview of Spectrum and some of our latest products. It includes our SDR-4000 SDR Radio modem, our RF-4902 rugged, frequency agile RF tuner, our SDR-2010 server-based signal processing platform, and our line of 3u VPX signal processing modems.
DPDK Summit 2015 - Intro - Tim O'DriscollJim St. Leger
DPDK Summit 2015 in San Francisco.
Introductory comments and kick-off by Tim O'Driscoll, Intel.
For additional details and the video recording please visit www.dpdksummit.com.
IGS-10020MT is a fully-managed Gigabit fiber switch usually designed for the industrial network. It features 8 10/100/1000BASE-T copper ports, 2 100/1000/2500BASE-X SFP ports and redundant power system in an IP30 rugged but compact-sized case that can be installed in any difficult environment without space limitation. Within such favorable enclosure, it provides user-friendly yet advanced IPv6/IPv4 management interfaces, abundant L2/L4 switching functions and Layer 3 static routing capability.
Contact us
Tel: +91-7875432180 Email: sales@bbcpl.in
Website: https://bbcpl.in
"Morphology of Modern Data Center Networks: Overview". Dinesh Dutt, Cumulus N...Yandex
Form follows function is a modern architectural principle that has been used to design and understand the workings of organisms and buildings. Computer networks are also an example of this principle. The classical networking topology (or form) inside an enterprise (and data center) has been the access-aggregation-core model that was designed to serve the needs of the applications then vogue in the enterprise. Enter the 21st century: companies like Google and Amazon, and applications based on cloud, big data and web 2.0 are redefining the fundamental morphology of data center networks.
This talk introduces the fundamental form of modern data center networking and discusses how form follows function in this brave new world. The talk will range from the application needs of the modern data center and how they redefine the network requirements to the most common topology in modern data centers to the protocols used and new technologies.
The Pug is a breed of dog with a wrinkly, short-muzzled face, and curled tail. The breed has a fine, glossy coat that comes in a variety of colours, most often fawn or black, and a compact square body with well-developed muscles.
Pugs were brought from China to Europe in the sixteenth century and were popularized in Western Europe by the House of Orange of the Netherlands, and the House of Stuart.In the United Kingdom, in the nineteenth century, Queen Victoria developed a passion for pugs which she passed on to other members of the Royal family. Pugs are known for being sociable and gentle companion dogs.[3] The breed remains popular into the twenty-first century, with some famous celebrity owners. A pug was judged Best in Show at the World Dog Show in 2004.
Donald J. Trump For President, Inc. –– Why Now?
On November 8, 2016, the American People delivered a historic victory and took our country back. This victory was the result of a Movement to put America first, to save the American economy, and to make America once again a shining city on the hill. But our Movement cannot stop now - we still have much work to do.
This is why our Campaign Committee, Donald J. Trump for President, Inc., is still here.
We will provide a beacon for this historic Movement as our lights continue to shine brightly for you - the hardworking patriots who have paid the price for our freedom. While Washington flourished, our American jobs were shipped overseas, our families struggled, and our factories closed - that all ended on January 20, 2017.
This Campaign will be a voice for all Americans, in every city near and far, who support a more prosperous, safe and strong America. That’s why our Campaign cannot stop now - our Movement is just getting started.
Together, we will Make America Great Again!
Cisco Live! :: Deploying SIP Trunks with Cisco Unified Border Element (CUBE/v...Bruno Teixeira
This session will provide an in-depth understanding on how to design and implement SIP Trunks with Cisco's Enterprise SBC and Cisco Unified Border Element (CUBE/vCUBE). It will familiarise participants with CUBE architecture, deployment options, and sizing guidelines. Differences between various CUBE and vCUBE platform options will also be discussed along with certain key elements of CUBE/vCUBE like Interworking, Media Manipulation, SIP Normalisation, Simplified Call Routing, Call Recording Architectures (ORA, NBR and SIPREC), Multi-tenancy and High Availability.
№ 1. Ретроспективный анализ и тренды логистики в Украине и мире 2015Alexandra Gorbenko
ЗУСТРІЧ № 1. Головні тренди в сфері логістика - продажі - маркетинг в 2015 році в Україні та світі.
*Ретроспективний аналіз і визначні тренди просування товарів на ринках В2В та В2С: кількісний та якісний стан галузі, топ-10 найважливіших напрямів для розвитку бізнесу, нові вимоги ринку до кваліфікації співробітників
* Аналіз професій, що обслуговують сферу просування товарів. Очікування роботодавців до менеджерів (управителів): огляд функціональних обов'язків викладених у інструкціях згідно до класифікатора професій та ринкових вимог. Огляд заробітних плат спеціалістів за напрямками бізнесу в Україні та світі
* Перелік навчальних програм за напрямками в Україні та світі: відкриті та закриті заходи, "школи", курси, тренінги. Вартість та тривалість навчання. Література та кейси для самостійного навчання: основний перелік перевірених посилань за напрямками: закупівля, збут, зберігання, перевезення, просування товарів на ринку, митне оформлення.
Menadex is the leading Premium Advertising Marketplace bringing the Middle East and North Africa Region (MENA) internet audiences to the most demanding and smart programmatic media buyers across the world.
Menadex is the leading Premium Advertising Marketplace bringing the Middle East and North Africa Region (MENA) internet audiences to the most demanding and smart programmatic media buyers across the world.
Baromètre Mappy/BVA du Web-to-Store - Octobre 2015Sébastien Maimon
Le baromètre #webtostore édité par Mappy/BVA offre une vision précise de la mutation qui s'exerce dans le commerce de détail.
Le smartphone a révolutionné le secteur de la distribution en offrant aux consommateurs toutes les informations nécessaires pour effectuer ses achats. Son déploiement à l’échelle internationale engendre de nouveaux modes de consommations dont les bénéfices technologiques donnent au consommateurs les super pouvoirs : transparence sur les prix, le lieu de fabrication, ROPO (Research Online Purchase OffLine), géo-localisation des revendeurs, réseaux sociaux, full digital, Full Store
, Showrooming, comparateurs de prix, applications communautaires, etc.
Cette nouvelle règle du jeu impose aux détaillants et aux marques une transformation digitale des modes de commercialisations. Le développement de stratégies omnicanal est désormais incontournable pour rester dans la partie, car penser "écosystème de marque" ouvre de nouvelles perspectives de croissance.
Proposer au consommateur différents canaux d’information, c’est lui donner le choix de la fréquence la plus adaptée à son mode de vie. Créer la conversation en captant l'attention du consommateur est un enjeu aux retombées colossales.
Encore faut-il franchir le pas et s'affranchir de ses habitudes de commercialisation.
In this Case Study read about Mistral’s expertise in designing a flexible and easily upgrade-able Video recording & processing solution with high resolution and frame rate for defense and aerospace applications.
Surf Communication Solutions provides of MoP (Media over Packet) Triple Play (Voice, Video, and Modem/Fax/Data) conversion solutions to communication equipment manufacturers. These solutions are provided in various integration levels: DSP software ; PTMC boards; DSP hardware/software; and PCI boards. http://www.surf-com.com
AP-VAC150 Video Doorphone for Unmmaned FacilitiesGuisun Han
Video Door Phone For Unmmaned Facilities !
Do You Concern On Hiring A Part-time Job And Hiring Staffs Because Of The Minimum Wage Increase?
AP-VAC150 Video Door Phone For Unmanned Facilities (Such As Unmanned PC Room, Unmanned Study Café, Unmanned Laundry Room, Unmanned Karaoke Room And Unmanned Motel, etc.) Shall Be Good Choice!
AP-VAC150 SIP(Session Initiation Protocols) Video Door Phone, Which Provides Identification From Remote Control Center) With AP-VP280G And AP-ACS1000 (Access Control System 1000)!
You Can Get More Information via YouTube Link or Attached Materials!
https://www.youtube.com/watch?v=2meQWu2rG-c&t=117s
With my regards,
Guisun Han
#Unmanned PC room
#무인PC방
# VAC150
#addpac
#Fingerprint recognition
#SIP
MIPI DevCon 2021: Meeting the Needs of Next-Generation Displays with a High-P...MIPI Alliance
Presented by Alain Legault, Hardent Inc.; Joe Rodriguez, Rambus Inc.; and Justin Endo, Mixel, Inc.
Next-generation display applications have an insatiable appetite for bandwidth. Using a combination of VESA Display Stream Compression (DSC) and MIPI DSI-2℠ technology, designers can achieve display resolutions up to 8K without compromise to video quality, battery life or cost. This presentation discusses a fully integrated, off-the-shelf display IP subsystem solution, consisting of Mixel (MIPI C-PHY℠/D-PHY℠ combo), Rambus (MIPI DSI-2® controller) and Hardent (VESA DSC) IP, that can deliver this state-of-the-art performance in a power-efficient and compact footprint.
VMworld 2013: How Good is PCoIP - A Remoting Protocol ShootoutVMworld
VMworld 2013
Shawn Bass, shawnbass.com
Cyndie Zikmund, VMware
Learn more about VMworld and register at http://www.vmworld.com/index.jspa?src=socmed-vmworld-slideshare
Similar to Upgrade Your Broadcast System to PCIe Gen2 (20)
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
Software Delivery At the Speed of AI: Inflectra Invests In AI-Powered QualityInflectra
In this insightful webinar, Inflectra explores how artificial intelligence (AI) is transforming software development and testing. Discover how AI-powered tools are revolutionizing every stage of the software development lifecycle (SDLC), from design and prototyping to testing, deployment, and monitoring.
Learn about:
• The Future of Testing: How AI is shifting testing towards verification, analysis, and higher-level skills, while reducing repetitive tasks.
• Test Automation: How AI-powered test case generation, optimization, and self-healing tests are making testing more efficient and effective.
• Visual Testing: Explore the emerging capabilities of AI in visual testing and how it's set to revolutionize UI verification.
• Inflectra's AI Solutions: See demonstrations of Inflectra's cutting-edge AI tools like the ChatGPT plugin and Azure Open AI platform, designed to streamline your testing process.
Whether you're a developer, tester, or QA professional, this webinar will give you valuable insights into how AI is shaping the future of software delivery.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
Have you ever wanted a Ruby client API to communicate with your web service? Smithy is a protocol-agnostic language for defining services and SDKs. Smithy Ruby is an implementation of Smithy that generates a Ruby SDK using a Smithy model. In this talk, we will explore Smithy and Smithy Ruby to learn how to generate custom feature-rich SDKs that can communicate with any web service, such as a Rails JSON API.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
UiPath Test Automation using UiPath Test Suite series, part 3
Upgrade Your Broadcast System to PCIe Gen2
1. Upgrade Your Broadcast System to PCIe Gen2 Brian Jentz, Altera Corporation Neil Childs, OmniTek
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7. Devices for Broadcast 8 – 36 up to 6.5 Gbps 2.8M – 11.5M usable ASIC gates 6.3 – 20.3 2.97, 2.5, 5, and 1.25 HardCopy ® IV GX ASIC 12 – 25 up to 11.3 Gbps; 12-24 up to 6.5 Gbps 230K – 530K 13.3 – 20.3 2.97, 2.5, 5, and 1.25 Stratix IV GT FPGA 0-16 up to 6.5 Gbps; 8.32 up to 8.5 Gbps 70K – 530K 6.3 – 20.3 2.97, 2.5, 5, and 1.25 Stratix ® IV GX FPGA 4 – 16 up to 3.75 Gbps 16K – 256K 0.7 – 8.5 2.97, 2.5, 1.25 Arria ® II GX FPGA Transceiver Channels Logic Elements Embedded Memory (Mbit) Data Rates for 3G-SDI, PCI Express Gen1 and Gen2, and Gigabit Ethernet (Gbps per Lane) Device
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9. PCIe Hard IP Testing Altera PCIe Development Cards PCIe Gen2 Motherboard Stratix IV GX PCIe Gen1 and Gen2 Arria II GX PCIe Gen1 PCle Gen2 platforms Motherboard Chipset Processor AMD Asus M3A78-T 790GX/SB750 AMD790GX Intel Asus P5Q-EN Intel-645 LGA775 Intel DX58S0 Tylersburg Core I7
10. Video Framework with PCIe DVI/HDMI SDI Format Conversion BT656 Deinterlacer (VIP) Deinterlacer (VIP) Scaler (VIP) Scaler (VIP) Input CODEC SDI BT656 Output DVI/HDMI Audio Sample rate converter CODEC Audio Video Delay frame sync Ethernet PCIE TS Mux Video Over IP PCIE Deinterlacer (VIP) Scaler (VIP) Altera ® IP Custom IP DDR2/3 Mem ctl DMA Ctl DMA Ctl Display port Deinterlacer (VIP) Scaler (VIP) Display port Third-Party IP PCIe PCIe MPEG2 H.264 JPEG2000 Custom video functions Altera ® IP
11. Video Framework: SOPC/Avalon-ST Video SOPC Builder Ready Avalon ® -ST Video SOPC-Ready Function SDI/HDMI/DP Clocked Video Input AV-ST-V vip1 AV-ST-V vip2 AV-ST-V Clocked Video Output SDI/HDMI/DP
12. Example: Format Conversion SD/HD/3G-SDI CLIP Motion adaptive Polyphase scaler 6x6 taps, 4:4:4 mode Deinterlacer 4:2:2 Frame rate conversion SCL Frame buffer DDR2 HP memory Avalon-ST video Clocked video Nios II processor Run-time configuration through Nios ® II processor CRS 4:2:2 to 4:4:4 CRS 4:4:4 to 4:2:2 Interlacer 4:2:2 Res.: 480i to 1080p SDI SD/HD/3G-SDI SD/HD/3G-SDI CLIP Motion adaptive Polyphase scaler 6x6 taps, 4:4:4 mode Deinterlacer 4:2:2 Frame rate conversion SCL Frame buffer CRS 4:2:2 to 4:4:4 CRS 4:4:4 to 4:2:2 Interlacer 4:2:2 SDI SD/HD/3G-SDI CVI CVO CVI CVO
13. Four-Channel 1080p Video Streaming with Stratix IV GX FPGA SDI core Standard detect Clocked in Multichannel Video Streaming DMA Controller Stratix IV GX FPGA PCIe Hard IP SOPC tool flow SDI video Streaming PCIe video Ext. memory interface Clocked out 352 insert MUX Test pattern
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18. FPGA Block Diagram Stratix IV FPGA SOPC Builder component Control registers Video output Video input SDI MegaCore function Multiplex 352 insert 352 insert Test pattern (color bar) Standard detect Stratix IV FPGA PCIe hard IP OmniTek translation OmniTek multi-channel streaming DMA controller MDMA FDMA FDMA Test mem Clocked video input Clocked video output FPGA capability Timing LUT Video I/O capability
19. SOPC Builder DMA Component DMA controller wrapper Altera PCIe hard IP DMA Controller Core DMA capability registers PCIe translation block - Avalon-MM BAR BAR 0 DMA scatter gather DMA master controller FDMA channel FDMA channel MDMA channel Further FDMA channels Avalon-ST video interface Avalon-ST video interface Avalon-ST video interface Avalon-MM Avalon-ST video
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21. PC GUI Application View four incoming video streams Detect video standard Generate four video outputs Select output standards
Hello and welcome to Upgrade Your Broadcast System to PCIe Gen 2 brought to you by Altera Corporation and Omnitek. My name is Brian Jentz and today I will be discussing a solution for SDI to PCIe that enables up to 4 bi-directional channels of 1080p Video. This is part 1 of the Video Framework Online Series. Later this year, we will present part 2: Remove the external bottleneck in your video design. Also, available now is an 8-minute on-line demo which shows how format conversion can be accelerated using the 1080p video framework.
First, we will look at the applications, challenges and benefits associated with implementing PCIe-based systems. Next, we will discuss a video framework that simplifies hardware design for video systems. The solution we will discuss today leverages this framework to simplify PCIe-based design. Then, Neil Childs from Omnitek will discuss a very efficient SDI to PCIe solution that addresses those key challenges. Finally, we will look at next steps you can take to find out more and evaluate this solution.
The IT industry has been playing an increasingly important role in broadcast. This includes leveraging PC technology and standards such as Ethernet and PCI Express. Many applications have moved away from proprietary motherboards and embedded processors to PC-based motherboards with x86 processors and bus structure. This simplifies software and hardware development. There has also been an explosion of video content providers – from university sports to houses of worship. This has driven significant growth in PC-based capture and editing. The combination of these two areas has driven a dramatic increase in the development and use of PCIe-based cards in broadcast and pro A/V. I have listed a number of the common applications on this slide.
With ESPN launching the first 1080p capable studio in Los Angeles in April, the broadcast industry looks poised to start the transition to 1080p. With 1080p, comes the requirement for higher bandwidth. A typical broadcast system with 4 SDI I/O will require 10 Gbps of bandwidth across the PCIe bus. PCIe has 8b10b which reduces raw data throughput by 20%. So, PCIe Gen2 with 5 Gbps per lane, goes down to 4 Gbps taking into account the impact 0f 8b10b. There is additional overhead which effectively reduces the practical bandwidth to 3.375 Gbps per lane. So, a PCIe Gen2x4 offers a practical bandwidth of 13.5 Gbps. In order to support 4 1080p channels across 4 lanes, PCIe Gen 2 is a must. Even there, the system needs to employ an DMA controller with approximately 80% efficiency. So 1080p comes with a significant bandwidth challenge for PCIe based systems.
In addition to bandwidth, there are a number of other challenges in a PCIe-based broadcast system. The SDI I/O implementation needs to support all data rates and frame rates. From 270 Mbps to 3 Gbps and 24 Hz to 60 Hz. PCIe introduces latency in the system, which needs to be mitigated PCIe and SDI operate on different clocks which requires an alignment of clock domains There are many different PC motherboard chipsets available, which forces hardware testing across many platforms With any broadcast equipment, the first company to market with the right feature set has a significant advantage and usually ends up with market share leadership.
First, we will discuss a video framework that simplifies hardware design for video systems. The solution we will discuss today leverages this framework to simplify PCIe-based design. Next, we will look at the applications, challenges and benefits associated with implementing PCIe-based systems. Then, Roger Fawcett from Omnitek will discuss a very efficient SDI to PCIe solution that addresses those key challenges. Finally, we will look at next steps you can take to find out more and evaluate this solution.
There are several different choices of FPGAs for broadcast applications. As an example, Altera’s 40-nm based Stratix IV GX devices offer transceiver speeds up to 32 6.5 Gbps transceivers, high on-chip memory, video processing performance of 300+ MHz, and 533 MHz external memory performance Altera’s 40-nm Arria II GX family delivers cost and power-optimized silicon for broadcast, featuring up to 16 3.75 Gbps transceivers and 300 MHz external memory performance. Stratix IV GT delivers 10+ Gbps transceiver which enables 10G Ethernet and 10G SDI for aggregated SDI applications. Hardcopy ASIC enables the lowest cost and power for applications such as portable cameras.
The fact that PCIe Hard IP is pre-verified and 100% timing closed saves design teams immensely on what is a complex function (up to 15K LE) Also: Shortens compile time Fits into a smaller FPGA Saves power relative to soft IP implementation In Stratix IV, the PLL in the transceiver block converts the 100 MHz motherboard reference clock to 250 MHz for Gen2 operation. No external PLL is required. Integrated Transaction layer (TL), Data Link layer (DLL), physical interface/media access control (PHY/MAC), and transceivers Low-risk, hardware-verified solutions PCI-SIG compliance workshops Interoperability with multiple ASSP vendors 5 generations of transceiver-based FPGAs with PCI Express support Development kits/demo boards
One of the challenges we discussed earlier was interoperability with a number of different platforms in the industry. Altera has passed PCI-SIG tests and compatibility tests with existing hardware platforms. Interoperability testing Compatibility/functionality with chipsets Core generator with verifying payloads (built in DMA engine) Test for PCIe compliance using PCI-SIG tests Performance testing Testing throughput of PCIe link Stress test using the chain DMA architecture Test configurations Modes PCI Express Gen1 x1, x4, x8 PCI Express Gen2 x1, x4, x8 Now that we have discussed the design challenges for broadcast systems with PCIe and the critical capabilities offered by Altera, I will turn it over to Omnitek to discuss the details of the reference design that they provide.
This diagram shows a typical broadcast system and solutions that exist from Altera and its 3 rd party network. Of course, SDI is the primary I/O standard for broadcast; but other standards co-exist as well. For example, many multiviewers have DVI or HDMI outputs today and may add Display Port in the future. More and more, studios want all their equipment to support any format; Thus, format conversion is moving from an optional feature to a standard requirement on all I/O. Due to requirements for video frame stores, relatively wide external DDR memory can be found in almost all video equipment and the performance of the memory controller and scheduler is a critical consideration in broadcast design. Altera is introducing a new controller and scheduler at IBC 2009 that is optimized for broadcast video applications. More details will be covered outside this webcast. Video Codecs are implemented in FPGAs in video server, contribution encoders, distribution encoders, and IRDs. Altera has a network of companies offering solutions in that space. A number of solutions for Audio exist, include audio de-embed, sample rate converter, and codecs such as AC3. Altera has been a leader in enabling video over IP in studio and headend applications, first introducing its first video over IP reference design in 2006. This webcast primarily focuses on SDI, PCIe, and DMA Controller functions. One of the historical challenges for video design has been the lack of industry interface for connecting different functions together. In response to this, Altera has lead the way in introducing a standard that has gotten significant 3 rd party and OEM support.
Altera introduced an open standard call Avalon Streaming Video. It defines a connectivity and lightweight protocol to enable interoperability for functions developed by different design teams. Avalon streaming video is the basis of a video framework that speeds video design. There are a number of 3 rd party video processing cores that support Avalon Video Streaming. Altera has a tool specific to Altera that recognizes this standard and enables integration of this blocks through a graphical tool. This tool creates interconnect that is correct by construction. This simplifies FPGA design for video systems.
Format conversion is a design that Altera developed which leverages this video framework plus internally developed video processing blocks to implement up/down/cross conversion. This design features two channels with support from 480i up to 1080p with full motion adaptive deinterlacing. A risc processor embedded in the FPGA is called Nios and it allows run-time configuration of all of the functions. This design offers the quality and feature set comparable to off-the-shelf chips plus the ability to customize for a particular application and integrate with other FPGA-based functions. This design fits in an Arria II GX device making it very cost effective versus other solutions.
This is a block diagram showing the key functions of a 4-channel SDI to PCIe Gen 2x4 implementation. Altera has offered SDI since 2003 and demonstrated the industry’s first triple rate SDI implementation at IBC 2006. Altera’s triple rate SDI core handles all the data rates and frame rates required for broadcast.
Firstly, hello, I’m Neil Childs of Omnitek and we have partnered with Altera to produce a SDI -> PCIe -> SDI reference design.
This is a complete solution, built around our Multichannel streaming DMA controller IP and accompanying driver/software. One key intention is that you should not need to have a deep understanding of PCIe. Most of the PCIe controllers available as soft and hard IP require you to format PCIe packets and manage tags etc By bundling our DMA controller, translation block, and the hard IP into one component we can handle all this for you
We started from the aim of transferring 4 * 1080p60 videos in both directions simultaneously. These are handled by what we term FDMA – FIFO DMA – channels. Our DMA controller can also use more traditional MDMA – Memory DMA – channels. The relative number, size and depth of these channels is all GUI configurable. We also wanted to minimize the local buffering required to support 3G-SDI. This requirement, together with the high overall bandwidth requires, places very high demands on our DMA controller and the PC architecture we operate within. We have designed the DMA controller and translation block together to use a lot of the more advanced PCIe features to achieve this. While we have a picture of the S4GX card on this slide, I should point out that we also provide a reference design for the Arria II GX equivalent.
The key to achieving the high bandwidth required for 4*1080p60, and the continuous bandwidth needed to allow operation with minimum local buffering is the Scatter Gather DMA controller. This is a fairly standard feature of DMA controllers, required for use in a PC environment where memory is typically allocated in 4Kbyte blocks which may not be contiguous. In this system DMA operations are broken down into segments and a linked list of these instructions is created by software. When the DMA controller completes one set of instructions it fetches the next link in the list and processes that set of instructions. It has the benefit that the CPU can setup several video frames worth of DMA instructions in advance which means that the CPU does not have to complete any time critical operations. One advanced feature of the Omnitek DMA controller is that it pre-fetches the next SG segment. If it were not to do this the system would pause at the end of a segment while the next set of instructions is fetched. This feature is critical to allow operation without external SDRAM buffering.
So having touched on the specifics of the DMA controller we now look at how this fits into the overall system. Most of the reference design has been implemented within SOPC Builder – this allows easy integration with the Altera VIP suite. We use the Altera CVI and CVO blocks to get video into SOPCB - these are designed to interface with the Altera SDI megacore IP. Omnitek have added a couple of extra components outside of SOPCB to support SMPTE352 and report the incoming video frame rate. We use our own PCIe translation block rather then the Altera PCI Express Compiler SOPC flow component as it allows us to bind the DMA controller more closely to the hard IP. However, in a similar fashion, extra PCIe BARs are mapped to Avalon-MM masters which allow them to access register space within SOPCB. BAR1, as well as accessing the CVI and CVO blocks, also addresses some Omnitek control registers.
It is worth mentioning that while the reference designs are targeted at video, the DMA controller itself just moves bytes around. It does not care what those bytes represent. If in the GUI you define a channel to be of video type, then additional Avalon-ST video interface components are included for that channel. This packs the video data into 32bit words for the DMA controller. If inside the GUI you set a channel to be of “data” type then these interface components are omitted. You can also see in this slide that the more traditional MDMA channels are mapped to an Avalon-MM master bus that could connect to other IP, such as external memory controllers.
In reality this design process within SOPC builder is a simple exercise of dropping in components and wiring the busses together. The diagram shown a 1 channel design, to add more channels you would simply double click on the DMA component to bring up the customization GUI and add another DMA channel. You would then insert the Altera CVI or CVO components and wire the video bus across to the new DMA channel. Because the DMA controller is an SOPC Builder component – it allows the user to access all the Altera VIP suite of components in their design. If you wanted to recreate the same design outside of SOPC builder, then the DMA channels are defined using the documented Avalon format.
Having transferred the frames of video into system PC memory, they are passed to DirectShow. This then DMAs the video from system memory to the Graphics card and displays the video on screen. Of course, a user design may choose to deal with the frames of video differently. Full source code for the driver and example application give users a head start on creating their own designs – with limited knowledge of PCIe. The example app itself shows the 4 input SDI streams as directshow windows – the video has been resized in the GPU, the DMA controller (in this design) always passes back the complete active video without scaling. The app also allows the user to load 4 short video clips into system memory, from where they are played out as a continuous loop.
To put these performance figures into context, 4lane gen2 PCIe = 16Gbit/sec after accounting for 8b10b. However after you have accounted for packet headers, crcs, flow control, ack/nak, the maximum achievable bandwidth is closer to 13.5Gbit/sec. You can see from these figures that we are getting reasonably close to this achievable maximum. This slide shows the bandwidth used to support 4*1080p60 in both directions. The 1.65Gbit/sec for read requests is due to the nature of PCIe. In order to move the 10.6Gbit/sec of data from the PC to the FPGA, the DMA controller must send read packets to the PC asking the PCIe root complex in the Northbridge to send that data back. As you can see, this overhead is quite a significant bandwidth in itself. You can also see that the DMA controller is quite a small part of an FPGA. The S4GX 230 has over 1200 M9Ks and over 90,000 ALMs (adaptive logic modules) = 2LUTs + 2regs.
Key message - PCIe is difficult. Omnitek has a long background not only related to video but also PCIe. By using our DMA controller you do not need PCIe hardware experience.
Hello, this is Brian Jentz again. Roger, thanks for the detailed explanation of the SDI to PCI design. Let’s wrap up by looking at where to go for more information and how to evaluate the solution.
You can go to Altera’s website to get access to the design for evaluation. You can also download user guides from that location. As mentioned during the webcast, this design runs on both Stratix IV GX and Arria II GX. We have provided links for those kits here.
Thank you for viewing today’s web cast - How to Design Your Power Delivery Network (PDN) for High-End FPGAs - brought to you by Altera Corporation. We would like to get your feedback about this webcast so please fill out the survey that will open on your screen at the conclusion of this program. If you still have questions, please click on the “Ask a Question” button and you will receive a response via email within 3 business days. My name is Seyi Verma and on behalf of Altera Corporation, thank you for joining us today.