this pdf includes the complete description of SR & JK flip flop

1. Verify the truth table of SR, JK
flip-flops using NAND & NOR
gates
Name:-Aman Goyat
10518210001
Btech/EEE

2. Flip Flop:-
 A flip flop is an electronic circuit with two stable states that can be used to store binary
data.
 The stored data can be changed by applying varying inputs. Flip-flops and latches are
fundamental building blocks of digital electronics systems used in computers,
communications, and many other types of systems. Flip-flops and latches are used
as data storage elements.
 In this we will talk about:-
 SR flip flop using the NAND & NOR gates.
 JK flip flop using the NAND & NOR gates.
 After this ppt you will make you dought clear about this topic.

3. SR Flip-flops(SET-RESET):-
 The basic building bock that makes computer memories possible, and is also used in
many sequential logic circuits.
 The SR flip-flop can be considered as a 1-bit memory
 The SR (Set-Reset) flip-flop is one of the simplest sequential circuits and consists of two
gates connected as shown in Fig. Notice that the output of each gate is connected to
one of the inputs of the other gate, giving a form of positive feedback or ‘cross-coupling’.
 When we are talking about set and reset it means that:-
 Set =Output value is 1
 Reset =Output value is 0

4. Two way of representation:-
:-NAND FLIP-FLOP :-NOR FLIP-FLOP

5. The NAND Gate SR Flip-Flop:-
 The simplest way to make any basic single bit set-reset SR flip-flop is to connect
together a pair of cross-coupled 2-input NAND gates as shown, to form a Set-Reset
Bistable also known as an active LOW SR NAND Gate, each output to one of the
other NAND gate inputs. This device consists of two inputs, one called the Set, S and
the other called the Reset, R with two corresponding outputs Q and its inverse or
complement Q (not-Q) as shown below.

6. Output Side:-
 The Set State:-
Consider the circuit shown above. If the input R is at logic level “0” (R = 0) and
input S is at logic level “1” (S = 1), the NAND gate Y has at least one of its inputs at logic “0”
therefore, its output Q must be at a logic level “1” (NAND Gate principles). Output Q is also fed
back to input “A” and so both inputs to NAND gate X are at logic level “1”, and therefore its
output Q must be at logic level “0”.
 Reset State:-
In this second stable state, Q is at logic level “0”, (not Q = “0”) its inverse output
at Q is at logic level “1”, (Q = “1”), and is given by R = “1” and S = “0”. As gate X has one of its
inputs at logic “0” its output Q must equal logic level “1” (again NAND gate principles). Output Q is
fed back to input “B”, so both inputs to NAND gate Y are at logic “1”, therefore, Q = “0”.

7. Truth Table for this Set-Reset Function

8. Experiment to perform SR Flip
Flop on kit:-

9. Truth-Table & Clock Diagram:-

10. The NOR Gate SR Flip-flop:-
Flip-flops can also be
considered as latch circuits due to them remembering or ‘latching’ a change
at their inputs. A common form of RS latch is shown in Fig. 5.2.5. In this
circuit the S and R inputs have now become S and R inputs, meaning that
they will now be ‘active high’.

11. Truth Table:-
Below we have shown that how SR Flip Flop can be
designed using NOR gate. In the circuit diagram, there are two input terminals S
R. Understanding of the truth table of NOR gate is important before knowing the
working of the circuit. In the NOR gate, if the input at both the terminals is low i.e. 0
then only we get the output high i.e. 1. If any of the input terminals or both of the
inputs are in high state i.e. 1, then output will be low i.e. 0.

12. If we have the S-R flip flop then why we
need the J-K flip flop…..?

13. The basic S-R NAND flip-flop circuit has
many advantages and uses in sequential
logic circuits but it suffers from two basic
switching problems.
• 1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
• 2. if Set or Reset change state while the enable (EN) input is high the
correct latching action may not occur
• Then to overcome these two fundamental design problems with the SR
flip-flop design, the JK flip Flop was developed.

14. JK flip Flop:-(universal flip flop)
 This simple JK flip Flop is the most widely used of all the flip-flop designs
and is considered to be a universal flip-flop circuit.
 The JK flip flop is basically a gated SR flip-flop with the addition of a
clock input circuitry that prevents the illegal or invalid output condition that
can occur when both inputs S and R are equal to logic level “1”.
 Due to this additional clocked input, a JK flip-flop has four possible input
combinations, “logic 1”, “logic 0”, “no change” and “toggle”.
 The J-K flip-flop is much faster. The J-K flip-flop does not have
propagation delay problems.

15. The Basic JK Flip-flop:-
Both the S and the R inputs of the
previous SR bistable have now been replaced by two inputs called
the J and K inputs, respectively after its inventor Jack Kilby. Then this equates
to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by
two 3-input NAND gates with the third input of each gate connected to the outputs
at Q and Q.

16. The Truth Table for the JK Function:-

17. Experiment to perform logic of JK
FLIP FLOP on kit:-

18. Truth-Table & Clock Diagram:-

19. Dual JK Flip-flop 74LS73:-

20. At the last:-