flip flop presentation

1. Satish Pradhan
Dnyanasadhana college, Thane

2. Introduction
 A flip-flop or latch is a circuit that has two stable states and can be used to store state
information.
A flip-flop is a bistable multivibrator.
The circuit can be made to change state by signals applied to one or more control inputs and
will have one or two outputs.
It is the basic storage element in sequential logic.
Flip-flops and latches are a fundamental building block of digital electronics systems used in
computers, communications, and many other types of systems.

3. History
The first electronic flip-flop was invented in
1918 by William Eccles and F. W. Jordan.
It was initially called the Eccles–Jordan trigger
circuit and consisted of two active elements
(vacuum tubes). Such circuits and their
transistorized versions were common in
computers even after the introduction of
integrated circuits, though flip-flops made
from logic gates are also common now.
Early flip-flops were known variously as
trigger circuits or multivibrators.

4. SR NOR LATCH
It is the most simple latch, where S & R stands for Set & Reset.
It can be constructed from a pair of cross-coupled NOR logic gates.
While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant
state, with Q the complement of Q.
If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays
high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is
forced low, and stays low when R returns to low.
The R = S = 1 combination is called a restricted combination or a forbidden state because, as
both NOR gates then output zeros, it breaks the logical equation Q = not Q. The combination is
also inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition from
restricted to keep). The output would lock at either 1 or 0 depending on the propagation time
relations between the gates (a race condition).

5. SR NOR LATCH
SR latch operation
Characteristic table Excitation table
S R Qnext Action Q Qnext S R
0 0 Q hold state 0 0 0 X
0 1 0 reset 0 1 1 0
1 0 1 set 1 0 0 1
1 1 X
not
allowed
1 1 X 0

6. HALF- ADDER

7. Unclocked D latch
We modify the design of R S flip-flop to
eliminate the possibility of race condition. The
resultant is a new kind of flip-flop known as a
D Latch.
A high D sets the latch, and a low D resets the
latch.
The inverter guarantees that S & R will always
be in opposite states; therefore, it’s impossible
to set up a race condition in D Latch.
D Q
0 0
1 1

8. Clocked D Latch
The inverter gate ensures that both S & R
inputs are never of same logical value.
When the clock is low, both the input AND
gates are disabled, D can change the values
without affecting the output Q.
When clock is high, and D=1 the upper AND
gate will be enabled and output takes the
value of D i.e. Q=1. While the lower gate will
be enabled and Q=0. That means Q retains the
last value of D till the clock goes low.
It also prevents the value of D from reaching
the Q until a clock pulse occur.

9. Clocked D LATCH
Four D latches connected as shown can be
used to store a 4 bit word (nibble).
All the latches are driven by the same clock.
When clock goes high, data at the input gets
loaded into flip-flops and appears at the
output and when clock goes low, data is
retained at the output.
As long as the clock is low, the D values can
change without affecting Q values.

10. IC 7474 & IC 7475
IC 7474 is a dual D flip-flop IC & IC 7475
contains quad bistable latches.
In 7475 latch when the clock signal is high the
output Q changes according to the input D.
when the clock signal goes low the output Q
will latch
In 7474 the output changes with the positive
edge of the clock.
A latch is used commonly to interface output
devices.

11. IC 74LS373
This octal latch is suitable to latch 8 bit data. This device includes eight D latches with tri state
buffers. It requires two input signals, Enable (G) and Output Control.
These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or
relatively low-impedance loads.
The high-impedance 3-state and increased high-logic-level drive provide these registers with the
capability of being connected directly to and driving the bus lines in a bus-organized system.
The eight latches of the ’LS373 are transparent D-type latches, meaning that while the enable (C
or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the
output is latched at the level of the data that was set up.

12. USES
Eight Latches in a Single Package
• 3-State Outputs for Bus Interfacing
• Hysteresis on Latch Enable
• Edge-Triggered D-Type Inputs
• Buffered Positive Edge-Triggered Clock
• Hysteresis on Clock Input to Improve Noise Margin
• Input Clamp Diodes Limit High Speed Termination Effects

13. IC 74LS373
Output
Control
Enable G D Output
L H H H
L H L L
L L X Q
H X X Z