Digital Design Course Summary

Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 2
References
Ref 1 Ref 2

Session 1: Focus
 Course Objectives
 Topics covered and References
 Analog Vs Digital
 Processing by Digital systems
 Number systems
◦ Binary, octal, hexadecimal
 Conversions from one to the other

Session 2: Focus
 Binary codes and their classifications
 Weighted codes
◦ Binary Coded Decimal (BCD)
 Various BCD formats
 Unsigned BCD arithmetic
 Packed and unpacked BCD
 Non-weighted codes
◦ Excess-3
◦ Gray code
◦ Optical Encoder Example using Gray Code

Session 3: Focus
 ASCII & Parity bit
 7-Segment Display
 Logic Gates
 AND, OR, NOT
 NAND and NOR
 XOR and Exclusive-NOR
 Logic Gates - ICs
 Binary Addition
◦ Half and Full Adder Circuits
 Binary Subtraction
◦ Half and Full Subtractor Circuits
 Parity Generators using XOR gates

Session 4: Focus
 Subtraction using 2’s Complement
◦ 2’s Complement Notation
◦ 2’s complement subtraction
 Universal Gates
◦ NAND and NOR
 Parity Check Circuits using XOR Gates

Session 5: Focus
 Binary Multiplication
◦ Repeated Left-shift and Add
 4-bit Multiplier Circuit
◦ Repeated Add and Right-shift
 Binary Division
◦ Repeated Right-shift and Subtract
◦ Repeated Subtract and Left-shift

Session 6: Focus
 Number Representations
◦ Scientific Notation
◦ Normalized numbers
 Floating-point Representation
◦ IEEE 754 Format
◦ Single Precision (32 bits)
 Exponent and Significand
 Biased Exponent
 Range of floating point numbers
◦ Reference: Video Lecture on this topic

Session 7: Focus
 Introduction to Boolean Algebra
 Ordinary Algebra Vs Boolean Algebra
 Boolean Expressions
◦ Variables, literals and terms
◦ Complement and Dual
 Laws of Boolean Algebra
 Rules of Boolean Algebra
◦ Rules 1 to 6

Session 8: Focus
 Rules of Boolean Algebra
◦ Rules 7 to 12
 Theorems of Boolean Algebra
◦ Consensus Theorem
◦ DeMargon’s Theorems

Session 9: Focus
 Simplification Techniques
 Simplification using Boolean Algebra
◦ Quiz 1 to 3
 Two forms of Boolean Expressions
◦ Sum-of-Products (minterms)
◦ Products-of-Sums (maxterms)
◦ Canonical notation
◦ Example
 Home Work

Session 10: Focus
 Introduction to Karnaugh map
 Examples
◦ SOP form
◦ POS form
◦ Both SOP and POS
◦ Implementation
◦ 5-variable K-map
 Don’t cares in K-map
◦ Example

Session 11: Focus
 Full Adder-subtractor Circuit
◦ Carry Propagation Delay
◦ Look-ahead Carry Implementation
◦ Advantages and disadvantages

Session 12: Focus
 Binary Multiplier
◦ 2-bit multiplier Implementation
◦ 4-bit by 3-bit multiplier Implementation
 Decoder
◦ Basic Binary Decoding logic
◦ 3-to-8 line Decoder Implementation
◦ 4-bit Decoder
◦ Decoder in Use
 Encoder
◦ Decimal-to-BCD Encoder

Session 13: Focus
 Multiplexers (MUX)
◦ 2-to-1 line MUX Implementation
◦ 4-to-1 line MUX Implementation
◦ MUX Symbols/Representation

Session 14: Focus
 Multiplexers (MUX)
◦ Usage in Real-life Applications
 Demultiplexer (DEMUX)
◦ 1-to-4-line Demultiplexer
◦ Symbols or Representation
◦ Usage in Real-life Applications
 Solving problems
◦ With Basic Gates
 Solving Logical problems
 Home work problems
◦ Logic Gates
◦ K-maps

Session 15: Focus
 Sequential Circuits
 Classification of Sequential Circuits
◦ Asynchronous
◦ Synchronous

Session 16: Focus
 Storage Elements
◦ SR-Latches
 NOR based

Session 17: Focus
 Storage Elements
◦ SR – Latches
 Using NOR gates
◦ S’R’-Latches
 Using NAND Gate
 D Latch (Transparent latch)
 Graphic Symbols of Latches

Session 18: Focus
 Latches and Flip-flops
◦ Level and Edge-triggered clocks
◦ Clock edges (+ve and –ve)
 Edge-triggered D Flip-flops
◦ Negative edge-triggered (Master-Slave)

Session 19: Focus
 Edge-triggered D Flip-flops
◦ Positive edge-triggered D Flip-flop Implementation
◦ Logic Symbol
 JK Flip-flop
◦ Implementation

Session 20: Focus
 Master-slave - D-Flip-flop
◦ Negative edge triggered
◦ Positive edge triggered
 D Flip-flop
◦ Preset and Clear Implementation
 Circuits using D Flip-flop
◦ Data latches
◦ Detecting the sequence of Edges

Session 21: Focus
 Applications using D Flip-flop
◦ Frequency Divider
◦ 4-bit Asynchronous Up counter
◦ 4-bit Asynchronous Down counter

Session 22: Focus
 Applications using D Flip-flop
◦ Serial to Parallel Data Converter
◦ Parallel to Serial Data Converter
 JK Flip-flop
◦ Why is JK flip-flop named so?
◦ Preset and Clear
 Applications using JK Flip-flops
◦ Frequency Dividers

Session 23: Focus
 More Applications using JK Flip-flops
◦ Frequency Divider - Divide by 4
◦ n-bit Ripple Counter (Mod-2n Counter)
◦ Ripple Counter with Modulus less than 2n
◦ 4-bit Register
 T Flip-flop

Session 24: Focus
 Finite State Machine (FSM)
◦ Example: Turnstile
 Types of Clocked Sequential Circuits
◦ Moore Model
◦ Mealy Model
◦ Example circuits
 Analysis of Clocked Sequential Circuits
◦ Example 1: Moore Machine (partial)

Session 25: Focus
 Types of Clocked Sequential Circuits
◦ Moore and Mealy Models
 Analysis of Clocked Sequential Circuits
◦ Logic Diagram
◦ State equations
◦ State Table
◦ State Diagram
 Example 1: Moore Machine
 Example 2: Mealy Machine
 Problem 1 – Using T Flip-Flop

Session 26: Focus
 State Diagrams
◦ Some Examples
 Design of Sequential Circuits
 Design Steps
 Design of Sequence Recognizer (1011)
◦ State Diagram
◦ State Table
◦ State Assignment

Session 27: Focus
 Design of Sequential Circuits
 Design Steps
◦ State Diagram
◦ State Table
◦ State Transition Table
◦ Designing combinational circuit
◦ Circuit Diagram

Session 28: Focus
 Quiz and Lab Mid-Sem Solutions:
◦ DD Quiz 3 – Set-1 (and answers to Set-2)
◦ DD Lab Mid-Sem solutions (set-1)

Session 29: Focus
◦ State Diagram
◦ State Table
◦ State Transition Table
◦ Designing combinational circuit
◦ Circuit Diagram – Home work

References
Ref 1 Ref 2

Digital Design Course Summary

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