I3E Technologies, #23/A, 2nd Floor SKS Complex, Opp. Bus Stand, Karur-639 001. IEEE PROJECTS AVAILABLE, NON-IEEE PROJECTS AVAILABLE, APPLICATION BASED PROJECTS AVAILABLE, MINI-PROJECTS AVAILABLE. Mobile : 99436 99916, 99436 99926, 99436 99936 Mail ID: i3eprojectskarur@gmail.com Web: www.i3etechnologies.com, www.i3eprojects.com

1. DESIGN OF SELF-TIMED RECONFIGURABLE CONTROLLERS
FOR PARALLEL SYNCHRONIZATION VIA WAGGING
ABSTRACT:
Synchronization is an important issue in modern system design as systems-on-
chips integrate more diverse technologies, operating voltages, and clock frequencies on a single
substrate. This paper presents a methodology for the design and implementation of a self-timed
reconfigurable control device suitable for a parallel cascaded flip-flop synchronizer based on a
principle known as wagging, through the application of distributed feedback graphs. By
modifying the endpoint adjacency of a common behavior graph via one-hot codes, several
configurable modes can be implemented in a single design specification, thereby facilitating
direct control over the synchronization time and the mean-time between failures of the parallel
master-slave latches in the synchronizer. Therefore, the resulting implementation is resistant to
process nonidealities, which are present in physical design layouts. This paper includes a
discussion of the reconfiguration protocol, and implementations of both a sequential token ring
control device, and an interrupt subsystem necessary for reconfiguration, all simulated in UMC
90-nm technology. The interrupt subsystem demonstrates operating frequencies between 505 and
818 MHz per module, with average power consumptions between 70.7 and 90.0 μW in the
typical-typical case under a corner analysis.