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FULLY PIPELINED LOW-COST AND HIGH-QUALITY
COLOR DEMOSAICKING VLSI DESIGN FOR
REAL-TIME VIDEO APPLICATIONS
ABSTRACT:
This brief presents a fully pipelined color demosaicking design. To improve the
quality of reconstructed images, a linear deviation compensation scheme was created to increase
the correlation between the interpolated and neighboring pixels. Furthermore, immediately
interpolated green color pixels are first to be used in hardware-oriented color demosaicking
algorithms, which efficiently promoted the quality of the reconstructed image. A boundary
detector and a boundary mirror machine were added to improve the quality of pixels located in
boundaries. In addition, a hardware sharing technique was used to reduce the hardware costs of
three interpolators. The very-large-scale integration architecture in this brief contains only 4.97
K gate counts, and the core area is 60 229 μm2 synthesized by using 0.18-μm CMOS process.
Compared with the previous low-complexity designs, this work has the benefits in terms of low
cost, low power consumption, and high performance.

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Fully pipelined low cost and high-quality color demosaicking vlsi design for real-time video applications

  • 1. FULLY PIPELINED LOW-COST AND HIGH-QUALITY COLOR DEMOSAICKING VLSI DESIGN FOR REAL-TIME VIDEO APPLICATIONS ABSTRACT: This brief presents a fully pipelined color demosaicking design. To improve the quality of reconstructed images, a linear deviation compensation scheme was created to increase the correlation between the interpolated and neighboring pixels. Furthermore, immediately interpolated green color pixels are first to be used in hardware-oriented color demosaicking algorithms, which efficiently promoted the quality of the reconstructed image. A boundary detector and a boundary mirror machine were added to improve the quality of pixels located in boundaries. In addition, a hardware sharing technique was used to reduce the hardware costs of three interpolators. The very-large-scale integration architecture in this brief contains only 4.97 K gate counts, and the core area is 60 229 μm2 synthesized by using 0.18-μm CMOS process. Compared with the previous low-complexity designs, this work has the benefits in terms of low cost, low power consumption, and high performance.