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ARRAY-BASED APPROXIMATE ARITHMETIC COMPUTING: A
GENERAL MODEL AND APPLICATIONS TO MULTIPLIER AND
SQUARER DESIGN
ABSTRACT:
We propose a general model for array-based approximate arithmetic
computing (AAAC) to guide the minimization of processing error. As part of this model,
the Error Compensation Unit (ECU) is identified as a key building block for a wide range
of AAAC circuits. We develop theoretical analysis geared towards addressing two
critical design problems of the ECU, namely, determination of optimal error
compensation values and identification of the optimal error compensation scheme. We
demonstrate how this general AAAC model can be leveraged to derive practical design
insights that lead to optimal tradeoffs between accuracy, energy dissipation and area
overhead. To further minimize energy consumption, delay and area of AAAC circuits,
we perform ECU design simplification by introducing logic don't cares. By applying this
model and using a commercial 90 nm CMOS standard cell library, we propose an
approximate 16 16 fixed-width Booth multiplier that consumes 44.85% and 28.33% less
energy and area compared with theoretically the most accurate fixed-width Booth
multiplier.

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