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DEPTH-RELIABILITY-BASED STEREO-MATCHING ALGORITHM
AND ITS VLSI ARCHITECTURE DESIGN
ABSTRACT:
A low-complexity depth-reliability-based stereomatching algorithm and an
efficient scanline memory-merging implementation scheme are proposed in this paper. The
developed algorithm analyzes the accuracy of disparity results by using simple local window-
based methods and preserves reliable information only. A bidirectional depth propagation flow is
then adopted to fill the unreliable segments by using reliable information. Moreover, a set of
predefined function-specific reliability variables are extracted to further improve depth quality in
the occluded and smooth regions, which can reduce 39% bad pixels obtained by applying the
basic 7 × 7 window-based matching. The proposed scanline memory-merging scheme along with
data prefetching can lead to 32.7% savings on the scanline memory area and relax the
requirements of external frame buffer size and bandwidth. Experimental results show that the
implemented stereo-matching hardware has a gate count of 223 k including the scanline memory,
and can achieve up to 70 frames/s for 480×540 resolution (2×2 downsampling of FullHD side-
by-side 3-D format) with 56 disparity levels

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Depth reliability-based stereo-matching algorithm and its vlsi architecture design

  • 1. DEPTH-RELIABILITY-BASED STEREO-MATCHING ALGORITHM AND ITS VLSI ARCHITECTURE DESIGN ABSTRACT: A low-complexity depth-reliability-based stereomatching algorithm and an efficient scanline memory-merging implementation scheme are proposed in this paper. The developed algorithm analyzes the accuracy of disparity results by using simple local window- based methods and preserves reliable information only. A bidirectional depth propagation flow is then adopted to fill the unreliable segments by using reliable information. Moreover, a set of predefined function-specific reliability variables are extracted to further improve depth quality in the occluded and smooth regions, which can reduce 39% bad pixels obtained by applying the basic 7 × 7 window-based matching. The proposed scanline memory-merging scheme along with data prefetching can lead to 32.7% savings on the scanline memory area and relax the requirements of external frame buffer size and bandwidth. Experimental results show that the implemented stereo-matching hardware has a gate count of 223 k including the scanline memory, and can achieve up to 70 frames/s for 480×540 resolution (2×2 downsampling of FullHD side- by-side 3-D format) with 56 disparity levels