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1. ALGORITHM AND ARCHITECTURE DESIGN OF THE H.265/HEVC INTRA
ENCODER
ABSTRACT:
Improved video coding techniques introduced in the h.265/hevc standard allow
video encoders to achieve better compression efficiencies. On the other hand the increased
complexity requires a new design methodology able to face challenges associated with ever
higher spatio-temporal resolutions. The paper presents the computationally-scalable algorithm
and its hardware architecture able to support the intra encoding up to the 2160p@30fps
resolution. The scalability allows the tradeoff between the throughput and the compression
efficiency. In particular, the encoder is able to check a variable number of candidate modes. The
rate estimation based on bin counting and the distortion estimation in the transform domain
simplify the rate-distortion analysis and enable the evaluation of a great number of candidate
intra modes. The encoder preselects candidate modes by the processing of 8×8 predictions
computed from original samples. The preselection shares hardware resources used for the
processing of predictions generated from reconstructed samples. To support intra 4×4 modes for
the 2160p@30fps resolution, the encoder incorporates a separate reconstruction loop.