Dr. Lalit Patnaik presented the design of a 100W radiation-tolerant power-factor-correction buck AC/DC converter for use in the High Luminosity LHC project. The design uses commercial off-the-shelf components to convert an AC input of 90-265V to a 48V DC output while maintaining a power factor over 0.9 and efficiency of around 90%. Simulation and preliminary testing validated the design, which will undergo further radiation testing to evaluate performance under total ionizing doses up to 300Gy and single event effects from proton beams. The proposed buck converter topology was shown to provide advantages over a boost topology for this application in terms of component selection and reliability.

1. Design of a 100W Radiation-Tolerant
Power-Factor-Correction Buck
AC/DC Converter
Dr. Lalit Patnaik
CERN, Geneva, Switzerland
1
HL-LHC WP18
Power
Electronics
Talks
18 Nov 2020

2. High Luminosity LHC Project
2
[1] HL-LHC homepage: https://hilumilhc.web.cern.ch/content/hl-lhc-project
[2] More light for the LHC: meet HiLumi LHC project [34-minute video] Lalit Patnaik
Objective:
10x more collisions
⇒ Increase discovery
potential of LHC

3. Distributed I/O Tier (DIOT)
3
Front-End Computer
VME/PICMG/PLC
master
Front-End Tier
Fieldbus Tier
Distributed I/O Tier
Fieldbus (WorldFIP/PROFINET/etc)
DIO3
slave
sensor
DIOn
slave
sensor
DIO2
slave
actuator
DIO1
slave
actuator
radiation-free
[2] DI/OT project wiki: https://ohwr.org/project/diot/wikis/home
radiation-exposed
Lalit Patnaik

4. Distributed I/O Tier Crate
4
Lalit Patnaik
PSU
• Dual redundancy
• Power sharing
Fixed Panel
System
Board
Peripheral Boards
Backplane
[2] DI/OT project wiki: https://ohwr.org/project/diot/wikis/home

5. RaToPUS: Radiation-Tolerant Power Supply
5
Objective: Design and test a generic PSU for Distributed I/O Tier (DIOT) crates
to be used under radiation environment by various CERN user groups.
➢ Using Commercial Off-The-Shelf (COTS) components
(a) Typical 100 W AC/DC power supply architecture for radiation-free applications.
(b) Proposed architecture (RaToPUS) for radiation-exposed applications.
[3] RaToPUS project wiki: https://ohwr.org/project/psu-rad-acdc-230v-12v5v-110w/wikis/home Lalit Patnaik

6. Power Factor Correction: Boost vs Buck
6
Lalit Patnaik
[4] H. Endo, T. Yamashita, and T. Sugiura, “A high-power-factor buck converter,” in Proc. IEEE Power
Electron. Spec. Conf. (PESC) Rec., Jun. 1992, pp. 1071–1076.

7. 300-450V
Not many options!
Power Factor Correction: Why Use Buck Topology?
7
Lalit Patnaik
Data source: Farnell
• PFC Boost: 400V DC link
➢AC/DC stage: 800V MOSFETs
➢DC/DC stage: 800V MOSFETs
• PFC Buck: 48V DC link
➢AC/DC stage: 800V MOSFETs
➢DC/DC stage: 200V MOSFETs (low RDS,on)
✓ Efficiency improvement
✓ Large number of COTS MOSFET options

8. 8
Lalit Patnaik
• Inherent inrush current limiting (∼1A)
✓No need of NTC thermistor:
- Small reduction in cost and PCB real estate
- Small efficiency improvement
- Enables use of fast blow fuse: Better fire safety
✓Higher reliability:
“The (boost) PFC is the most important failure
source of all devices equipped with it. […] Power
transistor failure (suspected cause: too high inrush
current and exceeded operating temperature).” [5]
[5] V. Bobillier and S. Mico, “Failure analysis and lessons learned on LHC experiments crate and power
supply equipment,” Journal of Instrumentation, Feb. 2015.
“Successful engineering is all about understanding how things break or fail.”
–Henry Petroski, American engineer specializing in failure analysis
[5]
Power Factor Correction: Why Use Buck Topology?

9. Choice of DC Link Voltage
0V
- Large inrush current
- High VDSS required for MOSFET in DC/DC stage
36V
72V
100V
325V
400V
Boost
Buck
- Large crossover distortion
- Poor power factor
- High VDSS required for MOSFET in DC/DC stage
- High VDSS required for MOSFET in DC/DC stage
- Good compromise for rad-tol applications
- Very low duty cycle; Poor efficiency
Lalit Patnaik 9

10. Caveat: Optimize Slope Compensation
Input current waveform can "grow
horns" if the slope compensation
(ks) is too low (solid red waveform).
[7] L. Huber, L. Gang, and M. M. Jovanovic, “Design-oriented analysis and performance evaluation of
buck PFC front end”, IEEE Transactions on Power Electronics, vol. 25, no. 1, pp. 85–94, 2009.
Lalit Patnaik 10

11. PFC Buck AC/DC Converter: Circuit Schematic
11
• Po = 100 W, Vin = 90-265 Vac, Vo = 48 Vdc, Total Ionizing Dose (TID) = 300 Gy
• EMI filter: Common-mode and Differential mode
• COTS PWM Controller (Current-Mode): TL2843
[6] B. Keogh, “Power factor correction using the buck topology,” TI Power Supply Design Seminar 2010. Lalit Patnaik

12. PFC Buck AC/DC Converter: Printed Circuit Board
12
Lalit Patnaik
Space for DC/DC stage: 48V to 12V
Active Clamp Forward Converter

13. MOSFET Under Radiation: Threshold Voltage Drift
13
• Vth drifts (decreases) with TID
• Higher gate bias (Vg) ⇒ Greater Vth drift
• Vth ≤ 0 ⇒ MOSFET is uncontrollable!
Radiation test results for 800 V MOSFET IPA80R280P7:
Lalit Patnaik

14. MOSFET Under Radiation: Threshold Voltage Drift
14
• Vth drifts (decreases) with TID
• Higher gate bias (Vg) ⇒ Greater Vth drift
• Vth ≤ 0 ⇒ MOSFET is uncontrollable!
Radiation test results for 800 V MOSFET IPA80R280P7:
Lalit Patnaik
Use maximum gate drive voltage of 10V

15. MOSFET Under Radiation: Single Event Burnout (SEB)
15
Radiation test results for 800 V MOSFET IPA80R280P7:
• No SEBs for VDS < 540 V
• Worst case VDS in PFC buck is 375 V
• Design is safe
Lalit Patnaik
50% VDSS derating ensures no SEB

16. Results: At Steady-State
16
Simulation Experiment
• High power factor > 0.9
• Small blanking period at the zero-crossing, when Vin < 48 V
• Vo=48V with 2.6 V (5.4%) ripple at 100 Hz
Lalit Patnaik

17. Results: Dynamic Loading
17
• Load current slew rate: 5.0 A/ms
• Most of the dynamic loading handled by DC/DC stage
• AC/DC stage can have a low bandwidth (∼10 Hz)
Lalit Patnaik

18. 18
Results: Power Factor and Efficiency
Lalit Patnaik
Power Factor > 0.9
For load > 60%
Efficiency > 85% 89.5%
For load > 60%

19. 19
Efficiency Improvement Measures
Lalit Patnaik
• Change from COTS inductor (single winding)
to custom inductor (multi-winding)
• Slightly higher resistance but higher
inductance, lower peak currents, lower loss
PFC inductor current waveform (from LTspice simulation)
Frequency [Hz] Current [A]
0 (dc) 2.5
100 1.1
100k 0.8
10 ms
6 A
100 µH
117 µH
COTS inductor
(single winding)
Custom inductor
(multi-winding)

20. 20
A Word on Magnetics Design
Lalit Patnaik
If the magnetic components are not designed well, the choice of power
topology, semiconductor devices, and control scheme might not be able
to rescue the power supply design.
"The design of magnetic
components is the easiest place to
jeopardize a power supply design
project." –Robert Mammano
Snippet source: 'Practical Switching Power Supply Design'
by Marty Brown (1990)

21. 21
Efficiency Improvement Measures (contd.)
Lalit Patnaik
Efficiency > 85% 89.5%
For load > 60%
• Faster turn-on and turn-off of MOSFET
(modified gate driver)
• Remove RC snubber for MOSFET (!)
• Change Si ultrafast diode to SiC Schottky
➢ Lower forward voltage
➢ Zero reverse recovery charge
4-5% increase in efficiency
30% reduction is losses
Inductor & MOSFET run 35⁰C cooler

22. Conclusion
• 100 W radiation-tolerant PFC buck AC/DC converter using COTS components
➢ Vin = 90-265 Vac; Vo = 48 Vdc
➢ Power Factor > 0.9
➢ Vo ripple < 10%
➢ Efficiency ∼ 90%
➢ TID up to 300 Gy
• Proposed design is validated by simulation, experiments, and component-level
radiation tests
• System-level radiation tests planned:
➢ Co-60 (gamma-ray) for dose effects
➢ 200 MeV proton beam for dose effects + single-event effects
• Project on Open Hardware Repository:
https://ohwr.org/project/psu-rad-acdc-230v-12v5v-110w/ 22
Lalit Patnaik

23. Relevant Publication
L. Patnaik, G. Daniluk, S. Danzeca, “Design of a 100W Radiation Tolerant Power-
Factor-Correction Buck AC/DC Converter,” PCIM Europe Digital Days, July 2020.
https://ieeexplore.ieee.org/document/9178215
23
Lalit Patnaik

24. 24
Lalit Patnaik
Email: lalit.patnaik@cern.ch
Twitter: @lalitpatnaik
Thank You Very Much!