IEEE Webinar Author: Lalit Patnaik

1. Designing Radiation-Tolerant Power Supplies
Using COTS Components
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Talk organized by IEEE Student Branch
Indian Institute of Technology, Bhubaneswar
Dr. Lalit Patnaik
CERN, Geneva, Switzerland
22 January 2021

2. From Bhubaneswar to Geneva
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Lalit Patnaik
Image source: http://www.ficciflo.com/chapter/bhubaneswar/
Image source: https://commons.wikimedia.org/wiki/File:CERN_Wooden_Dome_5.jpg
Bhubaneswar, India
Geneva, Switzerland

3. Context
Disclaimer
• Perspective of a power electronics engineer
• No background/expertise in radiation physics
• Designing rad-tol power supplies since 2018
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[1] DI/OT project wiki: https://ohwr.org/project/diot/wikis/home
[2] RaToPUS project wiki: https://ohwr.org/project/psu-rad-acdc-230v-12v5v-110w/wikis/home
Supported by:

4. RaToPUS Prototypes
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RaToPUS AC/DC
Topology: Power Factor Correction (PFC) Buck
230Vac input, 48Vdc output, 125W
Radiation tests coming up
RaToPUS DC/DC
Topology: Active Clamp Forward (ACF)
48Vdc input, 12Vdc output, 100W
Tested up to 300Gy TID

5. Premise
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COTS = COST Advantage
*COTS
COTS+
AEC
MIL
Rad-hard
Increasing robustness
Increasing cost $$$
*Commercial Off-The-Shelf

6. Before you jump the gun
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Before you have a radiation-tolerant power supply
you need a working power supply
Efficient, low-ripple, rock-stable
Radiation-tolerant

7. Bane of Power Supply Design
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• The jazz is in the load
• “Power supply design seldom receives the budget, expertise,
cooling, testing, or schedule that it deserves.” ~Ray Ridley
• Ensure all five before and during a project

8. First Rule of Power Supply Design
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“The first challenge in any power supply design is to gain a complete
understanding of the blocks that lie on either side of it.”
~Robert Mammano
Power Source
Load /
Useful Systems
Power Supply

9. Requirement Specifications
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Parameter Value
Input Nominal 230 Vac, 0.55 A @PF>0.9
Range: 90-265 Vac, 50-60 Hz
Outputs: Payload channel
Standby channel
12 Vdc, 8.33 A, 100 W (can be turned OFF)
5 Vdc, 2 A, 10 W (always ON)
Output voltage ripple + noise 100 mVpp for 12 V
20 mVpp for 5 V
Efficiency Overall: 80% -- AC/DC: 90%, DC/DC: 90%
TID 500 Gy
PSU dimensions (PCB + enclosure) 3U x 170 mm x 8HP i.e. 133 mm x 170 mm x 40 mm
External monitoring/control PMBus and PS_ON (for remote switching ON/OFF)
EMI specifications EN55022 Class B
Thermal environment 65⁰C ambient; No fan
[3] Detailed table of specifications: https://ohwr.org/project/psu-rad-acdc-230v-12v5v-110w/wikis/home
• Compile your list of 20-30 numbers
• Talk to users (again); Look at datasheets of similar products

10. Power Architecture and Topology Selection
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1. AC/DC: 230Vac to 48Vdc
2. 12V DC/DC: 48Vdc to 12Vdc
3. 5V DC/DC: 48Vdc to 5Vdc
4. RaToPUS: System Integration
= 1 + 2 + 3 + Monitoring + Mechanical
“The best power electronics is no power electronics.” ~Fang Z. Peng
• What is the minimum number of power stages that will do the job?

11. Topology Selection: AC/DC stage
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Vin Vo

12. Topology Selection: AC/DC stage
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PFC Boost PFC Buck
Input-side EMC filter Small Large
DC link voltage 400V 48V
DC link capacitor Small Large
MOSFET VDS rating for rad-tol DC/DC 800V (or more) 200V
MOSFET RDS,ON for rad-tol DC/DC Large Small
Inrush limiting NTC Thermistor Required Not required
Inrush current magnitude >10A 1A
Fuse for fire safety Slow blow Fast blow
[4] “Design of a 100W Radiation Tolerant Power-Factor-Correction Buck AC/DC Converter,” PCIM Europe, 2020.
https://ieeexplore.ieee.org/document/9178215
[5] Talk describing PFC Buck AC/DC design: https://www.youtube.com/watch?v=P5XJ3-uSUcA
• Compare (tables!) competing topologies relevant to the application

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• “The (boost) PFC is the most important
failure source of all devices equipped with
it. […] Power transistor failure (suspected
cause: too high inrush current and exceeded
operating temperature).” [6]
• Need special techniques to handle inrush
current problem
[6] V. Bobillier and S. Mico, “Failure analysis and lessons learned on LHC experiments crate and power
supply equipment,” Journal of Instrumentation, Feb. 2015.
[6]
PFC Boost Failures

14. Choice of DC Link Voltage
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15. Choice of DC Link Voltage
0V
- Large inrush current
- High VDSS required for MOSFET in DC/DC stage
36V
72V
100V
325V
400V
Boost
Buck
- Large crossover distortion
- Poor power factor
- High VDSS required for MOSFET in DC/DC stage
- High VDSS required for MOSFET in DC/DC stage
- Good compromise for rad-tol applications
- Very low duty cycle; Poor efficiency
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16. 300-450V
Not many options!
COTS Power MOSFETs Availability
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Data source: Farnell
For rad-tol designs
• Chances of finding a good
candidate device are more when
more options are available
• Avoid design choices that require
300-450V power MOSFETs?

17. Topology Selection: DC/DC stage
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Vin Vo
Main
MOSFET
Clamp
MOSFET

18. Topology Selection: DC/DC stage
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[7] Juan Pastrana, “Design of a 100 W Active Clamp Forward DC−DC Converter for Telecom
Systems Using the NCP1562,” ON Semiconductor Application Note.
[7]
(Conventional Forward Converter)
• Owing to its low VDS requirement,
the active clamp forward is an
excellent DC/DC topology for many
rad-tol applications (50-500W)

19. From Topology to Components
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Power Topology Get ALL waveforms (v, i)
Get ALL losses (p)
Choose active and passive components
Simulation
Calculation
Radiation Tests
Custom Magnetics
Other Modifications

20. MOSFET Under Radiation: Threshold Voltage Drift
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• Vth drifts (decreases) with TID
• Higher gate bias (Vg) ⇒ Greater Vth drift
• Vth ≤ 0 ⇒ MOSFET is uncontrollable!
Radiation test results for 800V MOSFET IPA80R280P7:
Lalit Patnaik

21. MOSFET Under Radiation: Threshold Voltage Drift
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• Vth drifts (decreases) with TID
• Higher gate bias (Vg) ⇒ Greater Vth drift
• Vth ≤ 0 ⇒ MOSFET is uncontrollable!
Radiation test results for 800 V MOSFET IPA80R280P7:
Lalit Patnaik
• VGS derating to minimize Vth drift:
Use maximum gate drive voltage of 10V

22. MOSFET Under Radiation: Single Event Burnout (SEB)
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Radiation test results for 800V MOSFET IPA80R280P7:
• No SEBs for VDS < 540 V
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• VDS derating to minimize SEB:
Operating VDS < 50% Rated VDS

23. Radiation Testing: Component-Level Tests
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• Component-level tests of COTS devices to find candidates with
➢ No/acceptable degradation with Total Ionizing Dose (TID) & Displacement Damage (DD)
➢ No catastrophic failures due to Single Event Effects (SEE)
• Challenges
➢ Huge number of components to test
➢ Large variations in test conditions vs operating conditions
➢ Availability of test facilities: proton beams, gamma irradiation…
Lalit Patnaik
Radiation testing is time and resource intensive
• Reuse already tested components from other designs

24. Radiation Testing: System-Level Tests
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• System-level tests of full PCBs
➢ To locate (and eliminate) functional failure modes
➢ To establish limits of operation (e.g. max dose)
Lalit Patnaik
Radiation testing is time and resource intensive
• Reuse radiation-test setup where possible
• Challenges:
➢ Distributed setup
➢ Poor observability

25. Examples of
Observed Failure Modes
in Radiation
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Failure Mode: Main MOSFET VDS Increases
Main
MOSFET
VDS
100V
160V
PWM pulses
To gate driver
Cause: Signal MOSFET Vth drift
Remedy:
- Find signal MOSFET with lesser Vth drift
- Use BJT based pulse delay circuit
Pulse Delay Circuit
• Beware of Vth drift in signal MOSFETs
• Beware of test conditions vs usage conditions

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Failure Mode: Spurious Tripping of
Over-Current Protection
MOSFET
Current
Sense
Cause: Increase in input bias current of comparator
Remedy:
- Find comparator with lesser bias current drift
- Reduce discharge resistor (R60) AND increase soft-start time
• Beware of input bias current drift in comparators and opamps
Ibias

28. Conclusion
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• Ensure budget, expertise, cooling, testing, schedule before and during a project
• Talk to users (again); Look at datasheets of similar products;
Compile your list of 20-30 numbers
• What is the minimum number of power stages that will do the job?
• Compare (tables!) competing topologies relevant to the application
• Avoid design choices that require 300-450V power MOSFETs?
• Owing to its low VDS requirement, the active clamp forward is an excellent
DC/DC topology for many rad-tol applications (50-500W)
• VGS derating to minimize Vth drift: Use maximum gate drive voltage of 10V
• VDS derating to minimize SEB: Operating VDS < 50% Rated VDS
• Reuse already tested components from other designs
• Reuse radiation-test setup where possible
• Beware of Vth drift in signal MOSFETs
• Beware of test conditions vs usage conditions
• Beware of input bias current drift in comparators and opamps

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Lalit Patnaik
Email: lalit.patnaik@cern.ch
Twitter: @lalitpatnaik
Thank You Very Much!

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Backup Slides

31. Power Factor Correction: Boost vs Buck
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H. Endo, T. Yamashita, and T. Sugiura, “A high-power-factor buck converter,” in Proc. IEEE Power
Electron. Spec. Conf. (PESC) Rec., Jun. 1992, pp. 1071–1076.

32. PFC Buck AC/DC Converter: Circuit Schematic
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• Po = 100 W, Vin = 90-265 Vac, Vo = 48 Vdc, Total Ionizing Dose (TID) = 300 Gy
• EMI filter: Common-mode and Differential mode
• COTS PWM Controller (Current-Mode): TL2843
B. Keogh, “Power factor correction using the buck topology,” TI Power Supply Design Seminar 2010. Lalit Patnaik

33. Active Clamp Forward DC/DC Converter:
Circuit Schematic
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