This document describes the data acquisition process and network topology for a Sercel 428XL seismic data acquisition system. It discusses how seismic data is acquired by field units, digitized, transmitted through a network of LAU nodes, and finally received and processed by the recording truck. Key components include the field digitizer units, LAU nodes, LCI recorder, and 428XL server. The data passes through various processing stages including analog to digital conversion, multiplexing, filtering, compression and error checking before being received and analyzed by the control node.
This document provides an overview of a training session on SystemVerilog for verification. The agenda includes verification planning, course contents on SystemVerilog basics and verification techniques, chip design flow, old verification languages, verification approaches, and a case study on verifying an arithmetic logic unit. Verification planning concepts like test plans, features and test types, specifications extraction, and measurements are also discussed.
Advance Microcontroller Bus Architecture(AMBA).
this is a advance bus architecture. it is defined by ARM.
all the content is taken from http://infocenter.arm.com/ website.
CHI is an evolution of the ACE protocol and part of the AMBA architecture. It was designed to improve performance and scalability for applications in mobile, networking, automotive and data center systems. CHI uses a layered architecture with protocol, network and link layers. It supports coherency across processor clusters and memory with topologies like ring, mesh and crossbar. Key nodes include request nodes, home nodes and subordinate nodes. The system address map routes transactions between nodes using unique node IDs.
IRJET- Design and Verification of APB Protocol by using System Verilog and Un...IRJET Journal
This document describes the design and verification of an AMBA APB protocol using System Verilog and Universal Verification Methodology (UVM). It begins with an introduction to AMBA and the APB bus protocol. The APB design is created in Verilog and consists of an APB bridge/master and APB slaves. The design is then verified using System Verilog and UVM testbenches. Simulation waveforms and UVM reports show the data written by the master is correctly read by the slave, indicating the APB protocol is functioning as intended.
This document discusses bootloaders for embedded systems. It defines a bootloader as the first code executed after a system powers on or resets that is responsible for loading the operating system kernel. The document then describes the tasks of a bootloader like initializing hardware, loading binaries from storage, and providing a shell. It outlines the booting process differences between desktops and embedded systems. Finally, it focuses on the universal bootloader U-Boot, describing its directory structure, configuration, building process, and commands.
Creating Your Own PCI Express System Using FPGAs: Embedded World 2010Altera Corporation
This document discusses creating PCI Express systems using FPGA devices. It provides an overview of PCI Express, describing its key functional elements like the root complex and endpoints. It also outlines PCI Express support in Altera FPGAs, including both hard IP blocks and soft IP cores that enable PCI Express connectivity. The hard IP blocks perform the various PCI Express layers and reduce resource usage compared to soft cores.
This document describes the Advanced Microcontroller Bus Architecture (AMBA) Advanced High-performance Bus (AHB) 2.0 specification. It details features of AHB such as burst transfers, split transactions, and single-cycle bus master handover. It also explains typical components in an AMBA AHB system including masters, slaves, arbitration, and bus operation with different transfer types.
This document discusses setting up a redundant LAN network. It describes what a LAN network is and the importance of network redundancy. It then provides details on various methods for implementing redundancy, including creating VPNs, using redundancy protocols like HSRP and VRRP, basic routing, MPLS routing, access lists, NAT/PAT, and configuring redundant LAN connections. The document includes configuration examples and concludes that the project was a valuable learning experience for understanding real-world networking operations.
This document provides an overview of a training session on SystemVerilog for verification. The agenda includes verification planning, course contents on SystemVerilog basics and verification techniques, chip design flow, old verification languages, verification approaches, and a case study on verifying an arithmetic logic unit. Verification planning concepts like test plans, features and test types, specifications extraction, and measurements are also discussed.
Advance Microcontroller Bus Architecture(AMBA).
this is a advance bus architecture. it is defined by ARM.
all the content is taken from http://infocenter.arm.com/ website.
CHI is an evolution of the ACE protocol and part of the AMBA architecture. It was designed to improve performance and scalability for applications in mobile, networking, automotive and data center systems. CHI uses a layered architecture with protocol, network and link layers. It supports coherency across processor clusters and memory with topologies like ring, mesh and crossbar. Key nodes include request nodes, home nodes and subordinate nodes. The system address map routes transactions between nodes using unique node IDs.
IRJET- Design and Verification of APB Protocol by using System Verilog and Un...IRJET Journal
This document describes the design and verification of an AMBA APB protocol using System Verilog and Universal Verification Methodology (UVM). It begins with an introduction to AMBA and the APB bus protocol. The APB design is created in Verilog and consists of an APB bridge/master and APB slaves. The design is then verified using System Verilog and UVM testbenches. Simulation waveforms and UVM reports show the data written by the master is correctly read by the slave, indicating the APB protocol is functioning as intended.
This document discusses bootloaders for embedded systems. It defines a bootloader as the first code executed after a system powers on or resets that is responsible for loading the operating system kernel. The document then describes the tasks of a bootloader like initializing hardware, loading binaries from storage, and providing a shell. It outlines the booting process differences between desktops and embedded systems. Finally, it focuses on the universal bootloader U-Boot, describing its directory structure, configuration, building process, and commands.
Creating Your Own PCI Express System Using FPGAs: Embedded World 2010Altera Corporation
This document discusses creating PCI Express systems using FPGA devices. It provides an overview of PCI Express, describing its key functional elements like the root complex and endpoints. It also outlines PCI Express support in Altera FPGAs, including both hard IP blocks and soft IP cores that enable PCI Express connectivity. The hard IP blocks perform the various PCI Express layers and reduce resource usage compared to soft cores.
This document describes the Advanced Microcontroller Bus Architecture (AMBA) Advanced High-performance Bus (AHB) 2.0 specification. It details features of AHB such as burst transfers, split transactions, and single-cycle bus master handover. It also explains typical components in an AMBA AHB system including masters, slaves, arbitration, and bus operation with different transfer types.
This document discusses setting up a redundant LAN network. It describes what a LAN network is and the importance of network redundancy. It then provides details on various methods for implementing redundancy, including creating VPNs, using redundancy protocols like HSRP and VRRP, basic routing, MPLS routing, access lists, NAT/PAT, and configuring redundant LAN connections. The document includes configuration examples and concludes that the project was a valuable learning experience for understanding real-world networking operations.
The document discusses interrupts in Linux systems. It defines interrupts as interventions that allow devices to get the CPU's attention when there is a mismatch between device and CPU speeds. It describes how interrupts work through interrupt lines, an interrupt controller, and registered interrupt handlers. It covers interrupt request numbers, programming interfaces for requesting and freeing interrupts, the responsibilities of interrupt handlers, and additional features like message signaled interrupts and soft interrupts, which are used to break up interrupt handling work.
The document provides an overview of the responsibilities and functions of the Genie-PCIe data link layer. The data link layer is responsible for reliable transmission of transaction layer packets (TLPs) between the physical and transaction layers. It handles flow control initialization, sequencing, buffering, error detection and recovery for transmitted TLPs using ACK/NAK protocols and data link layer packets (DLLPs). The data link control state machine manages the link status and ensures proper initialization and maintenance of the link.
Presentation discusses Issues in modeling bidirectional buses such as USB 2.0. Solutions for common issues are shown through pictures and verilog code.
This presentation describes the term firewall and it's concepts and provides basic information about it's unix-based software implementations: ebtables, arptables and iptables. This document is a part of a powerpoint presentation which I also uploaded. Made as a project for university course
TLM interfaces provide higher-level abstraction, reusability, maintainability, and faster simulation compared to lower-level data transfer methods. TLM supports operations like putting, getting, and peeking data between a producer and consumer. It can also broadcast transactions to multiple consumers. Examples demonstrate how TLM implements non-blocking calls to transfer data at a higher level of abstraction than port-based approaches while maintaining independence between components.
The document provides an overview of the UVM configuration database and how it is used to store and access configuration data throughout the verification environment hierarchy. Key points include: the configuration database mirrors the testbench topology; it uses a string-based key system to store and retrieve entries in a hierarchical and scope-controlled manner; and the automatic configuration process retrieves entries during the build phase and configures component fields.
Project implements a complex intra-networking system of various devices and modules working on IPv4 and IPv6 protocols providing various services like DNS, DHCP, HTTP, FTP, and SMTP. Information is routed among various client on the network with the use of protocols RIP, IMAP and OSPF. Project comprises of sub-netting, LAN switching and VLAN techniques to manage the number of hosts present in the network communicating with least network collision and congestion.
This chapter discusses path control implementation using Cisco technologies. It covers Cisco Express Forwarding (CEF) switching and how it improves performance over process and fast switching. It also discusses using policy-based routing (PBR) and Cisco IOS IP SLAs to implement path control and dynamically change paths based on network conditions. The chapter provides configuration examples for PBR and IP SLAs to control traffic flow.
Unit Testing contains Concept of Unit Testing, Static Unit Testing, Dynamic Unit Testing, steps for Static Unit Testing, Test Driver, Stub, selection of Data for Unit Testing, etc...
The document provides an introduction and overview of the Verilog PLI (Programming Language Interface). It discusses what the Verilog PLI is, where it is useful, the fundamentals of how it works including the different PLI libraries (TF, ACC, VPI), and how to integrate C files with Verilog files for use with the PLI.
This document provides an overview of the verification strategy for PCI-Express. It discusses the PCI-Express protocol, including the physical, data link, transaction, and software layers. It outlines the verification paradigm, including functional verification using constrained random testing, assertions, asynchronous/power domain simulations, and performance verification. It also discusses compliance verification through electrical, data link, transaction, and system architecture checklists. Finally, it discusses design for verification through a modular and scalable architecture to promote reusability and reduce verification effort and complexity.
The document discusses the network layer in the OSI model. It describes the key responsibilities of the network layer, including addressing, routing data between end devices, and allowing communication between different networks. The most common network layer protocol is the Internet Protocol (IP), which uses addresses and best-effort delivery to route packets to their destinations. IP packets contain source and destination addresses, and may be routed through multiple networks using hierarchical addressing schemes, routers, and routing tables maintained by routing protocols. Network testing tools like ping and traceroute allow engineers to diagnose connectivity issues.
The document is a slide presentation about running Linux on IBM Power systems. It discusses why Linux is widely used, best practices for installing and configuring Linux on Power systems, and options for deploying Linux workloads including the Integrated Facility for Linux (IFL). The IFL allows customers to activate unused cores and memory on Power 770, 780, and 795 systems running only Linux at a lower cost than other hardware platforms.
This document discusses challenges in using the Universal Verification Methodology (UVM) at the system-on-chip (SoC) level and proposes solutions. It outlines key features of UVM, then describes challenges like lack of control over UVM verification components from C code and difficulty reusing test cases across different levels. The document proposes a wrapper to connect UVM and SystemC ports and adds a TLM export and register-controlled sequence to allow processor control over sequences. It demonstrates controlling a sequence from a processor through this interface. Finally, it discusses areas like seamless UVM-SystemC connections that could be improved in future UVM versions.
The document provides instructions for configuring initial settings on a Cisco network device using Cisco IOS software, including configuring hostnames, limiting access to device configurations through passwords, and saving the running configuration. It describes assigning a unique hostname, securing privileged EXEC mode with the enable secret password, securing the console and virtual terminal lines with passwords and login, and using the service password-encryption command to encrypt passwords.
Multicast routing configuration and lab example in MikroTik
video multicast routing 1 router
https://www.youtube.com/watch?v=nqUlUIB93Mg
video multicast routing 2 router over wireless
https://www.youtube.com/watch?v=eYEocGYsGZ4
Konfig VLC sebagai stream server multicast
https://www.youtube.com/watch?v=Z1lthcBSSrM
Konfig VLC sebagai player
https://www.youtube.com/watch?v=s2uTs8NRQpY
Cisco Live! :: Introduction to IOS XR for Enterprises and Service ProvidersBruno Teixeira
The document provides an overview of an introductory session on IOS XR for enterprises and service providers. It outlines the agenda which includes discussing IOS XR architecture, modularity, scalability, stability, security, software packages, the command line interface, configuration management, monitoring tools, example configurations, and the route policy language. It also provides some logistical information about the session.
The document proposes Ethernet VPN (E-VPN) as a solution to overcome scaling challenges with the existing Virtual Private LAN Service (VPLS) technology. E-VPN uses MPLS and BGP to transport layer 2 connectivity between data centers. It treats MAC addresses as routable addresses and uses MP-iBGP to distribute customer MAC addresses between edge routers. This allows for remote MAC learning and helps scale to thousands of MAC addresses. The document also describes how E-VPN uses Ethernet Segment IDs and split horizon labels to avoid layer 2 loops in multi-homing scenarios.
This document provides an overview of IPv6 fundamentals, including:
- Key differences between IPv4 and IPv6 such as larger addressing space and elimination of NAT.
- Details of the IPv6 header format and use of extension headers for additional functions.
- The IPv6 addressing architecture including the various address types and formats.
- Protocols for autoconfiguration, neighbor discovery, and multicast in IPv6 networks.
The document discusses CRC and transmit errors in a Sercel 428XL seismic data acquisition system. It describes how the system uses synchronous and asynchronous communication protocols to transmit seismic sample data from field acquisition units to recording nodes. CRC checks are used to detect errors during synchronous communication, while retransmission protocols are used during asynchronous transmission between nodes. The predictive algorithm aims to minimize the impact of CRC errors by replacing corrupted samples with previous values.
This document presents a method for parallel CRC computation that improves on previous approaches. It derives a recursive formula from the polynomial generator degree that allows generation of parallel CRC circuits independently of the technology used. The approach generates an F-matrix from the polynomial that is used to design circuits for processing multiple bits in parallel. Simulation results show the parallel CRC circuits can process data faster than serial LFSR approaches, with 64-bit parallel processing achieving the fastest speed. The method provides a customizable solution for building parallel CRC hardware across different polynomial generators and data widths.
The document discusses interrupts in Linux systems. It defines interrupts as interventions that allow devices to get the CPU's attention when there is a mismatch between device and CPU speeds. It describes how interrupts work through interrupt lines, an interrupt controller, and registered interrupt handlers. It covers interrupt request numbers, programming interfaces for requesting and freeing interrupts, the responsibilities of interrupt handlers, and additional features like message signaled interrupts and soft interrupts, which are used to break up interrupt handling work.
The document provides an overview of the responsibilities and functions of the Genie-PCIe data link layer. The data link layer is responsible for reliable transmission of transaction layer packets (TLPs) between the physical and transaction layers. It handles flow control initialization, sequencing, buffering, error detection and recovery for transmitted TLPs using ACK/NAK protocols and data link layer packets (DLLPs). The data link control state machine manages the link status and ensures proper initialization and maintenance of the link.
Presentation discusses Issues in modeling bidirectional buses such as USB 2.0. Solutions for common issues are shown through pictures and verilog code.
This presentation describes the term firewall and it's concepts and provides basic information about it's unix-based software implementations: ebtables, arptables and iptables. This document is a part of a powerpoint presentation which I also uploaded. Made as a project for university course
TLM interfaces provide higher-level abstraction, reusability, maintainability, and faster simulation compared to lower-level data transfer methods. TLM supports operations like putting, getting, and peeking data between a producer and consumer. It can also broadcast transactions to multiple consumers. Examples demonstrate how TLM implements non-blocking calls to transfer data at a higher level of abstraction than port-based approaches while maintaining independence between components.
The document provides an overview of the UVM configuration database and how it is used to store and access configuration data throughout the verification environment hierarchy. Key points include: the configuration database mirrors the testbench topology; it uses a string-based key system to store and retrieve entries in a hierarchical and scope-controlled manner; and the automatic configuration process retrieves entries during the build phase and configures component fields.
Project implements a complex intra-networking system of various devices and modules working on IPv4 and IPv6 protocols providing various services like DNS, DHCP, HTTP, FTP, and SMTP. Information is routed among various client on the network with the use of protocols RIP, IMAP and OSPF. Project comprises of sub-netting, LAN switching and VLAN techniques to manage the number of hosts present in the network communicating with least network collision and congestion.
This chapter discusses path control implementation using Cisco technologies. It covers Cisco Express Forwarding (CEF) switching and how it improves performance over process and fast switching. It also discusses using policy-based routing (PBR) and Cisco IOS IP SLAs to implement path control and dynamically change paths based on network conditions. The chapter provides configuration examples for PBR and IP SLAs to control traffic flow.
Unit Testing contains Concept of Unit Testing, Static Unit Testing, Dynamic Unit Testing, steps for Static Unit Testing, Test Driver, Stub, selection of Data for Unit Testing, etc...
The document provides an introduction and overview of the Verilog PLI (Programming Language Interface). It discusses what the Verilog PLI is, where it is useful, the fundamentals of how it works including the different PLI libraries (TF, ACC, VPI), and how to integrate C files with Verilog files for use with the PLI.
This document provides an overview of the verification strategy for PCI-Express. It discusses the PCI-Express protocol, including the physical, data link, transaction, and software layers. It outlines the verification paradigm, including functional verification using constrained random testing, assertions, asynchronous/power domain simulations, and performance verification. It also discusses compliance verification through electrical, data link, transaction, and system architecture checklists. Finally, it discusses design for verification through a modular and scalable architecture to promote reusability and reduce verification effort and complexity.
The document discusses the network layer in the OSI model. It describes the key responsibilities of the network layer, including addressing, routing data between end devices, and allowing communication between different networks. The most common network layer protocol is the Internet Protocol (IP), which uses addresses and best-effort delivery to route packets to their destinations. IP packets contain source and destination addresses, and may be routed through multiple networks using hierarchical addressing schemes, routers, and routing tables maintained by routing protocols. Network testing tools like ping and traceroute allow engineers to diagnose connectivity issues.
The document is a slide presentation about running Linux on IBM Power systems. It discusses why Linux is widely used, best practices for installing and configuring Linux on Power systems, and options for deploying Linux workloads including the Integrated Facility for Linux (IFL). The IFL allows customers to activate unused cores and memory on Power 770, 780, and 795 systems running only Linux at a lower cost than other hardware platforms.
This document discusses challenges in using the Universal Verification Methodology (UVM) at the system-on-chip (SoC) level and proposes solutions. It outlines key features of UVM, then describes challenges like lack of control over UVM verification components from C code and difficulty reusing test cases across different levels. The document proposes a wrapper to connect UVM and SystemC ports and adds a TLM export and register-controlled sequence to allow processor control over sequences. It demonstrates controlling a sequence from a processor through this interface. Finally, it discusses areas like seamless UVM-SystemC connections that could be improved in future UVM versions.
The document provides instructions for configuring initial settings on a Cisco network device using Cisco IOS software, including configuring hostnames, limiting access to device configurations through passwords, and saving the running configuration. It describes assigning a unique hostname, securing privileged EXEC mode with the enable secret password, securing the console and virtual terminal lines with passwords and login, and using the service password-encryption command to encrypt passwords.
Multicast routing configuration and lab example in MikroTik
video multicast routing 1 router
https://www.youtube.com/watch?v=nqUlUIB93Mg
video multicast routing 2 router over wireless
https://www.youtube.com/watch?v=eYEocGYsGZ4
Konfig VLC sebagai stream server multicast
https://www.youtube.com/watch?v=Z1lthcBSSrM
Konfig VLC sebagai player
https://www.youtube.com/watch?v=s2uTs8NRQpY
Cisco Live! :: Introduction to IOS XR for Enterprises and Service ProvidersBruno Teixeira
The document provides an overview of an introductory session on IOS XR for enterprises and service providers. It outlines the agenda which includes discussing IOS XR architecture, modularity, scalability, stability, security, software packages, the command line interface, configuration management, monitoring tools, example configurations, and the route policy language. It also provides some logistical information about the session.
The document proposes Ethernet VPN (E-VPN) as a solution to overcome scaling challenges with the existing Virtual Private LAN Service (VPLS) technology. E-VPN uses MPLS and BGP to transport layer 2 connectivity between data centers. It treats MAC addresses as routable addresses and uses MP-iBGP to distribute customer MAC addresses between edge routers. This allows for remote MAC learning and helps scale to thousands of MAC addresses. The document also describes how E-VPN uses Ethernet Segment IDs and split horizon labels to avoid layer 2 loops in multi-homing scenarios.
This document provides an overview of IPv6 fundamentals, including:
- Key differences between IPv4 and IPv6 such as larger addressing space and elimination of NAT.
- Details of the IPv6 header format and use of extension headers for additional functions.
- The IPv6 addressing architecture including the various address types and formats.
- Protocols for autoconfiguration, neighbor discovery, and multicast in IPv6 networks.
The document discusses CRC and transmit errors in a Sercel 428XL seismic data acquisition system. It describes how the system uses synchronous and asynchronous communication protocols to transmit seismic sample data from field acquisition units to recording nodes. CRC checks are used to detect errors during synchronous communication, while retransmission protocols are used during asynchronous transmission between nodes. The predictive algorithm aims to minimize the impact of CRC errors by replacing corrupted samples with previous values.
This document presents a method for parallel CRC computation that improves on previous approaches. It derives a recursive formula from the polynomial generator degree that allows generation of parallel CRC circuits independently of the technology used. The approach generates an F-matrix from the polynomial that is used to design circuits for processing multiple bits in parallel. Simulation results show the parallel CRC circuits can process data faster than serial LFSR approaches, with 64-bit parallel processing achieving the fastest speed. The method provides a customizable solution for building parallel CRC hardware across different polynomial generators and data widths.
The document discusses physical layer data transmission and signals. It covers topics like analog vs digital signals, periodic vs non-periodic signals, properties of signals like amplitude, frequency, period, phase, and bandwidth. It also discusses signal representation and analysis in the time and frequency domains, including Fourier analysis which shows how composite signals can be decomposed into simpler sine waves.
TCP provides reliable data transfer through several key features:
- It numbers data bytes and uses acknowledgments to ensure all bytes are received correctly. If bytes are lost, they are retransmitted.
- Congestion control algorithms like slow start and congestion avoidance allow TCP to gradually increase data transfer rates while avoiding overwhelming the network.
- Fast retransmit detects lost packets sooner by retransmitting on three duplicate ACKs, while fast recovery resumes data transfer using ACKs still in the pipe.
This document summarizes circuit switching and packet switching techniques in communications networks. It discusses how circuit switching establishes a dedicated physical path between communicating nodes but is inefficient for bursty traffic. Packet switching breaks messages into packets that are transmitted over shared links, improving efficiency. Key aspects covered include virtual circuits, datagrams, packet switching advantages, X.25 standards, and how Frame Relay improved on X.25 by reducing overhead.
The document discusses data link control and framing in computer networks. It describes two main functions of the data link layer: defining frames and performing error detection on frames. It also discusses different types of framing such as fixed-size framing and variable-size framing using character-oriented and bit-oriented protocols. Specific protocols discussed include Stop-and-Wait ARQ which uses positive acknowledgments and retransmissions, and Go-Back-N ARQ which allows for pipelining of multiple frames before requiring an acknowledgment.
Abstract - The Transmission Control Protocol (TCP) is
connection oriented, reliable and end-to-end protocol that support
flow and congestion control, with the evolution and rapid growth
of the internet and emergence of internet of things IoT, flow and
congestion have clear impact in the network performance. In this
paper we study congestion control mechanisms Tahoe, Reno,
Newreno, SACK and Vegas, which are introduced to control
network utilization and increase throughput, in the performance
evaluation we evaluate the performance metrics such as
throughput, packets loss, delivery and reveals impact of the cwnd.
Showing that SACK had done better performance in terms of
numbers of packets sent, throughput and delivery ratio than
Newreno, Vegas shows the best performance of all of them.
This document discusses various topics related to Long Term Evolution (LTE) including call flow, radio link failure, discontinuous reception (DRX), paging, scheduling, random access channel (RACH) procedure, self-organizing networks (SON), and quality of service (QoS). It provides details on the call flow process when a user equipment (UE) is powered on, performs initial cell selection and attachment, and establishes a default bearer. It also describes procedures for radio link failure, DRX, paging, scheduling, RACH, SON functions including self-configuration and optimization, and QoS with default and dedicated bearers.
The document discusses 5G new radio (NR) physical layer resources including numerology, time-domain resources, frequency-domain resources, and space-domain resources. It provides details on key 5G NR concepts such as subcarrier spacing, symbols, slots and frames. Cyclic prefix length is determined based on subcarrier spacing to maintain consistent overhead. Slot formats in 5G NR provide more flexibility with symbol level uplink/downlink switching compared to LTE.
The document describes experiments performed on time division multiplexing, pulse code modulation, differential pulse code modulation, delta modulation, frequency shift keying, and differential phase shift keying. The experiments aim to study the principles and characteristics of these digital communication techniques by using equipment like multiplexing/demultiplexing trainer kits, PCM modulator and demodulator kits, and oscilloscopes. The procedures involve applying input signals, observing the output waveforms on oscilloscopes, and analyzing the effects of varying signal parameters.
The document describes two FPGA projects using HDL:
1. Salt and pepper noise removal from images using a median filter optimized for FPGA hardware. The filter reduces comparison times by 40% over traditional algorithms.
2. Generation of pulse-width modulation (PWM) signals using a counter and comparator on an FPGA. A 25% duty cycle PWM signal is successfully generated to control devices.
The document provides details on the hardware design, VHDL code modules, and testing of both projects. Real-time filtering of 1Kx1K images and MATLAB simulation of PWM generation are demonstrated. Guidelines for efficient HDL coding suited for FPGA implementation are also listed.
The document provides an overview of LTE (Long Term Evolution) Release 8. It discusses key requirements for LTE such as supporting high data rates, low latency, and an all-IP network. It describes the network architecture including components like eNodeB, MME, S-GW, and P-GW. It also covers functionality of these components and the protocol stack consisting of PDCP, RLC, MAC, and RRC layers. Mobility management, QoS, and comparisons to other technologies like HSPA+ and WiMAX are also summarized.
This document discusses TCP over wireless networks. It explains that TCP was designed for fixed networks with low delay and errors, but wireless networks have high delay, errors and variable bandwidth. This causes TCP to perform poorly over wireless. The document outlines various techniques to improve TCP performance over wireless like Fast Retransmit and Recovery, Slow Start proposals with larger initial windows, ACK counting and ACK-every-segment. It also discusses protocols like HTTP, RLP that operate between TCP and the wireless transmission layers.
The document provides an overview of ZigBee/IEEE 802.15.4 wireless technology. It discusses the need for low-power, low-cost wireless connectivity for applications like home automation, medical devices, and industrial sensors. It describes the ZigBee Alliance's role in developing networking and application standards on top of the IEEE 802.15.4 physical radio specification. Key features of ZigBee networks include low power consumption, large network capacity, low data rates, and flexibility for many applications.
This chapter discusses digital control systems, including their components and operation. Digital control systems consist of a digital controller, analog to digital converter (ADC), and digital to analog converter (DAC). The ADC converts analog signals from sensors into digital signals for the controller. The controller processes the digital signals and outputs digital signals to the DAC. The DAC then converts the digital outputs back into analog signals to act on the physical system. Key aspects covered include comparing analog and digital control loops, describing the operation of ADCs and DACs, and selecting appropriate sampling frequencies to avoid signal distortion.
A New Multi-Channel MAC Protocol With On-Demand Channel Assignment For Multi-...Steven Wallach
This document proposes a new multi-channel MAC protocol for mobile ad hoc networks that uses an on-demand approach to dynamically assign channels. It aims to address problems like hidden terminals and channel deadlocks that can occur with multi-channel protocols. The protocol uses two transceivers per node - one for control and one for data. Nodes exchange RTS, CTS, and RES control packets to negotiate channel assignments. Analysis and simulation results show that the protocol increases throughput and utilization compared to single-channel protocols, and its performance improves as the number of channels and data packet length increases. The authors are working to extend the protocol to use reservation-based channel access.
This document discusses high-speed serial I/O design challenges for chip-to-chip communication systems. As processing power increases, data rates must also increase between chips but electrical channels limit this scaling. Channel loss and reflections distort signals, necessitating equalization techniques. While I/O circuits can achieve high data rates, power constraints also limit scaling. Future optical interconnects may overcome these limitations and fully leverage increased processing bandwidths.
This document summarizes a lecture on computer networks and error control. It discusses topics like Hamming codes, cyclic redundancy checks (CRCs), stop-and-wait protocols, automatic repeat request (ARQ) protocols, and sliding window protocols. The reading assignment is chapter 3 of the Tanenbaum textbook and the lecture will cover error control, error and flow control, and how layer 2 protocols implement these functions using frames, headers, trailers, and checksums.
This document discusses various topics related to the Public Switched Telephone Network (PSTN), including:
1) Switching types like circuit switching and packet switching, as well as connection-oriented and connectionless networks.
2) PSTN exchanges and interfaces, including interfaces for access networks and trunk networks using signaling protocols.
3) Functions of the local exchange like maintenance, operations, user services, and examples of intelligent network services.
- A switch is a multi-input, multi-output device that transfers packets from an input to one or more outputs, allowing links to be interconnected to form a larger network.
- There are two main types of switching: circuit switching establishes a dedicated end-to-end path before information transfer, while packet switching involves intermediate nodes storing incoming data blocks and retransmitting them along the path to the destination.
- X.25 is a widely used packet switching protocol that defines how a terminal connects to a packet network and how packets are exchanged over that network using devices like modems and packet switches.
The document provides information about land seismic oil exploration techniques, including 2D and 3D seismic data collection and processing. It discusses using explosive sources like dynamite or vibratory sources like vibrators to generate seismic waves that reflect off underground formations. The reflected data is recorded and processed to create seismic profiles that show subsurface rock layer structures and potential oil and gas reservoirs. Hydraulic fracturing, a controversial technique for stimulating oil and gas production from shale formations, is also briefly mentioned.
This document provides an overview of fiber optics including definitions, key elements, light wave propagation, fiber optic classification and applications. It discusses the core and cladding, numerical aperture, monomode vs multimode fibers, fiber composition including plastic, glass and applications in networking, communications, internet, telephony, CATV and military uses. It also outlines advantages such as low attenuation, size and weight benefits as well as disadvantages including complex splicing and high cost equipment requirements.
This document provides an overview of health and safety considerations for the oil and gas industry. It discusses unsafe acts and conditions, management systems for health and safety, personal protective equipment, electrical safety, lockout/tagout procedures, walking surfaces, ladders, scaffolds, violence in the workplace, first aid, fires, radiation, and emergency contingency planning. The management system section describes planning, performing, assessing, and improving health and safety. Personal protective equipment responsibilities and training are outlined. Electrical safety responsibilities include hazard identification and protective equipment. Lockout/tagout procedures provide energy isolation. [END SUMMARY]
This document discusses health and safety in the oil and gas industry. It covers several topics:
- Management systems for health and safety with planning, performance, assessment, and improvement.
- Personal protective equipment (PPE) including responsibilities, hazard assessment, protective clothing, and training.
- Electrical safety including responsibilities, hazards, flash hazard analysis, and qualifications.
- Control of hazardous energy sources including lockout procedures.
- Emergency contingency planning including different plans for shelter in place, administrative closings, and occupant emergencies.
This document provides an outline for a curriculum vitae (CV) that focuses on self-management and human talent. The CV outline includes sections for personal information, competencies and skills, academic qualifications, languages, thesis project, special mentions, social networks, courses and trainings, and miscellaneous experience. The document suggests considering how recruiters will review the CV and managing its length. It also recommends targeting the CV at local, national, and international settings.
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CRC AND TRANSMIT ERROR REPORT
1. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
1
CRC & TRANSMIT ERROR
Introduction:
The land seismic theory and operations are about producing an excitation (by a source) to the land and
“listening” (Travel Time) the wave from the “objective” to the surface.
How this wave is acquired and transmitted is a very complex process which involves:
Analog to Digital Conversion,
Multiplexing and Demultiplexing,
Sigma-Delta Filter Application,
Convolution process,
Communications protocols (TCP-IP; Ethernet) and so many
others stages that we are going to cover during this
presentation.
This document is based on a Sercel System Model 428XL.
In the Appendix are explained all the concepts marked as A#XX
2. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
2
THE SEISMIC SERCEL NETWORK
The complete system can be described into 4 nodes:
1. Control Node: Server and Human Control Interface (e428 Client Software)
2. Recorder Node: LCI
3. Data Buffer Node: LAUX, LAUL, LRU
4. Acquisition Node: FDU, DSU3, DSU1.
A. The samples of seismic data are always from the Acquisition Node to the Data Buffer Node.
B. The samples are analyzed and compressed by the Data Buffer Node and finally sent directly to
the Control Node through the Asynchronous protocol.
C. The status and result are sent to the Recorder Node for analysis through the asynchronous
protocol too.
Communication Protocol:
Communication between LAU and FDU:
On Line only @ 8 or 16 [Mbps].
Use SYNCHRONOUS COMMUNICATION.
LAU Master to FDU: Commands
FDU to LAU Slave: Seismic Data and Status.
Communication between LAU or LCI and LAU
On Line or Transverse @ 8 or 16 [Mbps].
Use ASYNCHRONOUS COMMUNICATION.
Full duplex. (A#1).
Automatic routing.
Broadcast possibilities.
Multi-Transverse possibilities
CRC Error Checking.
3. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
3
The protocol used on Line and secondary Transverse @ 8 or 16 [Mbps] is a TCP IP protocol.
The TCP IP protocol description: The TCP/IP Protocol can be split into 4 layers as an standard TCP IP
Protocol, so:
Layer 1:
PHYSICALL Layer:
Interface between Hardware and Software Communication
between 2 adjacent LAU’s.
Encode cells.
Packet CRC checking.
Layer 2:
Data Link Layer:
Point to Point communication (P2P).
Communication between 2 adjacent LAU’s.
Frame management.
Frame CRC Checking.
Layer 3:
NETWORK Layer:
Routing management.
Communication between 2 Lau’s or LCI or Server.
Packets management.
Layer 4:
TRANSPORT Layer:
Communication between 2 Lau’s or LCI or Server
Message management by MULTIPLEXING / DEMULTIPLEXING
(A#2)
4. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
4
ENCAPSULATION OF THE DATA:
16 [Mbps] Frame
The 16[Mbps] frame is used in the Line
The protocol used on the Transverse @ 100 [Mbps] is a STANDARD EHTERNET
PROTOCOL.
Module’s Description and Basic Connections:
Done in the LCI:
- Interfacing with the links.
- Generating the Firing Order and sensing the Time Break.
- Seismic line management and control.
- Auxiliary links control.
- Collecting system status data to be returned to the HCI (Human Control Interface).
Done in the 428XL Server (PRM and HCI applications)
- Collecting the data from the links (Done by the Server).
- Noise editing (Zeroing/Clipping/Diversity Stack).
- Correlation and Stacking.
5. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
5
Pipeline Architecture:
The block handles the data as a pipeline.
They are able to process the data from different acquisitions at the same time.
This Allow the 428XL to offer a zero dead time. I.E.: no delay between
consecutive acquisitions. As a result, the vibrator drivers and dynamite shooters
do not have to wait for the system to be ready!
LCI Architecture
It contains three boards:
a. LPBX: Blaster Board Interface.
b. LPWX: Power Management Board.
c. LPXL: Line and Transverse Management.
a. LPBX: Blaster Board Interface:
- This board manages the Synchronization of the spread.
- This clock is tuned @ 16,384[MHz] +/- 1 ppm (1 part per million).
Main components used on LPBX:
- TCXO: 16,384[MHz] Reference Clock for Line Synchronization.
- TCXO2: 17,920[MHz] Reference Clock for DPG Synchronization.
b. LPWX: Power Management Board:
- Manages all the different power supply need by the other cards.
- Uses MosFet Transistor Technology:
The advantages of using this technology are:
Allows to manage a very high frequency for the power supply.
Reduction in the working temperature.
Reduction of components size.
c. LPXL: Line and Transverse Management:
- The board is able to manage the communication through the LINE and the TRANSVERSE.
Important:
Remind that the LINE speed is 8[Mbps] or 16[Mbps] and TRANSVERSE speed is
100[Mbps].
The Flash Memory that the LCI has contains all the programs for the DSP, FPGA and IBM.
6. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
6
DATA Exchange between LINE – LCI – 428XL Server
For the SlipSweep + Navigation the Default Mode is Continuous Asynchronous Mode.
Acquisition Modes:
- An Acquisition is a set of Elementary Acquisitions
- The Elementary Acquisition is always started by a T0 and the length of this Elementary Acquisition
is limited.
- In the Asynchronous Mode (SLIPSWEEP MODE) for the FIRST T0 the LAU SYNCHRONIZE the
Acquisition and for the following T there’s no re-synchronization.
- In case of Error found by the LAU during the Acquisition, the only solution is to reset the LAU
MEMORY is an Abort from Operator then apply LINE OFF/ON.
Retrieve Mode: The Continuous Asynchronous Mode will be the default mode for the 428XL.
Errors Management:
On Samples – Overscalling:
An error message is able to be generated every 16 samples. What’s
more, the PRM application will do a summary of the error for the complete Acquisition.
On Acquisition – AcqError due to link unplugged during Acquisition:
An Error message is able to be generated every 16 samples.
The LAU will not transmit the blocks (16 samples) of the default traces.
The Samples value missed are replaced by the value 0
On LAU Memory – Memory Overflow:
All traces concerned by the trouble are non-valid.
Acquisition synchronization trouble – T0 too Early: Non applicable for SlipSweep Mode.
Transmission Error During Retrieve - Transmit Time-out: the Operator has the possibility to
Retry, Cancel, or Record the Retrieve.
7. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
7
Topology for the Sercel Land Equipment
The SPREAD includes:
- FDU
- LAUL
- LAUX
- Recording Truck: LCI, Server, Etc.
FDU – FIELD DIGITIZER UNIT
The main role of the FDU is to DIGITIZES the Seismic Data.
The FDU CONVERTS the analog data coming from the geophone to a digital one and send the digital
data to the LAUL after that, the data will go to the LAUX and finally to the LCI.
The Analog to Digital conversion is based on a SIGMA DELTA CONVERTER which works @ 256 [KHz].
The output from the Sigma Delta Converter is a sample of 24 bits @ 4 [KHz] frequency (The 4[KHz]
frequency is due to the sample rate of 0.25[ms], so f= 1/0.25[ms]= 4 [KHz]).
8. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
8
FDU MAIN COMPONENTS:
a. Power Supply that generates 6.3[v] for the analog part of the board and 2.7[V] for the digital
one.
b. FDU-INT that reshapes the signal, and contains the 2 PLL’s (A#3) used to synchronize the FDU
c. FDU-COM that manages the communication with the LAUL, processes the data: performs a first
decimation (rate 64) from 256[KHz] to 4 [Khz] and manages the other functions.
d. Sigma-Delta Converter that converts the analog signal from the geophone to a digital bit stream
@ 256 [KHz].
e. EEPROM contains the FDU’s identity and the calibration parameters.
Initialization Sequences
The INITIALIZATION is done once the FDU is power-on. The process consists
in 4 steps:
- CLOCK SYNCHRONIZATION: The PLL’s in the FDU-INT are synchronized with the data clock @
8.192[MHz] or 16.384[MHz].
- ALIGNMENT: The FDU-COM detects the beginning of the data frames. The FDU can now interpret
the orders coming from the equipment.
- ORIENTATION PHASE: As the FDU can be connected either way, so, an automatic internal
orientation is done at this stage in order to select the active and passive pair.
- INITIALIZATION TESTS: Field test of the string and Instrument Tests.
Seismic Data Path
The data is scrambles to transfer white noise (A#4) on the line, to have a better synchronization of the
field units.
9. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
9
A CRC IS INSERTED TO ENABLE THE LAU TO DETECT ANY TRANSMISSION TROUBLE
Geophone Data Path
The analog data is converted into a 24 bits with a 0.25[ms] Sample Rate (SR) and then sent to the LAUL
where it is filtered (linear or minimum phase filter), decimated, compressed and sent to the CM.
FDU
A phase comparison between the data and the clock (output of the VCO (1)) is done.
Then the voltage generated by the phase comparator (2) is filtered and amplified before being applied
to the VCO.
According the input of the VCO (Tension or Voltage value), the VCO delivers a new signal with a new
frequency.
The comparison is done until the phase comparison is not null.
In each LAUL an additional PLL performs and extra jitter filtering (A#5) in the forward path.
The clock Synchronization circuitry is also implemented in the LAUL, LAUX, and LCI
10. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
10
ACQUISITION CHANNEL CIRCUITRY
Definition:
ADC Analog to Digital Converter, a device that will convert an analog signal into a digital one.
DSP (A#6) Digital Signal Processing.
Description: The signal acquisition circuitry is composed by the following four circuits:
Input filter (FDU): Performing initial high-cut filtering and some noise cancellation.
Modulators (FDU): Consisting of a Delta Sigma (∑-Δ) Analog to Digital converter (∑-Δ ADC).
Delay Memory (Used in LAU Slave): Consisting of a RAM used to provide temporary storage
for signal processing and remove the sample skew by synchronizing the start acquisition.
It is important to take into account that the RAM (Random Access Memory) is cleared (all data is
deleted) once the line status is power-off.
Digital Signal Processors (FDU and used in LAU Slave): Removing all that is of no use
(including the quantization noise and high frequency components.
11. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
11
Analog to Digital Converter (ADC) – How it works:
Conventional ADC: Any ADC will take the value of the analogue signal at the time t and will convert it
to a digital value (here 4.5v). Then it will do the same at time t+1 (here 1.25V) and so on:
Aliasing Effect:
In the example below we assume Fmax is the maximum frequency in the signal spectrum.
So, Fs/2 must be greater that Fmax (Fs>2Fmax), this is in order to AVOID ALIASING EFFECT.
In case of aliasing, the original signal cannot be recovered.
12. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
12
Quantization Error: Assuming that a properly sampled signal like the one showed in below.
The conversion from an analog signal to a digital one gives a quantization error.
Let’s analyze an example with 8 bits: 8 bits allow us to read 28
. Then we will have 256 different values
on a 5[V] Scale.
This means that the quantization error will be:
5
256
=20[mV]
For example, with a 9 bits, we can read 512 different values, with a quantization error of 10 [mV].
Oversampling:
In seismic data acquisition the maximum frequency of interest is 500 [Hz].
As a result, the sampling frequency should not be less than 1[KHz] (done by 2xFmax).
The 428XL has a sampling frequency of 256[KHz], then, the oversampling ratio is 256.
Advantages of OVERSAMPLING:
Easier ANTIALIASING.
Bit Gain All ADC generate WHITE NOISE. This noise (known as quantization noise) is evenly
spread across the range from 0[Hz] to Fs/2.
By Oversampling @ 256[KHz] the quantization noise is spread from 0[Hz] to 128[KHz] with a
lower level.
13. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
13
Sercel Delta Sigma Converter (∑-Δ)
Input Protection:
- High Frequency (HF) noise elimination.
- Antialiasing filter for oversampling frequency (256[KHz]
How it works:
- The digital signal generated by the ∑-Δ converter is encoded as a 1-bit stream and
transmitted on a serial line.
- That is why, a Digital Signal Processor (DSP) is used to convert the serial signal to a
parallel 24-bit signal @ 4[KHZ] (T=0.25[ms])
- By INCREASING the order of the ADC (we can achieve this connecting in cascade
mode/configuration) and increasing the oversampling ratio, then, the SIGNAL-TO-NOISE RATIO
and the CONVERTER’S DYNAMIC RANGE and RESOLUTION ARE INCREASED.
14. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
14
Noise Shaping:
Many bits can be gained if the noise is shaped:
A DIGITAL CONVERTER CONSIST OF AN ADC, DAC AND AN AMPLIFIER
The aim of noise shaping is to decrease noise at low frequencies.
So the transfer function applicable for the noise shaping is:
Qa= A/D quantization noise
Qd= D/A errors
15. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
15
So;
Qa is the quantization error relative to the 1-bit ADC. This is 50% error
Qd is the error relating to the 1 bit DAC. It is virtually zero, only caused by the noise of the DAC
H must be designed such that its value is very high (𝟏𝟎 𝟔
), and in the band of interest (e.g. 0 to 1000[Hz],
and very low (aprox. =0) out of the band of interest.
Assuming Qd is negligible:
DELAY MEMORY (LAU)
Description:
The RAM DELAY memory or called also ROTATING BUFFER, is located in the LCI board,
LAUL, and LAUX.
It is the key element, permitting the following functions to be performed:
Data Storage for digital signal processing
Removal of sampling skew.
Implementation of different anti-aliasing filter characteristics.
16. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
16
Data Processing
a. Sample Skew Processing: When a control word is sent to the field units, a delay of a few
milliseconds arises between the moment the first unit receives the word and the moment the
last one receives it.
Each repeater brings about a delay of 1.5[µs] and cables give rise to a delay of 5[ƞs] per meter.
That is why, the start of all FDU must be synchronized and we need to use the following method
to do it. After the line is formed, each station unit starts to acquire data. This is fed to the FDU,
then the LAU and displayed on the HCI (Human Computer Interface) into the screen
(Seismonitor in Jline environment), but it is not recorded. The memory of the LAU Slave gets
filled up and retains the latest samples milliseconds of data.
During the line forming, the microcontroller (µcontroller) (of the LAU master for each segment
and the LCI) determines the delay corresponding to the time associated with the selected filter,
plus the delay associated with the propagation time for the messages between the acquisition
module and each link.
As a result, the first data processed is the data that was recorded before the
order to start acquisition was received.
b. DATA MEMORY DELAYS: Some delays are required in order to implement the required
convolution process. They depend on the sample rate and the filter type.
Filters Used
The decimators are used to perform three functions:
a. Achieving a high-cut filter (anti-aliasing), which is required because the signal is under-sampled.
b. Decimating the data from 256[KHz] to the sample rate.
c. Applying a linear-phase filter (no phase shift) or minimum-phase filter to the data.
17. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
17
LAUX
Function: In our case study we are going to mention the more characteristics features of the LAUX:
a. Same functionalities as LAUL
b. Multipath capabilities
c. Rerouting capabilities
d. For more features check the User’s manual.
How it Works:
The LAUX wakes up by sensing the voltage on its 4 transmission ghost pairs (hablar del ghost
pairs) (minimum VDC=5[V]), then supplies both sides with the +/-24[V] on each transmission
ghost pair and the transverse transmission ghost with a DC voltage to wake up the next LAUX
and so on.
The LAUX power on/off is software controlled and therefore any part of the spread can be
powered OFF if wanted on the HCI (Human Computer Interface).
The LAUX contains two independent boosters to supply its two sides.
The LAUX will work correctly if the voltage is above 10,5[V].
This field equipment interfaces the lines to the CM (Control Module) and also
collects, decimates, filters, and compresses the data before sending it to the Server
(Seismic Data) or to the LCI (Status, results). It also synchronized all the samples
with the time break. The sample rate can be 0.25[ms], 0.5[ms], 1[ms], 2[ms], 4[ms].
LAUX Architecture: It has
A transverse and a line interface (PLL, signal shaping)
An IBM403 (µcontroller)
Peripherals
DSP (to decimates, filters and compressing the data)
It is made of 1 sandwich box which contains two boards:
LPWX (Line Power Crossing board) board containing the boosters and Power supply of
the unit, the equalizers and the PLL’s.
LPXL (Line Processor Crossing and Line board) board containing the digital hardware.
LPWX Board: Provides
The charger for the Line Tester; 9.5[V]
The waking bloc that produces a 3.3[V] to manage the power-up circuits.
The power control block that manages everything and check the leakage.
The battery control block that protects the boards against and over-voltage.
ADC that measures the voltages.
LPXL Board: This board runs the program stored in the flash memory. Also managed the FDU and
process the data.
LPXL Board Architecture: Its main architecture contains the following components:
a. Digital Signal Processing (DSP): Decimates, filters and compress the data
b. Flash memory: Used to store the program.
c. DRAM: One is used by the DSP to process the data, the other one by the IBM.
d. IBM 405: Microprocessor @ 33[MHz].
e. DPR: Dual Port Ram, interfaces between the different buses.
f. FPGA: Interfaces with the LIPX board.
g. UART: Communication device to Xdev plug (TMS, LT).
18. ENG. ALEX LEVY
QA/QC SEISMIC CONSULTANT
Seis.eng01@gmail.com
18
h. EhtPhy: Component for Ethernet management.
LAUL
Function:
High Storage Memory capacity for non-Real Time operation.
Receives/Transmit FDU statuses and results.
Power supply the line @ 50[V].
How it works:
It wakes up by sensing voltage on the transmission ghost lines, then supplies with voltage the
opposite transmission ghost line
It interprets the orders coming from the LCI or 428XL Server, controls a line of FDU (up to 120
channels depending on interface) and collects the data from them.
On the data it performs:
Decimating,
Filtering,
Compressing
After all these it sent back information to the LCI (status) or 428XL Server (Seismic Data),
through the LAUX.
Synchronizes all the samples with the Time Break.
LAUL Architecture: It is made of only 1 board:
LPL16 (Line Processor Land board and 16 stands for 16[Mbps] – It means 16 Mega-bits-per-
second).
Cables
The Transmission is made using two pairs between all the elements: LCI, LAUX, LAUL, and FDU.
Cables Constitution:
The transverse and the line cable are exactly the same.
It is important to know about the type and main characteristic of the Sercel Cables:
o Standard: ST+6.5mm(0.25in)
o Waterproof: and traction resistant: WPSR 9.5mm (0.37), with a Kevlar braid.
o Waterproof: and traction resistant long range: WPSR-LR 9.5mm, with a Kevlar braid Must be
used in the secondary transverse only with LAUX408.
o EXT: 0.27mm (0.31in), extension cable that can be used in the transverse only with LAUX 408.
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GHOST PAIRS: The new transverse has +/-24[V] power control. It’s why we fin again “Booster” power
supply for the transverse management in the LPWX board into the LAUX.
The data transmission is done on 2 pairs and the power supply is re-built with the Ghost Pairs.
Those signals are conveyed by the ghost pairs that make use of the transmission pairs.
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The ghost pair transmits the power supply (+/-24[V]) for the line and the transverse.
CRC & TRANSMIT ERROR
The 428XL system uses a synchronous transmission @ 8192[MHz] or 16.384[MHz] on LINES
and 100 [Mbps] Ethernet on TRANSVERSES.
The transmission bits are organized in frames occurring every 1[ms].
The frames are generated by the 428XL (LCI) central unit on its Left and Right Transverses, and
replicated by each LAUX on its Low and High Port.
A frame is composed of 64 cells: The first cell is the frame header; the next 63 ones are
dedicated to LAU/LAU or FDU/LAU communications.
A cell is 16 bytes long on Lines and 32 bytes long on Transverses.
1 Byte = 16 bits
1 bit = 0 or 1 digital level (0 digital = 0[V] and 1 digital = 5[V])
Each cell is composed of three parts:
a. Cell header containing control bits (one byte).
b. Cell data (14 bytes on Line, 30 bytes on Transverse).
c. Cell CRC (one byte).
The FRAMES are used to implement TWO Communication Schemes as described:
1. FDU/LAU communication (LOW LEVEL PROTOCOL), each FDU writes 4 samples in a cell data
field.
- The addressing mode uses a token mechanism: each FDU writes its data in the first free cell
following a frame header and sets a busy bit (in the cell header). The addressing mode is then
sequential, so the next FDU writes its data in the next DATA CELL.
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- The communication is SYNCHRONOUS with FDU acquisition and provides an error detection
mechanism using the CRC field.
2. LAU/LAU communication (High Level Protocol)
- FDU samples received by an LAU are processed and compressed to form packets that are sent back
to the 428XL central unit.
- There is no time relation with FDU acquisition: A High Level Protocol with error detection and
recovery is implemented.
Time Synchronization:
The FDU samples the analog input using a 256[Kbits/s] sigma-delta converter.
The sampling clock is derived from the 8.192[MHz] line frequency.
The FDU perform a first decimation process to produce 24-bit sample @ 0.25[ms] sampling rate.
Four 0.25[ms] samples are written into a cell every 1[ms].
The time difference between the generation of the 428XL frame and sampling by each FDU is
measured at line power-on with a precision of 122[ns]. This value (called T1) is measured and
stored in each LAU for each FDU it controls.
The frame header sent by the 428XL central unit contains the T0 information. The information is
received by all LAU’s and FDU’s
An LAU or FDU decodes T0 if the CRC of the frame header is correct.
The T0 information is repeated three times.
The TB from the shooting system is not synchronous with the generation of the 428XL frame.
When TB occurs, the 428XL measures the time from TB to the start of the next frame with a
precision of 488[ns] and writes the T0 information and the measured time (called T2) in the
next frame header.
The LAU uses T1+T2 time to have the data received from FDU’s synchronized with T0.
LAU Acquisition:
The LAU contains two processor
1. DSP processor: This processor runs two independent processes:
1.1. Process 1:
- Receives incoming frames,
- Decodes cells,
- Check cell consistency and CRC,
- Extract samples and stores into a 512[ms] circular buffer.
1.2. Process 2:
- Reads samples from the circular buffer
- Performs convolution and decimation to generate acquisition samples at the user
sample rate.
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- Compresses them into packets of 16 scans and sends the compressed packets to
the IBM processor
2. IBM403 processor:
- This processor stores compressed packets into an acquisition buffer.
- The acquisition buffer is sent to 428XL central unit upon request using the LAU/LAU protocol.
- This phase (called retrieval) can be done at later date compared to acquisition.
Transmit Error Effects
The TRANSMIT ERROR AFFECTS THE LINE TRANSMISSION DIFFERENTLY DEPEENDING ON THE
PROTOCOL USED:
FDU to LAU Communications:
When receiving a frame from the line, the LAU checks for cell consistency.
When a cell CRC error is detected, the corresponding path is displayed in orange.
If frame headers are unaltered, the acquisition continues.
If frame headers are altered, then the acquisition stops with an error such as frame
error or token error.
LAU to LAU Communications:
The transfer of compressed sample packets from LAU to the 428XL central unit uses the
high level protocol.
If a transmit error occurs, a packet CRC error is detected, the wrong packet is discarded
and repeated.
Transmit error have no effect on this type of communication.
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CRC error handling algorithm
An algorithm is implemented that minimizes the effect of random transmit error
upon acquisition and allows the acquisition to continue, in event of CRC errors,
rather than stopping with and error message.
In any frame where a CRC error occurs, the four 0.25[ms] samples of each FDU are
replaced by the four corresponding samples of the previous frame.
As the 0.25[ms] FDU samples are then filtered, the result is an “interpolation” (A#7) (@ 2[ms] sampling
rate, the duplicated samples are convoluted with 508 samples around).
The corresponding path is displayed in orange.
The trace affected by CRC error during the acquisition are marked as “edited” in the SEGD
record.
The Trace Edit Field in demultiplexed trace header is set to 03.
Case Study:
In order to better explanation of how the CRC error handling algorithm works, a practical case is showed
below, in which a CRC error is generated during the acquisition of an FDU test sin wave @ 31.25[Hz] for
all sampling rates.
The trace altered by the CRC (seis5441) is captured by the SGA along with a reference trace (seis5436).
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Effect of consecutive CRC ERRORS:
We are going to see a CRC error on all acquisition frames during 20[ms] every 100[ms] and 2[ms]
sampling rate.
The acquisition signal is a 31.25[Hz] sine wave.
The trace altered by CRC Errors is displayed in red and can be compared with a normal trace displayed in
brown.
APPENDIX:
(A#1) Full Duplex:
Send/Receives larger amount of data.
Send/Receives data at the same time.
There is no danger of collision and therefore the transfer data is completed!
A full duplex link can only connect two devices, so, in case of multiple devices connection a lot of
links must be done.
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A full duplex link can only connect two devices, so many links are required if multiple devices are
to be connected together
In a Full Duplex 10Base-T Ethernet environment, the two host would have two channels,
separating out transmit and receive.
(A#2) Multiplexing/Demultiplexing:
Multiplexing is a method by which multiple analog message signals or digital data streams are
combined into one signal over a shared medium.
The multiplexed signal is transmitted over a communication channel.
The multiplexing divides the capacity of the communication channel into several logical channels,
one for each message signal or data stream to be transferred.
A reverse process, known as demultiplexing, extracts the original channels on the receiver end.
A device that performs the multiplexing is called a MUX, and a device that performs the reverse
process is called DEMUX or DMX.
(A#3) PLL:
The digital PLL is really just an analog PLL with a digital phase detector.
The DPLL is a hybrid system
The DPLL is very popular in synthesizer applications
In the figure the optional digital divider, and variations on it, are used in frequency synthesis
applications.
Popular types of digital phase detectors include:
– Exclusive or gate (EXOR)
– Edge-triggered JK-flipflop
– Phase frequency detector (PFD)
In digital communications various levels of synchronization are required
The synchronization problem can be viewed as one of parameter estimation from waveforms
The PLL is used to SYNCHORNIZE THE FDU.
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(A#4) White Noise:
White noise is defined as an uncorrelated noise process with equal power at all frequencies
(Figure 2.1).
A noise that has the same power at all frequencies in the range of ±∞ would necessarily need to
have infinite power, and is therefore only a theoretical concept.
However, a band-limited noise process, with a flat spectrum covering the frequency range of a
bandlimited Communication system, is to all intents and purposes from the point of view of the
system a white noise process.
(A#5) Jittering Effect:
Jitter effect may be caused by electromagnetic interference (EMI) and crosstalk with carriers of other
signals.
Jitter can cause a display monitor to flicker, affect the performance of processor, introducing clicks or
other undesired effect in audio signals, and loss of transmitted data between network devices.
The amount of tolerable jitter depends on the affected application.
In analog to digital and digital to analog conversion of signals, the sampling is normally assumed to be
periodic with a fixed period (the time between every two samples is the same)
If there is jitter present on the clock signal to the analog-to-digital converter or a digital-to-analog
converter, the time between samples varies and instantaneous signal error arises. The error is
proportional to the slew rate of the desired signal and the absolute value of the clock error.
Various effect such as noise (random jitter), or spectral component (periodic jitter) can come about
depending on the patter of the jitter in relation to the signal.
In some conditions, less than a nanosecond of jitter can reduce the effective bit resolution of a
converter with a Nyquist Frequency of 22[KHz] to 14 bits.
This is a consideration in high-frequency signal conversion, or where the clock signal is especially prone
to interference.
Anti-Jitter circuits:
Anti-Jitter circuits (AJC’s) area a class of electronic circuits designed to reduce the level of jitter in a
regular pulse signal.
AJC’s operate by re-timing the output pulses so they align more closely to an idealized pulse signal.
They are widely used in clock and data recovery circuits in digital communications, as well as for data
sampling systems such as the analog-to-digital converter and digital-to-analog converter.
Examples of anti-jitter circuits include phase-locked loop and delay-locked loop.
Inside digital to analog converters jitter causes unwanted high-frequency distortions. In this case it can
be suppressed with high fidelity clock signal usage.
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ABFT Frequency Translator is designed to attenuate jitter / phase noise; accompanied with a 10MHz
Reference Signal - while up-converting the input frequency by times two or times 4. This solution
maintains phase & frequency cohesion to the 10MHz input reference. The approached employed in the
ABFT design is a non-traditional Phase Locked Loop; ensuring significant jitter clean-up, very close-to-
the-input carrier.
If ABFT is driven from a Noisy 10.00MHz reference, the intrinsic phase noise of the ABFT device will take
over; starting at about 1kHz offset and will be typically better than -150dBc/Hz @ 10kHz away from the
carrier. This will yield better than 0.50 ps. rms jitter over 12kHz to 20MHz BW, regardless of the input
reference noise.
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(A#6) Digital Signal Processing (DSP):
(A#7) Interpolation:
Interpolation is a method of constructing new data points within the range of a discrete set of know
data point.
In engineering and science, one often has a number of data points, obtained by sampling or
experimentation, which represent the values of a function for a limited number of values of the
independent variable.
It is often required to interpolate (estimate) the value of that function for an intermediate value of the
independent viable.
References:
- Sercel User’s Manual 1; 2; 3; Technical Manual
- Data Communication Fundamentals; By Kharagpur
- Phase-Locked Loops with applications ECE 5675/4675 Lectures Note Spring 2011; By Mark A.
Wickert.
- Advanced Digital Signal Processing and Noise Reduction; By Saeed V. Vaseghi.
- Crystals Oscillators Real-Time-Clocks Filters Precision Timing Magnetics Engineered Solutions;
Abracon Corporation.