This document discusses the optimal use of multilayer ceramic capacitors (MLCCs) for synchronous buck converters used in point-of-load applications. It describes how the electrical parameters of MLCCs are highly dependent on factors like voltage, frequency, temperature and package size. The document provides guidelines for selecting the right type, value, size and number of MLCCs for the input and output filters of synchronous buck converters. It presents an application example and experimental results to demonstrate the effectiveness of the proposed design methodology.

1. Optimal Utilization of Multi Layer Ceramic Capacitors for Synchro-
nous Buck Converters in Point of Load Applications
Peyman Asadi, Yang Chen, Parviz Parto
International Rectifier
8845 Irvine Center Dr., Suite 101
Irvine, CA, 92618, U.S.A.
Abstract
Capacitors as a part of input and output filter play a major role on the performance, size, and total cost
of synchronous buck converters. Thus, right selection of type and value of these capacitors is
essential to achieve a high performance and competitive solution. Multilayer Ceramic Capacitor
(MLCC) is a popular solution for the modern Point of Load (POL) applications. Despite several
benefits of MLCC, its electrical characteristics are highly nonlinear and its specifications de-rate
substantially with the voltage at its terminals, the operating frequency, and ambient temperature.
Understanding these behaviors is crucial in optimal design of synchronous buck converters using
MLCCs. In this paper, the effect of design and operating factors on the electrical parameters of
MLCCs are investigated. Furthermore, some guidelines are introduced on how to select the optimal
size, value, type, and number of MLCCs for input and output filter of synchronous buck converters. An
application example with experimental results is presented to demonstrate the effectiveness of the
proposed method.
1. INTRODUCTION
Low output voltage, high load current, fast
transient response, high efficiency both at
heavy load and light load are common re-
quirements for POL circuit design. With the
shrink of board size and height, stringent limits
are put on the physical size of POL circuits. On
the other hand, fast transient load response
pushes the utilization of a higher bandwidth in
the control loop design. Thus, a high switching
frequency should be used. All of these re-
quirements open the door for MLCCs to re-
place bulk capacitors, such as electrolytic, tan-
talum, polymer capacitors, both at input side
and output side, because: i) MLCCs have
smaller footprint and height, which meet the
physical size requirements and reduce Equiva-
lent Series Inductance (ESL); ii) they also have
smaller Equivalent Series Resistance (ESR),
which dissipate less power and help to sup-
press output voltage ripple at high switching
frequency and output voltage swing during
load transients; iii) they are more cost-
effective.
Previous literature [1] introduces the technol-
ogy of different types of capacitor and indi-
cates the possibility of shrinking capacitor size
to increase power density. References [2-3]
explain the MLCC capacitance and ESR char-
acteristics in different working conditions, such
as DC or AC voltage, temperature, frequency
etc. References [4-7] focus on the roles of
MLCCs in modern power management area.
Reference [8] introduces a highly integrated
synchronous buck converter with all ceramic
capacitor. It has an enhanced efficiency both
at heavy and light load and 70% reduced
board size.
Figure 1 shows a typical SupIRBuck circuit. It
can be seen that passive components, such as
inductor and ceramic capacitors, still occupy
about 50% board area, even though this area
is greatly reduced from previous non-ceramic
application. Thus, optimizing the quantity of
capacitors becomes important and challeng-
ing. In considering a high-frequency DC-DC
Buck converter, MLCCs serve not only as in-
put/output filtering and signal decoupling, but
affect the loop stability. For example, the quan-
tity of output capacitors and their small signal
capacitance is closely related to the double
pole frequency of the control loop. Thus, as a
circuit designer, it becomes essential to under-

2. stand MLCC's characteristics under different
operating conditions in order to minimize the
quantity, size and cost of them, while keeping
the high performance of the DC-DC converter.
In this paper, analysis and design considera-
tions of using MLCCs, such as capacitor ac
current ripple rating and temperature rise, ca-
pacitance de-rating with voltage and tempera-
ture, size vs. ESL, are presented for typical
POL circuits in Server and Netcom applica-
tions. All these considerations are integrated
into a design tool that can complete design
procedures systematically.
Fig. 1. Top view (upper) and bottom
view (lower) of a SupIRBuck circuit
In this paper, modeling and parameter varia-
tion of MLCCs are introduced in section 2, and
then section 3 explains the criteria of selection
of MLCCs for synchronous buck converters.
Experimental results and conclusions are pro-
vided in section 4 and 5.
2. MODELING AND PA-
RAMETER VARIATION OF
MLCCS
The technology and physics of MLCCs are
discussed by many publications [1-7]. In this
section, the most important characteristics of
MLCCs for design of POL converters are high-
lighted.
The structure of a multilayer ceramic capacitor
is shown in Fig. 2. Basically, multiple layers of
dielectrics are sandwiched between electrode
plates, which are terminated to the component
endings. The capacitance of MLCC can be de-
scribed as.
(1)
d
SnK
C
⋅⋅
=
where, K, n, S, d are dielectric constant, num-
ber of layers, effective area under two elec-
trodes (S=L x W), and dielectric thickness, re-
spectively.
The advancement of manufacturing technol-
ogy has made development of MLCCs possi-
ble with d<0.5um in recent years. Thus, many
high value MLCCs with small package are
commercially available.
The class 1 and class 2 dielectric materials are
commonly used for POL circuits. The dielectric
constant of Class 1 materials (i.e. NP0) varies
almost zero with temperature. Class 2 materi-
als (e.g. X5R, X7R) have high dielectric con-
stant. However, capacitors with calss 2 mate-
rial derate substantially with temperature, and
applied voltage across MLCC. Thus in POL cir-
cuits, MLCCs with class 1 materials will be
mostly used where precise and small capaci-
tance are needed such as compensation net-
works and MLCCs with class 2 material will be
used mainly where a large bulk capacitance is
needed. In this case, de-rating of capacitor pa-
rameters should be well taken into account for
effective use of MLCCs.
(a) Cross Section of a MLCC
(b) A layer of Dielectric and Electrodes
Fig. 2. Basic structure of a MLCC
Knowing the small signal behaviour of capaci-
tors is essential for analyzing the stability and
performance of synchronous buck converters.
Many multi-element models have been pro-
posed for MLCCs and, in this paper, we adapt
the most commonly used model as shown in
Fig. 3. In this three element model model, C is
the Apparent Capacitance. Apparent capaci-
tance can be much smaller than the nominal
capacitance value of the part. This difference
varies from one vendor to another and even
from one part number to another. Moreover,
apparent capacitance changes with the DC,
and AC voltage across the terminal of capaci-
tor and its operating temperature.

3. Fig. 3. Small signal model for MLCCs
The apparent capacitance for some capacitors
with X5R dielectric material are measured and
shown in Fig. 4. It can be observed that the
apparent capacitance of a 22uF capacitor with
EIA-0805 package with 1V DC bias voltage
can be as low as 12uF. The results imply that
47uF capacitance drops with DC voltage
steeper than 22uF capacitor in the same pack-
age size. The 10V rated capacitor keeps its
apparent capacitance better as compared to
6.3V capacitor for the same applied voltage.
Moreover, the 22uF capacitor in EIA-1206
package has higher capacitance than the
same capacitor in EIA-0805 package and it
derates slower with DC voltage. These behav-
iors can be explained by the fact that the di-
electric material is composed of many dipoles
that can be oriented with the electric field
across the electrode plates and the strength of
a dielectric depends on the number of un-
aligned dipoles [4]. DC voltage across capaci-
tor terminals creates an electric field in the di-
electric, which in turn reduces the number of
unaligned dipoles and reduces the strength of
the capacitor. The thickness of layers for
higher value capacitors with smaller package
are smaller, thus the electric field in layers is
stronger and derating is sever.
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
DC Voltage (V)
C(uF)
22UF/ 6.3V/ X5R/ 0805/ 20%, Vendor A
22UF/ 6.3V/ X5R/ 1206/ 20%, Vendor A
47uF/ 6.3V/ X5R/ 0805/ 20% Vendor B
10uF/ 10V/ X5R/ 0805/ 20% Vendor C
22uF/ 6.3V/ X5R/ 0805/ 20% Vendor C
Fig. 4. Variation of C vs. DC voltage
The apparent capacitance of MLCC varies with
applied AC voltage. The voltage ripple across
input and output capacitors are usually small
for synchronous buck converter and its derat-
ing can be neglected.
ESR and ESL are dependent on package ge-
ometry and dielectric material. However, ESL
remains constant for a selected MLCC,
whereas, ESR varies with operating frequency,
and temperature. Comparing the ESR and
ESL of a capacitor with different packages,
usually ESR is increasing by using a smaller
size package and ESL is increasing with a big-
ger package size.
3. SELECTION OF MLCCS
FOR SYNCHRONOUS
BUCK CONVERTERS
A typical application circuit of a synchronous
buck converter circuit using MLCCs is shown
in Fig. 5. The converter is a highly integrated
multi-chip voltage mode controlled PWM con-
troller and driver with integrated MOSFETs [8].
The input voltage (Vin), output voltage (Vo),
switching frequency (Fs), and nominal load
current (Io) of the converter are 12V, 1.8V,
600kHz, and 12A, respectively for the selected
application. The ripple current generated dur-
ing the on time of the upper MOSFET should
be provided by the input capacitor. The RMS
value of this ripple (IRMS) is expressed by Eq.
(2).
(2)28.4)( AVVVVII inoinooRMS =−⋅⋅=
The selection of input capacitors should be
based on their ripple current rating, ESR, ESL
and temperature rise. The ripple current rating
and ESL are increasing by the size of capaci-
tor. However, ESR is decreasing by the size.
For this application, four 10uF, 16V, X5R, in
1206 case size was selected. Each MLCC is
sharing 1.07A RMS current and the tempera-
ture rise is less than 10o
C.
The voltage ripple and transient requirements
determine type and number of output capaci-
tors. The minimum required capacitance at the
output to meet the transient requirement can
be estimated from Eq. (3).
(3)2
2
)VV(LIC spec_transooLmin Δ⋅⋅Δ= ⋅
where, L, ΔIL, and ΔVotrans_spec are output filter
inductor, peak to peak inductor current ripple,
and maximum allowable output voltage swing
during load transient, respectively. The actual
output capacitance is usually selected with
margins on top of the minimum requirement.
And small signal value of the capacitors should
be used here.

4. Fig. 5. A typical Synchronous Buck Converter using MLCCs
The output voltage ripple can be found from
Eq. (4).
)(
F*C*
I
ESL*
L
VV
ESR*IV
seqo
L
eq
oin
eqLoripple
4
8
Δ
+⎟
⎠
⎞
⎜
⎝
⎛ −
+Δ=
where, Voripple, Coeq, ESReq, and ESLeq, are out-
put voltage ripple, equivalent output capaci-
tance, ESR, and ESL, respectively. Usually,
the last item in (4) dominates the ripple in
MLCC application. For this application, using
six of 22uF (nominal value) capacitor with
0805 case size, X5R, 6.3V can meet both ±1%
Voripple and ±5% ΔVotrans_spec as design require-
ments.
To close the control loop with desired Band-
width and Phase Margin, a TYPE III-B com-
pensation network (PID) is used. The target
bandwidth (Fo) is set to 100kHz with 70°C
phase boost (θ ) at the cross over frequency.
Thus, the location of poles and zeros should
be set as following.
300kHz508.82kHz50
567.1kHz
1
1
(5)17.63kHz
1
1
723
2
1
321
2
2
====
=
−
+
=
=
+
−
=
=
⋅
=
sPZZ
oP
oZ
oeqeq
po
F*.F,F*.F
sin
sin
FF
sin
sin
FF
kHz.
CL
F
θ
θ
θ
θ
π
where, Fpo is the double pole frequency; Fz1
and Fz2 are selected zeros in the control loop
and Fp2 and Fp3 are poles.
If we select C7=2.2nF the rest of compensation
values can be calculated as following.
2.49kΩ:Select2.49kΩ.
3.92kΩ:Select3.97kΩ
2
1
220pF:Select283.7pF
2
1
(6)10nF:Select9.65nF,
*2
1
1.87kSelect1.85kΩ.
2
989
810
27
8
33
33
3
4
31
4
3
7
3
===
===
===
===
Ω===
RR*
VV
V
R
R,R
F*C*
R
C,C;
R*F*
C
C
R*F
C
R:
V*C
V*C*L*F*
R
refo
ref
Z
P
Z
in
oscooo
-
-
π
π
π
π
4. EXPERIMENT
VERIFICATION
A circuit with the component values of Fig. 5
was built and tested. The total solution fits on
an area of 25mmx10mm of PCB with compo-
nents mounted on both side of the board. The
Bode plot shows a 99.4kHz bandwidth and
53.9o
phase margin, which are close to the de-
sign goals. The double pole frequency of the
closed loop is around 23kHz from which the
small signal capacitance of the output MLCC
can be calculated to be 12.5uF/each or so in
this specific case, though the nominal value is
22uF.
Figure 7 shows the output voltage ripple and
Fig.8 presents the transient load response. It
can be seen that the Vo ripple is less than ±1%
of Vo (1.8V) and Vo transient peak-to-peak
voltage is less than ±5% of 1.8V. Both per-
formances match very well with the design tar-
gets.

5. Fig. 6. Bode plot with 99.4kHz Bandwidth
and 53.9° phase margin
Fig. 7. Output voltage ripple at 12A load
Fig. 8. Transient load response from 6A to
12A at 2.5A/us slew rate (Ch2:Vo, Ch4:Io)
5. CONCLUSIONS
The electrical characteristics of multilayer ce-
ramic capacitors for using in Synchronous
Buck converters were investigated in this pa-
per and some guidelines on the optimal selec-
tion of size, value, type, and number of MLCCs
for these converters were presented in a sys-
tematic approach. These steps are shown with
an application example. Experimental results
from the application circuit meet all the design
goals and confirm the effectiveness of our ap-
proach. Following these steps eliminates the
trial and error steps during board design proc-
ess. Moreover, by optimal selection of capaci-
tors and tuning control loop accordingly, the
designer can shrink the overall footprint of the
solution effectively and bring down the cost of
the convertor substantially. The design proce-
dure is integrated into a tool, which supplies
most convenience for users.
6. REFERENCES
[1] W.J. Sarjeant, J.Zirnheld, F.W. MacDou-
gall, “Capacitors“, IEEE TRANS. ON
PLASMA SCIENCE, vol. 26, NO. 5, pp.
1368-1392, OCT. 1998
[2] O.Déjean, T.Lebey, V. Bley, “An Experi-
mental Characterization of Nonlinear Ce-
ramic Capacitors for Small and Large Sig-
nals“, IEEE Trans. on Components and
Packaging Technologies, vol. 23, NO. 4,
pp. 627-632, DEC. 2000
[3] J. Prymak, M. Randall, P. Blais, B. Long,
“Why that 47uF capacitor drops to 37uF,
30uF, or lower”, Proceedings CARTS USA
2008, 28th
Symposium for Passive Elec-
tronics, March, 2008, Newport Beach, CA
[4] P.Markowski, C.Quinn, “Bypass Capaci-
tors for Point-of-Load Architecture”,
http://powerelectronics.com/mag/power_b
ypass_capacitors_pointofload/
[5] M.S.Randall et. al. “Capacitor Considera-
tions for Power Management”, 2006
CARTS Conference Proceedings, April
2006, Orlando, FL
[6] A. Abou-Alfotouh, A.Lotfi, M.Orabi, “Com-
pensation Circuit Design Considerations
for high Frequency DC/DC Buck Convert-
ers with Ceramic Output Capacitors“,
IEEE Applied Power Electronics Confer-
ence 2007, pp. 736 – 742, Feb.-March,
2007
[7] K.Kundert, “Power Supply Noise Reduc-
tion“,http://www.designers-
guide.org/Design/bypassing.pdf
[8] P. Asadi, C. Contenti, “Innovative Wide
Input, Output DC-DC Buck Converter En-
hances Efficiency and Drastically Shrinks
Footprint”, PCIM2009 Europ, May, 2009,
pp.252-257