Conoce cómo Crystal Group realiza una compresión del consumo en la electrónica digital.

1. Understanding Power
Consumption in
Digital Electronics
White Paper by:
Brian Rinehart
Special Projects Technical Director
October 2014
Crystal Group Inc. | 850 Kacena Road., Hiawatha, IA | 800.378.1636 | crystalrugged.com
Contact: leslie.george@crystalrugged.com

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TABLE OF CONTENTS
Contents
EXECUTIVE SUMMARY...................................................................................................................................3
INTRODUCTION ...............................................................................................................................................3
BACKGROUND..................................................................................................................................................3
STATIC POWER.................................................................................................................................................3
DYNAMIC POWER............................................................................................................................................4
DIE TO DIE VARIATION...................................................................................................................................6
UTILIZATION .....................................................................................................................................................6
CONCLUSIONS .................................................................................................................................................7
ABOUT THE AUTHOR .....................................................................................................................................7
ABOUT CRYSTAL GROUP INC......................................................................................................................7
COTS Computing in Oil Well Production and Monitoring Applications

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EXECUTIVE SUMMARY
Effective thermal management in digital electronics comprises a vast number of design
considerations that must be accounted for before fielding computational hardware for low
maintenance installations into high stress environments and operating conditions. Some of the
mitigation may be addressed through proper chip design and selection, generally outside the
control of server vendors. Other mitigation must be addressed through incorporation of proper
design and integration techniques at the system level.
INTRODUCTION
There are a vast number of variables that go into power consumption and dissipation
measurements. Simply powering on a server and measuring the current without taking these
variables into consideration will almost always result in misleading data that could lead to system
design issues that drive confounding perplexity under different operating, environmental, and/or
randomly due to die variations. The purpose of this paper is to sort out these factors and describe
the various physical properties of semiconductor technology that contribute to power
consumption in digital processors and supporting chipsets found in computational server hardware.
Concepts defined in this paper include static power, quiescent power, gate leakage, linear and
exponential dependencies on switching frequency and temperature, and common die to die lot
silicon variations.
BACKGROUND
There are two main distinct and independent contributors to power consumption and dissipation,
namely static power and dynamic power. Static power, sometimes referred to as quiescent power
consumption stems primarily from leakage and the necessary power required to drive a gate, or
millions of gates in high performance logic circuits and processors. Dynamic power consumption is
based on the number of gates changing state, the frequency of these state changes, and the
capacitance of each of these gates or millions of gates. Many server OEM’s focus on static power
consumption but fail to consider the full effects of dynamic power consumption, thereby steering
the way to exaggerated thermal performance claims.
STATIC POWER
As the wafer geometries continue to shrink with technological advances, there are two distinct
resulting phenomena—one of them good, one of them not so good when it comes to power
consumption. First, the amount of gate voltage, also known as pinch-off voltage, that is tolerable
before a junction breakdown occurs, decreases. The reduction in operating voltage intuitively and
clearly reduces the power consumption, easily seen by merely applying Ohm’s Law: P=E2/R where
Power is a function of energy (voltage) squared divided by the input resistance. The secondary
phenomenon isn’t as beneficial and dramatically offsets any benefit of reducing the voltage drive
due to die geometry shrinkage. With a decrease in pinch-off voltage, a given gate isn’t necessarily
allowed to close entirely. That is, when a given junction is driven to provide a logic low, the lack of

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a closed gate causes a little leakage current to pass through the positive supply rail, and “off” isn’t
exactly off. Conversely, when a given junction is driven to present a logic high output, a little leakage
current passes through the ground rails. The leakage current on a gate can be very small, on the
order of nano-amperes. However, when multiplied by millions or billions of gates as found in high
performance processors and support chip electronics, this leakage adds up to significant amount of
power dissipation. Further, the phenomenon that causes leakage is temperature sensitive.
As the temperature of a semiconductor increases, the more energetic electrons are allowed to enter
the depletion channel between the gate and source and it takes more pinch-off voltage to achieve
the same level of isolation between junctions. Thus, for a fixed available pinch-off voltage, the
increase in temperature thereby exacerbates the leakage and causes an increase in static power
over the amount at say room temperature. The relationship between leakage or quiescent current
grows exponentially as temperature increases as shown in Figure 2. As an aside, another
temperature related problem is called thermal runaway. As adevice heats, additional leakage power
is dissipated. As additional power is dissipated, the device continues to heat up, thereby causing
additional leakage. If not controlled, thermal runaway can lead to the ultimate failure of a gate,
device, or motherboard.
DYNAMIC POWER
The second major component to power consumption is dynamic power. Dynamic power is defined
as the amount of power dissipated due to the charging (and discharging) of gate (and I/O)
capacitance. Mathematically, this relationship exists between the total capacitance, the charging
voltage, and the repetition frequency as shown in Equation 1. From a physical perspective, as die
geometries continue to shrink with technological advances, the shrinkage in substrate causes a
decrease in the capacitance of a given gate. The result is decreased power for a given design.
However, one reason for shrinking die geometries isn’t necessarily so much as to reduce the effects
of power consumption as it is to allow for higher density processing within a given package.
Therefore, any advantages in dynamic power consumption gained by geometry reduction are
clearly offset by the increase in number of gates in a given package. It may be of interest to note
that package density isn’t driven only by the number of gates that physically fit under the lid, but
the amount of heat (measured in Watts) that a given package is capable of dissipating before
Figure 1. A simple logical inverter circuit; the basis for internal chip logic and often used to drive discrete I/O.

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package deterioration and ultimately failure occurs. In the case of server grade processors,
manufacturers such as Intel incorporate thermal sensors and automatically throttle back core clocks
to help manage thermal issues related to dynamic power consumption and helping to prevent
permanent damage. Unlike static power consumption which is exponentially related to
temperature increases, dynamic power consumption is linearly dependent on the number and
frequency of gates switching, but tends to be totally independent of thermal consideration. See
Figure 2 for the relationships between static, dynamic, and total power consumption/dissipation.
Once we have an understanding of dynamic power, we can break it down further into two basic
types: gate power and I/O power. While the parameters that go into these calculations may vary
due to differencesin physical propertiesof internal gates vs. I/O pins, the equation remains the same
in terms of multiplying number of pins (or gates) changing state with the capacitance of a pin (or
gate) junction and the square of the transition voltage with the frequency of oscillation of each pin
(or gate) as shown below:
𝑷𝑷=𝑵𝑵𝑵𝑵 𝒙𝒙 𝑪𝑪 𝒙𝒙 𝑽𝑽𝑽𝑽𝑽𝑽𝑽𝑽 𝒙𝒙 𝒇𝒇
where P is the power (in Watts) consumed due to gate or I/O transitions, 𝑵𝑵𝒑𝒑 is the number of gates
(or pins) changing state, C is the total capacitance, 𝑽𝑽𝒅𝒅𝒅𝒅 is the transition voltage, and f is the average
frequency of change. As an example, consider a memory interface with 64 data lines, 32 address
lines, and eight control lines with a fan-out distribution to four memory devices. The power
calculation is shown in Table 1 below.
Pin Type # of Pins
Switching
Rate
Capacitance VDD
Frequency
(MHz)
Power (W)
Data 64 50% 5pF + 4xCin 1.25 1600 2
Address 32 8% 10pF +
4xCin
1.25 800 0.096
Control 8 50% 10pF +
4xCin
1.25 8 0.0015
Total 2.0975
Table 1. Example power calculation for a memory interface

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If we scale this to all of the I/O on a server motherboard and add similar calculations for the millions
of gates internal to processors, memory, supporting chips, etc., we see these can vary greatly
depending on utilization and loading.
DIE TO DIE VARIATION
The characteristics of silicon that contribute to power consumption, namely, gate capacitance, gate
leakage, voltage thresholds, input currents, etc., can and will vary extensively across lot to lot, wafers
within a given lot, and in fact, even within gates on a given die. Therefore, it is essential to
understand that measuring power consumption, no matter how well the loading use case and
environmental factors are controlled, could be anywhere within a Gaussian distribution and should
not be considered any more credible than nominal or theoretical maximum values attained through
analysis.
UTILIZATION
After consideration of physical properties described above that drive static and dynamic power
consumption, there are other, more user-controlled parameters that can drive power consumption
quantification. For example, in a computer server application, there are typically multiple
processors, processing cores, more memory, and occasionally more graphics processing capability
Figure 2. Total power as a function of static and dynamic power. Note that static power is exponentially thermal
dependent whereas dynamic power is linearly frequency dependent.

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than will be typically utilized in any given practical application. For this reason, to obtain absolute
worst case power and thermal dissipation numbers, it is imperative to exercise every chip in a
system to the maximum extent possible. For processors, that may leverage a tool such as Prime95.
For memory, a tool such as MemTest may be used. For graphics processing, a tool such as Furmark
may be utilized. Again, without maximizing all core and chip utilization, measured power
consumption data in the lab could vary greatly and fall short of actual power consumed and
dissipated in fielded applications.
CONCLUSIONS
Effective thermal management in digital electronics comprises a vast number of design
considerations that must be accounted for before fielding computational hardware for low
maintenance installations into high stress environments and operating conditions. Now that we
have a better understanding of the vast number of variables that go into power consumption and
dissipation measurements, we should be able to avoid system designs that lead to thermal
performance issues under various operating and environmental conditions, and/or randomly due
to die variations.
Some of the mitigation may be addressed through proper chip design and selection, generally
outside the control of server vendors. Other mitigation must be addressed through incorporation
of proper design and integration techniques at the system level. Techniques employed by Crystal
Group include high technology cable selection and routing to minimize airflow restrictions,
judicious selection of motherboards to keep high power processors and memory in line with
maximum airflow, and evaluation at 100% duty cycle on every core and memory. This is the only
way to truly capture thermal performance capabilities!
ABOUT THE AUTHOR
Brian Rinehart is a Special Projects Technical Director with Crystal Group. He has
been with the company since 2010. Prior to Crystal Group, Brian was a Principal
Electrical Engineer and/or Senior Engineering Manager at Rockwell Collins for
several years. Brian received BSEE, in RF and DSP Communication from Iowa
State University.
ABOUT CRYSTAL GROUP INC.
Crystal Group Inc., an employee-owned small business located in Hiawatha, Iowa, USA, is a
technology innovation leader specializing in both custom and COTS products for defense,
government and industrial markets since 1987. Crystal Group designs and manufactures
installation-ready rugged servers, displays, networking devices, embedded systems, power supplies
and storage devices that fit critical applications in demanding environmental conditions.
Brian Rinehart
Crystal Group Inc.

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industrial standards. Additionally, the company offers integration services, configuration
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