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Cmos scaling on resistive component 2012
- 1. Keep Scaling ofthe CMOS Fabrication Process on Resistive Component to Beyond 22nm James M.M. Chu, PhD Department of Engineering Science NCKU
- 2. Application Oriented ICPerformance Needs Server Desktop Netbook Smart Phone Laptop Tablet Mobile Phone High ☆☆☆ ☆☆☆ ☆☆ ☆ Performance Low Active ☆☆☆ ☆☆ ☆☆☆ ☆☆☆ Power Low Leakage ☆ ☆ ☆☆ ☆☆☆ 2
- 3. Product Spectrum ofIC Applications 65nm 45nm 32nm 22nm +22% High Leakage Power Performance Server / Desktop x10 Standard Performance Notebook x10 Netbook Low Power Tablet Smart Phone Mobile Phone Operation Frequency 3
- 4. Future CMOS ScalingPaths From INTEL 4
- 5. Contact Max. Resistivity(Ω-cm2) ITRS Roadmap - Resistivity MPU Physical Gate length 29nm 1.60E-07 Contact maximum resistivity for bulk MPU/ASIC (Ohm-cm2) 27nm Contact maximum resistivity for FDSOI 1.20E-07 MPU/ASIC (Ohm-cm2) 8.00E-08 24nm 22nm 4.00E-08 20nm 18nm 1.00E-11 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 Production Year 5
- 6. MOSFET Device Structure VS VG VD LG VS VG VD ψ W Gate Tox Rc VT Idsat Source Xj Drain L Silicon Rs MOSFET device structure Transistor circuit schematic 6
- 7. CMOS Device ResistantComponents RC Contact Plug Gate RCSD ROV RSDE Rexternal = RS/D Rchannel - RC = Plug contact - RCSD = Silicide, Silicide to S/D contact - RSD = Deep S/D junction - RSDE = S/D Extension - ROV = Accumulation-layer under the gate overlay 7
- 8. CMOS Resistance ScalingTrend 800 Rchannel Rexternal (Ω-μm) Resistance (Ω-μm) 700 600 500 Rchannel Rexternal at 400 32nm node 300 200 100 0 90nm 65nm 45nm 32nm 22nm Technology Node 8
- 9. External Resistivity Breakdown- nMOS nMOS Rexternal = 44.5%, Rchannel = 55.5% RC (Contact Plug Resistance) RCSD (NiSi / Si Interface) RS/D (Spreading + Shunt) RSDE (Spreading + Overlay) RC (Contact Plug Resistance) RSDE (Spreading + Shunt) 5% 16.7 % 16.7 % 6% RS/D (Spreading + Overlay) RCSD (NiSi / Si Interface) Rchannel = 44.5% RExternal = 55.5% 9
- 10. External Resistivity Breakdown- pMOS pMOS Rexternal = 49.1%, Rchannel = 51.9% RC (Contact Plug Resistance) RCSD (NiSi / Si Interface) RSDE (Spreading + Overlay) RC (Contact PlugRS/D (Spreading + Shunt) Resistance) RSDE (Spreading + Shunt) RCSD (NiSi / Si Interface) 2.6 % 4.5 % 22.5 % 19.5 % RS/D (Spreading + Overlay) Rchannel = 49.1% RExternal = 51.9% 10
- 11. Silicide Thickness v.sGate Length 40 40 30 29nm 30 Dimension (nm) 27nm Dimension(nm) 24nm 22nm 20nm 18nm 20 20 21nm 19.5nm 17.9nm 16.2nm 14.7nm 13nm 10 10 Silicide thickness for bulk MPU/ASIC (nm) Silicide thickness for bulk MPU/ASIC (nm) Proposed MPU Physical Gate Length (nm) MPU Physical Gate Length (nm) 450mm Wafer Insertion 0 0 2009 2009 2010 2010 2011 2011 2012 2012 2013 2013 2014 2014 2015 2015 Year of Production Year of Production 11
- 12. Rcsd v.s Max.Rc Resistivity Scaling 15 1.80E-07 Contact silicide sheet resistivity (Ω-cm2) 1.60E-07 18nm Contact Max. Resistivity (Ω-cm2) 12 20nm 1.40E-07 22nm 1.20E-07 9 1.00E-07 24nm MPU Physical Gate length 8.00E-08 6 Contact silicide sheet Rs for bulk MPU/ASIC 22nm 6.00E-08 (Ohm/sq) 20nm 4.00E-08 3 Contact maximum 18nm resistivity for bulk 2.00E-08 MPU/ASIC (Ohm-cm2) 0 0.00E+00 2009 2010 2011 2012 2013 2014 2015 Production Year 12
- 13. Overview of SilicideCharacters in Fabrication Silicide/ Silicide Silicon Work Interface function Passivation silicide silicide Poly Si Silicide/Silicon Silicide Substrate Interface Thermal SBH Stability 13
- 14. KPI for CMOSFabrication Process Technology Manufacturability Extendibility 14
- 15. Summary • CMOS scalinghas three paths and resistive component play bigger role after 32nm node. • The process of Metal Silicide formation shows room for extension. • The process development for 22nm and below should fit several KPI for manufacturability and extendibility.