This presentation that given in ISSM 2010 at Tokyo. Japan is to share the art of wet etch process which is the result form the JDP with UMC TD.

1. ISSM 2010 NiPt SALICIDE Process
Optimization for
28nm CMOS Manufacturing
James M.M. Chu (Speaker)
Application Dept. Manager
SE Asia/Greater China Region
FSI International
James.chu@fsi-intl.com
ISSM 2010 1 G-Number

2. NiPt Silicide for CMOS
Source Gate Drain Scaling
NiSi
Contact electrode
Contact electrode
NiSi 65nm
NiSi 45nm
Gate
Stack
NiSi 28nm
NiSi NiSi
STI STI
Si
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3. NiSi Encroachment Defects
Spiking
Piping
65nm node and beyond : Ni(Pt 5-10%) replace Ni for defect control.
But … residual surface Pt removal become a challenge !!!
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4. Motivations
 Tostay with current material (NiPt) and
chemistry (SPM) for SALICIDE formation
 To scale NiSi into 28nm CMOS device
 To optimize wet selective etch process
– Support the residual NiPt removal on the film
thickness and Pt% proposed
– Reduce the process cycle time
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5. NiPt Salicide Process
 Process Flow (Fig.1)
Surface preparation: wet + dry in-situ
Metal Dep.: Ni(Pt) + TiN cap→ main focus of this presentation
1st Anneal (RTP-1): 200-300°C range
Selective wet etching→ main focus of this presentation
2nd Anneal (RTP-2): > 500°C
Defect inspection: SEM e-beam BVC inspection
WAT Measurement: Sheet Resistance / Uniformity
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6. Pt Reaction Model
 Common Pt reaction model
- Aqua regia base :
Pt + 4NO3- + 8H +  Pt(4+) + NO2 + 4H2O Silicide
Pt(4+) + 6Cl - + 2H +  H2PtCl6 Attacked !
- Hydrochloric acid base :
Pt + 2H2O2 + 4H +  Pt(4+) + 4H2O
Pt(4+) + 6Cl - + 2H +  H2PtCl6
 Sulfuric Acid Peroxide Pt reaction model
- Sulfuric acid base (main focus of this presentation) Take place
Pt + H2SO4 + H2O2  Pt(OH)2++ + PtO++ + H2SO3 On
high temperature
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7. Batch/SW
Processor Comparison
HT SPM
HT SPM
wafers wafers
wafer
Closed chamber Closed chamber
Fig.2(a) Batch wafer type Fig.2(b) Single wafer type
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8. Pt% / NiPt Film Optimization
on Rs/BVC
increasing film thickness
BVC Count (a.u.)
BVC Count (a.u.)
x15
Low Pt %
5% Pt
NiPt Film High Pt %
10% Pt A B C
Same NiPt film thickness NiPt Thickness
NiPt film thickness (same Pt%)
Fig.3(a) Pt additive on BVC performance Fig. 3(b) NiPt thickness vs. BVC
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9. Pt% / NiPt Film Optimization
on Rs/BVC
Sheet Resistance (a.u.)
BVC Count (a.u.)
BVC - - -
Rs - - - Ο
A B C
NiPt film thickness (same Pt%) Linear ProgramNiPt Thickness thickness / Pt%
for NiPt film
Fig.3(c) Ni thickness vs. Rs Fig.3(d) Linear program for Pt Additive
to NiPt film thickness for BVC and Rs
ISSM 2010 9 G-Number

10. Process Window - Cycle Time
NiPt Thickness B
Low Pt% High Pt%
Batch type
HT SPM
Baseline
Pt-free
Batch type
HT SPM
Baseline
Dual Cycles
Pt-free
Single wafer
). u a e m ssec o P
type
r
HT SPM
Pt-free Pt-free
Fig. 4 (a) Process time comparison Fig.4 (b) Process cycle time
of batch type to single wafer type improvement
it
wet chemical etch processor
. (
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11. Process Window – SW Time
SPM
Process 90 120 150 180 210
time (s)
A Pt-free Pt-free Pt-free - -
High Pt%
NiPt Thickness B - Pt-free Pt-free Pt-free -
(Å)
C - - Pt-free Pt-free Pt-free
Table 1 Process window of single wafer wet etch processor over various
Pt additive and NiPt film thickness
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12. Process Selectivity
Rs Uniformity Variation Range
a N_Diff b P_Diff
NU variation range 0.45% NU variation range 0.35%
Process Time Process Time
c N_Poly d P_Poly
NU variation range 0.49% NU variation range 0.35%
Process Time Process Time
Fig. 5 Rs Uniformity variation range by different wet etch process times
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13. Summary
28nm NiPt Salicide process with co-optimization
of NiPt film thickness, Pt additive and the
complementary wet selective etch processor
Results
• Satisfactory Rs/ Rs uniformity performance
• 15x Improvement on NiSi encroachment through BVC count
• 15x Improvement in cycle time with single wafer system
ISSM 2010 13 G-Number