1. Chapter Four
Transistors
Transistors are three terminal, three-layered, two-
junction electronic devices whose voltage-current
relationship is controlled by a third voltage or current.
We may regard a transistor as a controlled voltage or
current source.
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2. …Cont
Advantages of transistors over
vacuum tubes
• Smaller size, light weight
• No heating elements required
• Low power consumption
• Low operating voltages
Areas of application
signal amplifiers,
electronic switches,
oscillators,
design of digital logics,
memory circuits etc.
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3. Transistor classification
Transistors fall into two main classes:-
bipolar and field effect.
They are also classified according to the semiconductor
material employed:-
silicon or germanium
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4. Bipolar Junction Transistors (BJT)
Specifically the bipolar junction transistor is the three layer
semiconductor devices consisting of either,
two n and one p-type layers of material or two p and one n-
type layers of material.
• The former is called an NPN transistor and the later is
called the PNP transistor.
• The BJT is used in two broad areas-as a linear amplifier
to boost or amplify an electrical signal and as an
electronic switch.
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5. BJT Construction and Operation
Two types of construction exist namely:
1. Thin layer of n-type material sandwiched between two
p-type materials (called a PNP Transistor)
2. Thin layer of p-type material sandwiched between two
n-type materials (called NPN Transistor)
•(a) Basic epitaxial structure of transistor (b) NPN Transistor (c) PNP Transistor
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6. …Cont
Emitter (E) is heavily doped – supplies charge carriers.
Base (B) is lightly doped – allows most of the charge
carriers to pass through it.
Collector is moderately doped(C) – collects the charge
carriers.
there are two junctions shared between the three
terminals:
Emitter-base junction
Collector-base junction
For normal operation,
E-B junction should be forward biased ,and
C-B junction should be reverse biased.
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7. Symbolic Representation
• The following figure shows the symbolic representation
of the PNP and NPN transistors.
• In each case arrow head represents the direction of current
through emitter.
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8. Principles of operation and
characteristics
The working principle of NPN transistor, and PNP
transistor is similar except
the fact that roles of free electrons and holes are
interchanged and current directions are reversed.
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12. BJT Configuration Types
Depending on the terminal common to output and input
there are three types of commonly used transistor
configurations:
Common base configuration.
Common emitter configuration.
Common collector configuration
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13. Common base configuration
In this type of configuration input is applied between emitter
and base and output is taken from the collector and base.
base of the transistor is common to both input and output
circuits and hence common base configuration.
IE and VEB are the input current and input biasing voltage.
IC and VCB are the output current and biasing output
voltages.
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16. Active region
Region to the right of y-axis, where the curves are linear.
When VCB is increased, IC increases slightly. This is
because, when VCB is increased, depletion region width
at C-B junction increases, so effective base width
decreases and IB decreases. This effect is known as early
effect (also called base width modulation).
.
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17. …Cont
Cutoff region: region below IE =0 curve. Here IE is less
than zero (E-B diode is reverse biased) and VCB is
positive (C-B diode is reverse biased) .
Transistor is said to be in OFF state since IC is zero.
Saturation region: Region to the left of y-axis, above
IE =0 curve. Here IE is positive nonzero ,and IC
decreases exponentially.
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18. …Cont
Input resistance: Ratio of change in VEB to
corresponding change in IE, with VCB held constant.
Ri=Δ VEB / Δ IE with VCB constant
Output resistance: Ratio of change in VCB to
corresponding change in IC, with IE held constant.
Ro=Δ VCB /Δ IC with IE constant
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19. …Cont
Voltage gain: Ratio of change in output voltage to
change in input voltage with IE held constant.
Av=Δ VCB /Δ VEB with IE constant.
Current gain: Ratio of change in collector current to
change in emitter current, with VCB held constant.
αac= Δ IC /Δ IE with VCB constant
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20. Common emitter configuration
Emitter is common, base is input terminal and collector is
output terminal..
Common-Emitter configuration
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21. Input characteristics
• VBE is increased, IB increases similar to diode characteristics.
• If VCE is increased, then IB decreases slightly. This is due to early
effect
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23. …Cont
Active region: Region to the right of VCE Sat, above
IB =0 curve, where the curves are linear .
When VCE is increased, IC increases slightly due to
early effect.
If IB is increased, IC also increases.
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24. …Cont
Cut off region: Region below IB =0 curve
Here E-B diode and C-B diode are both reverse biased.
Saturation region: Region to the left of VCE Sat and
right of y-axis. Here E-B diode and C-B diode are both
forward biased
Input resistance: Ratio of change in VBE to
corresponding change in IB, with VCE held constant.
Ri = VBE / IB with VCE constant
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25. …Cont
Output resistance: Ratio of change in VCE to
corresponding change in IC, with IB held constant.
Current gain: Ratio of change in collector current to
change in base current, with VCE held constant
βac = IC/ IB with VCE constant
Voltage gain: Ratio of change in output voltage to change
in input voltage with IB held constant.
AV= VCE / VBE with IB constant
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26. Common Collector Configuration
Collector is common or reference to both input and
output terminals.
IB is the input current and IE is the output current.
The common-collector configuration is used primarily for
impedance-matching purposes since it has a high input
impedance and low output impedance, opposite to that of
the common-base and common-emitter configurations.
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27. …Cont
For all practical purposes, the output characteristics of the
common-collector configuration are the same as for the
common-emitter configuration.
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28. Field Effect Transistors
Field Effect Transistors (FETs) are three terminal
electronic devices used for varieties of application, mostly
similar to BJTs, such as amplifiers, electronic switches and
impedance matching circuits.
However, the field effect transistor differs from bipolar
junction transistor in the following important
characteristics.
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30. Difference Between BJT and FET
1. In FETs an Electric Field is established to control the
conduction path of output devices without the need for direct
contact between the controlling and controlled quantities.
2. It exhibits high input impedance
3. FET’s are less sensitive to temperature variations and
because of their construction they are more easily integrated
on IC’s.
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31. Types of Field Effect Transistors
(The Classification)
JFET
MOSFET (IGFET)
n-Channel JFET
p-Channel JFET
n-Channel
EMOSFET
p-Channel
EMOSFET
Enhancement
MOSFET
Depletion
MOSFET
n-Channel
DMOSFET
p-Channel
DMOSFET
FET
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32. Construction and Characteristics of
Junction Field Effect Transistors (JFETs)
The JFET is a three-terminal
device with one terminal
capable of controlling the
current between the other two.
For the JFET transistor the n-
channel device will appear as
the prominent device.
The major part of the structure
is the n-type material that forms
the channel between the
embedded layers of p-type
material.
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33. …Cont
The top of the n-type channel is connected through an ohmic
contact to a terminal referred to as the drain (D),
while the lower end of the same material is connected through
an ohmic contact to a terminal referred to as the source (S).
The two p-type materials are connected together and to the
gate (G) terminal.
In essence, therefore, the drain and source are connected to the
ends of the n-type channel and the gate to the two layers of p-
type material
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34. Cont…
• In the absence of any applied potentials the JFET has two
p-n junctions under no-bias conditions.
• The result is a depletion region at each junction as shown
in Fig. below that resembles the same region of a diode
under no-bias conditions.
• Recall also that a depletion region is that region void of
free carriers and therefore unable to support conduction
through the region.
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35. …Cont
• A positive voltage VDS has been applied across the
channel and the gate has been connected directly to the
source to establish the condition VGS =0 V.
• The result is a gate and source terminal at the same
potential and a depletion region in the low end of each p-
material similar to the distribution of the no-bias
conditions.
• The instant the voltage VDD (=VDS) is applied, the
electrons will be drawn to the drain terminal, establishing
the conventional current ID with the defined direction.
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36. cont
• The path of charge flow clearly reveals that the drain
and source currents are equivalent (ID =IS). Under
the conditions appearing in the flow of charge is
relatively uninhibited and limited solely by the
resistance of the n-channel between drain and source.
JFET in the VGS = 0V and VDS > 0V
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37. …cont
• The depletion region is wider near the top of both p-
type materials.
• As the voltage VDS is increased from 0 to a few volts,
the current will increase as determined by Ohm’s law
and the plot of ID versus VDS will appear .
• The relative straightness of the plot reveals that for
the region of low values of VDS, the resistance is
essentially constant. As VDS increases and approaches
a level referred to as VP the depletion regions will
widen, causing a noticeable reduction in the channel
width.
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38. …Cont
• The reduced path of conduction causes the resistance to
increase and the curve in the graph to occur.
• The more horizontal the curve, the higher the resistance,
suggesting that the resistance is approaching “infinite”
ohms in the horizontal region.
• If VDS is increased to a level where it appears that the two
depletion regions would “touch” a condition referred to as
pinch-off will result.
• The level of VDS that establishes this condition is referred to
as the pinch-off voltage and is denoted by VP . At pinch-off
ID maintains at saturation level defined as IDSS .
• In reality a very small channel still exists, with a current of
very high density.
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41. ..cont
• As VDS is increased beyond VP, the region of close
encounter between the two depletion regions will
increase in length along the channel, but the level of
ID remains essentially the same.
• In essence, therefore, once VDS >VP the JFET has
the characteristics of a current source. The current is
fixed at ID = IDSS, but the voltage VDS (for levels
>VP) is determined by the applied load.
Current source equivalent for VGs=0, VDS>VP.
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42. ..cont
• Hence; IDSS is the maximum drain current for a
JFET and is defined by the conditions VGS = 0 V and
VDS > |VP|.
• The voltage from gate to source, denoted VGS, is the
controlling voltage of the JFET. Just as various curves
for IC versus VCE were established for different levels
of IB for the BJT transistor, curves of ID versus VDS for
various levels of VGS can be developed for the JFET.
For the n-channel device the controlling voltage VGS
is made more and more negative from its VGS = 0 V
level. In other words, the gate terminal will be set at
lower and lower potential levels as compared to the
source.
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43. ..cont
• A negative voltage of -1 V has been applied between
the gate and source terminals for a low level of VDS.
The effect of the applied negative-bias VGS is to
establish depletion regions similar to those obtained
with VGS = 0 V but at lower levels of VDS. Therefore,
the result of applying a negative bias to the gate is to
reach the saturation level at a lower level of VDS as
shown in Fig. 5.16 for VGS =-1 V.
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44. ..cont
• The resulting saturation level for ID has been reduced and
in fact will continue to decrease as VGS is made more and
more negative. Note also on Fig below how the pinch off
voltage continues to drop in a parabolic manner as VGS
becomes more and more negative. Eventually, VGS when
VGS = -VP will be sufficiently negative to establish a
saturation level that is essentially 0 mA, and for all
practical purposes the device has been “turned off.”
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45. …Cont
Application of a negative voltage to
the gate if JFET
n-Channel JFET characteristics with IDSS
= 8 mA and VP = -5 V.
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46. • The level of VGS that results in ID = 0 mA is defined by
VGS =VP, with VP being a negative voltage for n-
channel devices and a positive voltage for p-channel
JFETs.
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47. P-Channel Devices
• The p-channel JFET is constructed in exactly the
same manner as the n-channel device but with a
reversal of the p- and n-type materials.
P-channel JFET.
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48. • The defined current directions are reversed, as are
the actual polarities for the voltages VGS and VDS.
• For the p-channel device, the channel will be
constricted by increasing positive voltages from
gate to source and the double-subscript notation
for VDS will result in negative voltages for VDS on
the characteristics has an IDSS of 6 mA and a
pinch-off voltage of VGS = +6 V.from the figure
below.
• Do not let the minus signs for VDS confuse you.
They simply indicate that the source is at a higher
potential than the drain.
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52. 52
MOSFET
There are two types of MOSFET’s:
• Depletion mode MOSFET (D-MOSFET)
• Operates in Depletion mode the same way as a JFET
when VGS 0
• Operates in Enhancement mode like E-MOSFET when
VGS > 0
• Enhancement Mode MOSFET (E-MOSFET)
• Operates in Enhancement mode
• IDSS = 0 until VGS > VT (threshold voltage)
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53. 53
Depletion Mode MOSFET
Construction
The Drain (D) and Source (S) leads connect to the to n-doped regions
These N-doped regions are connected via an n-channel
This n-channel is connected to the Gate (G) via a thin insulating layer of SiO2
The n-doped material lies on a p-doped substrate that may have an additional terminal
connection called SS
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55. 55
Basic Operation
A D-MOSFET may be biased to operate in two modes:
Depletion mode or the Enhancement mode
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56. 56
p-Channel Depletion Mode MOSFET
The p-channel Depletion mode MOSFET is similar to the n-channel except that the
voltage polarities and current directions are reversed.
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58. 58
Enhancement Mode MOSFET
Construction
The Drain (D) and Source (S) connect to the to n-doped regions
These n-doped regions are not connected via an n-channel without an external voltage
The Gate (G) connects to the p-doped substrate via a thin insulating layer of SiO2
The n-doped material lies on a p-doped substrate that may have an additional terminal
connection called SS.
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60. 60
Basic Operation
The Enhancement mode MOSFET only operates in the enhancement mode.
VGS is always positive
IDSS = 0 when VGS < VT
As VGS increases above VT, ID increases
If VGS is kept constant and VDS is increased, then ID saturates (IDSS)
The saturation level, VDSsat is reached.
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61. 61
p-Channel Enhancement Mode
MOSFETs
The p-channel Enhancement mode MOSFET is similar to the n-channel except that the
voltage polarities and current directions are reversed.
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