Computer Architecture Degree Program in Applied Computer Science University of Urbino http://informatica.uniurb.it/

1. Carc 05.02
alessandro.bogliolo@uniurb.it
05. CPU
05.02. Reference architecture: DLX
• Minimum instruction set
• Reference architecture
• Reference architecture at work
Computer Architecture
alessandro.bogliolo@uniurb.it

2. Carc 05.02
alessandro.bogliolo@uniurb.it
05 CPU
05.02 Reference architecture: DLX
• Minimum instruction set
• Reference architecture
• Reference architecture at work

3. Carc 05.02
alessandro.bogliolo@uniurb.it
Minimum instruction set
OP Rb Rsd OFFSET
0 6 11 16 31
OP Rs1 Rs2 fALU
0 6 11 16 31
Rd
21
OP IND
0 6 31
OP Rs1 Rs2 OFFSET
0 6 11 16 31
(F3)
(F1)
(F2)
(F2)
Jump instruction
JMP label ;PC  INDx4 000100
Conditional branch
JE R2, R3, dest ;if R2==R3 then PC  PC+OFFSETx4 000101
JS R2, R3, dest ;if R2 < R3 then PC  PC+OFFSETx4 000110
Memory access
LD R1, 100(R2) ;R1  M[R2+100] 000010
ST 200(R1), R2 ;M[R1+200]  R2 000011
Arithmetic/Logic operations
ADD R1, R2, R3 ;R1  R2+R3 000001

4. Carc 05.02
alessandro.bogliolo@uniurb.it
IR
PC1
Reference architecture
WB
ME
EX
A
B
IMM
RW
ID/EX
WB
ME
ALU
out
B
RW
EX/MA
WB
ALU
out
MEM
Dat
RW
MA/WBIF/ID
Instr.
Mem.
PC
Register
file
Alu
Data
Mem.
WB
logic
Register
file
Control
Unit

5. Carc 05.02
alessandro.bogliolo@uniurb.it
IR
Arithmetic operations
WB
EX
A
B
IMM
RW
ID/EX
WB
ALU
out
RW
EX/MA
WB
ALU
out
RW
MA/WBIF/ID
PC
RF
Alu
instruction
OP
RS1
RS2
Rd
fALU RR1
RR2
A
B
RWen
RW
D
CU
A
B
C
OP Rs1 Rs2 fALU
0 6 11 16 31
Rd
21
+
4

6. Carc 05.02
alessandro.bogliolo@uniurb.it
IR
Memory accesses (LD)
WB
ME
EX
A
IMM
RW
ID/EX
WB
ME
ALU
out
RW
EX/MA
WB
MEM
Dat
RW
MA/WBIF/ID
RF
Alu
instruction
OP
Rb
Rsd
OFF
SET RR1
RR2
A
B
RWen
RW
D
CU
A
B
C
OP Rb Rsd OFFSET
0 6 11 16 31
DM
EN RD
ADDR
D
PC
+
4

7. Carc 05.02
alessandro.bogliolo@uniurb.it
IR
Memory accesses (ST)
ME
EX
A
B
IMM
ID/EX
ME
ALU
out
B
EX/MA MA/WBIF/ID
RF
Alu
instruction
OP
Rb
Rsd
OFF
SET RR1
RR2
A
B
RWen
RW
D
CU
A
B
C
OP Rb Rsd OFFSET
0 6 11 16 31
DM
EN WR
ADDR
D
PC
+
4

8. Carc 05.02
alessandro.bogliolo@uniurb.it
IR
Unconditional branch (JMP)
EX
IMM
ID/EX EX/MA MA/WBIF/ID
instruction
OP
IND
CU
OP IND
0 6 31
PC
+
4
JMP

9. Carc 05.02
alessandro.bogliolo@uniurb.it
IR
PC1
Conditional branch (JS, JE)
EX
A
B
IMM
ID/EX EX/MA MA/WBIF/ID
RF
Alu
instruction
OP
Rb
Rsd
OFF
SET RR1
RR2
A
B
RWen
RW
D
CU
A
B
C
OP Rb Rsd OFFSET
0 6 11 16 31
PC
+
4
+
S
Z
JS/JE