Capacitance Sensing - Layout Guidelines for PSoC CapSense

This application note provides layout guidelines for the use of PSoC CapSense technology in electronic designs, emphasizing the importance of minimizing parasitic capacitance and properly routing traces to ensure effective capacitive sensing. Key guidelines include sensor pad placement, trace dimensions, and the effects of ground planes on signal integrity, as well as considerations for the use of flex circuits and multiple PSoCs in complex designs. The document also discusses the relationship between sensor size, button clearance, and capacitance, as well as recommendations for achieving optimal signal-to-noise ratios in CapSense applications.