The race to gain silicon market share in the Enterprise space prompts semiconductor companies to develop SoCs with communication interfaces that provide the highest performance while enjoying broad market adoption. In this presentation we look at the PCIe 5.0 specification and its positioning in the boiling market of high speed interfaces. We review the challenges and pitfalls associated with the implementation of the PCIe5.0 interface protocol and provide some guidelines for successful integration in SoCs.

1. Will PCIe 5.0 become ubiquitous
in tomorrow’s SOCs?
By Trupti Gowda, Sr. FAE, PLDA
1

2. © PLDA 2018 - All Rights Reserved
Agenda
❖ PCIe history and roadmap
❖ Emerging interconnect standards
➢ Overview
➢ Trends
❖ PCIe 5.0 overview
❖ PCIe 5.0 IP and market perspective
❖ Final thoughts
2

3. © PLDA 2018 - All Rights Reserved
The Evolution of PCIe® 3
2003
2006
2010
2017
2019
PCIe 1.0 @ 2.5GT/s
PCIe 2.0 @ 5.0GT/s
PCIe 3.0 @ 8.0GT/s
PCIe 4.0 @ 16GT/s
PCIe 5.0 @ 32GT/s

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The Data Center I/O Push 4
1
10
100
1000
Rate
(Gbit/s)
Gigabit Ethernet
10 Gigabit Ethernet
100 Gigabit Ethernet
2005 2010 2015 2020
PCIe 1.0 x1
PCIe 1.0 x16
PCIe 2.0 x1
PCIe 3.0 x1
PCIe 4.0 x1
PCIe 2.0 x16
PCIe 3.0 x16
PCIe 4.0 x16
PCIe 5.0 x16
PCIe 5.0 x1
400 Gigabit Ethernet
40 Gigabit Ethernet

5. © PLDA 2018 - All Rights Reserved
Emerging Interconnect Standards
❖ Push for more I/O bandwidth and delayed PCIe 4.0 explain
emergence of new interconnect standards in 2016
5
CCIX: Cache Coherent
Interconnect for Accelerators
- Up to 25Gbps per lane
- PCIe PHY and Link layers
- Cache coherence across link
Gen-Z: Memory Semantic
Interconnect
- IEEE 802.3 or PCIe PHY
- Load/store model
- Long haul/rack-to-rack
OpenCAPI: Open Coherent
Accelerator Processor Interface
- IEEE 802.3 PHY
- Up to x32 (OpenCAPI 4.0)
- Support caching

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Quick Spec Comparison 6
Source: OpenCAPI, Gen-Z, CCIX: Technology overview, trends, and alignments - Brad Benton, AMD, August 2017

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OpenCAPI 3.0
Gen-Z 1.0
CCIX 1.0
PCIe 5.0
PCIe 4.0
Market Deployment Status 7
2016 2017 2018 2019 2020
Spec r1.0
Silicon rollout
Spec r1.0
Spec r1.0
Spec r1.0
Spec r1.0
Silicon rollout
Silicon rollout
Silicon rollout
Silicon rollout (POWER9)

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SoC Perspective - Short Term
Current generation SoCs likely to support multiple standards
❖ Need to future-proof SoC
❖ Current NRZ PHY technology exists and supports all
➢ Ex. A 25G PHY IP covers PCIe 4.0, CCIX, OpenCAPI, Gen-Z
❖ Controller IP exist and account for little in SoC cost and size
❖ SoC vendors are often multi-consortium members
➢ Have an interest in standards success
Ex. IBM POWER9 Processor with PCIe 4.0 and OpenCAPI 3.0
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Convergence on the Horizon?
❖ Unlikely PCIe will go away anytime soon
➢ Well anchored in x86 ecosystem
➢ Huge SW/FW legacy
➢ Agressive 5.0 roadmap
❖ What about coherency for accelerators?
➢ OpenCAPI for POWER® Architecture?
➢ CCIX everywhere else?
➢ Coherency extensions (ECN) for PCIe?
❖ Gen-Z could find a place at the edge for long-haul/rack-to-
rack/decentralized SCM communication
9

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A look at PCIe 5.0
Focus on signal integrity and low power
10
Signal Integrity
❖PHY Layer changes & additions
➢Support for 32Gbps
➢EIEOS update, SKP OS update
➢New physical connector
❖ Same 128B/130B encoding
❖ No changes at Link and
Transaction layers
Low Power
❖ Rich set of Link and Device States
❖ L0s, L1, L1-substates, L2/L3
❖ D0, D1, D2, D3_hot/cold
❖ Platform-level power optimization
hooks: Dynamic Power Allocation,
Optimized Buffer Flush/Fill, Latency
Tolerance Reporting
❖ Active power –5pJ/b, Standby
power: 10uW/Lane

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PCIe 5.0 from an IP Perspective
❖ PHY IP
➢ Available from various vendors, up to 56G (NRZ)
➢ PIPE 5.x compatibility required
■ 32-bit @1Ghz or 64-bit @500Mhz
❖ Controller IP
➢ 512-bit data path a must
■ 1Ghz application clock @x16 link
➢ Available from various vendors
❖ Verification IP
➢ Available from various vendors
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PCIe 5.0 Market Adoption
❖ Enterprise Storage (NVMe) SoCs
➢ Higher performance with same or lower link width (constrained form
factors)
❖ Enterprise Networking SoCs
➢ 100G->400G Ethernet
❖ HPC/AI/ML SoCs
➢ More co-processing throughput
❖ Some Automotive SoCs
➢ AI processing at the edge for autonomous driving
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Final Thoughts
❖ PCIe 5.0 to prevail in high-end applications
➢ Esp. within the x86 ecosystem
➢ Enterprise/data center SoCs
❖ PCIe 4.0 and 3.0 not going away
➢ Consumer and legacy markets
❖ Emerging protocols may find their niche
➢ CCIX: Accelerator-to-accelerator, non-x86-cpu-to-accelerator
➢ OpenCAPI: POWER architecture ecosystem
➢ Gen-Z: Disaggregated data center, rack-to-rack interconnect, SCM
interconnect
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14. THANK YOU!
14▪ Any question?