This document presents a simplified space vector pulse-width modulation (SVPWM) scheme for three-phase cascaded H-bridge inverters. It treats each unit as a three-level inverter and uses three-level SVPWM to modulate each unit individually. Duty cycles from sector 1 are mapped to obtain duty cycles for other sectors. This simplifies the process compared to conventional multilevel SVPWM. Simulation and experimental results validate the presented SVPWM scheme, which provides a higher effective switching frequency while maintaining the same DC-link voltage utilization as conventional SVPWM, with significantly reduced FPGA resource utilization.

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A Simplified Space Vector Pulse-Width Modulation Scheme
for Three-Phase Cascaded H-bridge Inverters
ABSTRACT:
A simplified space vector pulse-width modulation (SVPWM) for three-phase cascaded H-bridge
(CHB) inverters is presented in this paper. Treating each unit as a three-level inverter and
adopting serial calculation mode, a CHB inverter is modulated unit by unit using three-level
SVPWM. Duty cycles of real sector are obtained by mapping duty cycles of sector 1, in which
the calculation of three-level SVPWM is done. The process to implement multilevel SVPWM is
simplified to the process to implement three-level SVPWM. By reusing FPGA chip resource
which is used for the calculation of three-level SVPWM, the presented SVPWM can be easily
adopted to a CHB inverter with different number of units, while the FPGA chip resource
utilization is reduced significantly. In addition, the presented SVPWM provides an effective
switching frequency higher than the switching frequency of IGBTs. Simulation and experimental
results are provided to verify the feasibility of the presented SVPWM.
KEYWORDS:
1. Three-phase CHB multilevel inverter
2. Space vector modulation (SVM)
3. Space vector pulse-width modulation (SVPWM)
4. Field programmable gate array (FPGA)
SOFTWARE: MATLAB/SIMULINK

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CONCLUSION:
This paper presents a simplified SVPWM scheme for three-phase CHB inverters. Treating each
unit as a three-level inverter and adopting serial calculation mode, a three-phase CHB inverter
with n units is modulated unit by unit by using three-level SVPWM instead of using multilevel
SVPWM. Then, duty cycles of sector N used to generate gate pulses are obtained by mapping
duty cycles of sector 1. Based on principles of the presented SVPWM, the tedious process to
implement the conventional multilevel SVPWM is simplified significantly. By reusing FPGA
chip resources which are used to do the calculation of three-level SVPWM, the presented
SVPWM can be easily adopted to a three-phase CHB inverter with different number of units.
Simulation and experimental results are used to validate the presented SVPWM. The presented
SVPWM provides a higher effective switching frequency of nfs, while maintains the same dc-
link voltage utilization as that of the conventional SVPWM. Compared with the conventional
SVPWM, FPGA chip resource utilization of the presented SVPWM is reduced significantly,
while the FPGA resource utilization increment of the presented SVPWM is controlled without
dramatically increasing.
REFERENCES:
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