The document discusses image enhancement techniques for use in multiprocessor systems-on-chip (MPSoC). It reviews existing image enhancement methods implemented on FPGA and identifies limitations like low accuracy. The paper proposes using advanced bus architectures like AMBA/AXI in MPSoC to improve communication between memory and input medical images for enhancement, reducing heterogeneity effects. It summarizes various image enhancement algorithms that could be implemented on reconfigurable FPGA hardware for use in MPSoC, including brightness control, contrast stretching, histogram equalization, and edge detection techniques.
AN OPTIMIZED BLOCK ESTIMATION BASED IMAGE COMPRESSION AND DECOMPRESSION ALGOR...IAEME Publication
This document presents a new optimized block estimation based image compression and decompression algorithm. The proposed method divides images into blocks and estimates each block from the previous frame using sum of absolute differences to determine the best matching block. It then compresses the luminance channel using JPEG-LS coding and predicts chrominance channels using hierarchical decomposition and directional prediction. Experimental results on test images show the proposed method achieves higher compression rates and lower distortion compared to traditional models that use hierarchical schemes and raster scan prediction.
Face recognition using assemble of low frequency of DCT featuresjournalBEEI
Face recognition is a challenge due to facial expression, direction, light, and scale variations. The system requires a suitable algorithm to perform recognition task in order to reduce the system complexity. This paper focuses on a development of a new local feature extraction in frequency domain to reduce dimension of feature space. In the propose method, assemble of DCT coefficients are used to extract important features and reduces the features vector. PCA is performed to further reduce feature dimension by using linear projection of original image. The proposed of assemble low frequency coefficients and features reduction method is able to increase discriminant power in low dimensional feature space. The classification is performed by using the Euclidean distance score between the projection of test and train images. The algorithm is implemented on DSP processor which has the same performance as PC based. The experiment is conducted using ORL standard face databases the best performance achieved by this method is 100%. The execution time to recognize 40 peoples is 0.3313 second when tested using DSP processor. The proposed method has a high degree of recognition accuracy and fast computational time when implemented in embedded platform such as DSP processor.
Conference Proceedings of the National Level Technical Symposium on Emerging Trends in Technology, TECHNOVISION ’10, G.N.D.E.C. Ludhiana, Punjab, India- 9th-10th April, 2010
Efficient Image Compression Technique using Clustering and Random PermutationIJERA Editor
Multimedia data compression is a challenging situation for compression technique, due to the possibility of loss
of data as well as it require large amount of storage place. The minimization of storage place and proper
transmission of these data need compression. In this dissertation we proposed a block based DWT image
compression technique using genetic algorithm and HCC code matrix. The HCC code matrix compressed into
two different set redundant and non-redundant which generate similar pattern of block coefficient. The similar
block coefficient generated by particle of swarm optimization. The process of particle of swarm optimization is
select for the optimal block of DWT transform function. For the experimental purpose we used some standard
image such as Lena, Barbara and cameraman image. The size of resolution of this image is 256*256. The source
of image is Google.
HARDWARE SOFTWARE CO-SIMULATION OF MOTION ESTIMATION IN H.264 ENCODERcscpconf
This paper proposes about motion estimation in H.264/AVC encoder. Compared with standards
such as MPEG-2 and MPEG-4 Visual, H.264 can deliver better image quality at the same
compressed bit rate or at a lower bit rate. The increase in compression efficiency comes at the
expense of increase in complexity, which is a fact that must be overcome. An efficient Co-design
methodology is required, where the encoder software application is highly optimized and
structured in a very modular and efficient manner, so as to allow its most complex and time
consuming operations to be offloaded to dedicated hardware accelerators. The Motion
Estimation algorithm is the most computationally intensive part of the encoder which is simulated using MATLAB. The hardware/software co-simulation is done using system generator tool and implemented using Xilinx FPGA Spartan 3E for different scanning methods.
International Journal of Computational Engineering Research(IJCER)ijceronline
The document discusses image compression using artificial neural networks. It begins with an introduction to image compression and the need for it. Then it reviews various existing neural network approaches for image compression, including backpropagation networks, hierarchical networks, multilayer feedforward networks, and radial basis function networks. It proposes a new approach using a multilayer perceptron with a modified Levenberg-Marquardt training algorithm to improve compression performance. Authentication and protection would be incorporated by exploiting the one-to-one mapping and one-way properties of neural networks. The proposed system is described as compressing images using neural networks trained with a modified LM algorithm to achieve high compression ratios while maintaining image quality.
Ray-casting implementations require that the connectivity
between the cells of the dataset to be explicitly computed
and kept in memory. This constitutes a huge obstacle
for obtaining real-time rendering for very large models.
In this paper, we address this problem by introducing
a new implementation of the ray-casting algorithm for irregular
datasets. Our implementation optimizes the memory
usage of past implementations by exploring ray coherence.
The idea is to keep in main memory the information of
the faces traversed by the ray cast through every pixel under
the projection of a visible face. Our results show that
exploring pixel coherence reduces considerably the memory
usage, while keeping the performance of our algorithm
competitive with the fastest previous ones.
A Comparative Case Study on Compression Algorithm for Remote Sensing ImagesDR.P.S.JAGADEESH KUMAR
This document summarizes research on compression algorithms for remote sensing images. It begins with an abstract describing the challenges of transmitting large remote sensing images from sensors to networks. The document then reviews 18 different research papers on various compression algorithms for remote sensing images, including wavelet-based algorithms, fractal coding methods, and region-based approaches. It evaluates each algorithm's performance in compressing remote sensing images while maintaining quality. The document aims to perform a comparative case study of these different compression algorithms.
AN OPTIMIZED BLOCK ESTIMATION BASED IMAGE COMPRESSION AND DECOMPRESSION ALGOR...IAEME Publication
This document presents a new optimized block estimation based image compression and decompression algorithm. The proposed method divides images into blocks and estimates each block from the previous frame using sum of absolute differences to determine the best matching block. It then compresses the luminance channel using JPEG-LS coding and predicts chrominance channels using hierarchical decomposition and directional prediction. Experimental results on test images show the proposed method achieves higher compression rates and lower distortion compared to traditional models that use hierarchical schemes and raster scan prediction.
Face recognition using assemble of low frequency of DCT featuresjournalBEEI
Face recognition is a challenge due to facial expression, direction, light, and scale variations. The system requires a suitable algorithm to perform recognition task in order to reduce the system complexity. This paper focuses on a development of a new local feature extraction in frequency domain to reduce dimension of feature space. In the propose method, assemble of DCT coefficients are used to extract important features and reduces the features vector. PCA is performed to further reduce feature dimension by using linear projection of original image. The proposed of assemble low frequency coefficients and features reduction method is able to increase discriminant power in low dimensional feature space. The classification is performed by using the Euclidean distance score between the projection of test and train images. The algorithm is implemented on DSP processor which has the same performance as PC based. The experiment is conducted using ORL standard face databases the best performance achieved by this method is 100%. The execution time to recognize 40 peoples is 0.3313 second when tested using DSP processor. The proposed method has a high degree of recognition accuracy and fast computational time when implemented in embedded platform such as DSP processor.
Conference Proceedings of the National Level Technical Symposium on Emerging Trends in Technology, TECHNOVISION ’10, G.N.D.E.C. Ludhiana, Punjab, India- 9th-10th April, 2010
Efficient Image Compression Technique using Clustering and Random PermutationIJERA Editor
Multimedia data compression is a challenging situation for compression technique, due to the possibility of loss
of data as well as it require large amount of storage place. The minimization of storage place and proper
transmission of these data need compression. In this dissertation we proposed a block based DWT image
compression technique using genetic algorithm and HCC code matrix. The HCC code matrix compressed into
two different set redundant and non-redundant which generate similar pattern of block coefficient. The similar
block coefficient generated by particle of swarm optimization. The process of particle of swarm optimization is
select for the optimal block of DWT transform function. For the experimental purpose we used some standard
image such as Lena, Barbara and cameraman image. The size of resolution of this image is 256*256. The source
of image is Google.
HARDWARE SOFTWARE CO-SIMULATION OF MOTION ESTIMATION IN H.264 ENCODERcscpconf
This paper proposes about motion estimation in H.264/AVC encoder. Compared with standards
such as MPEG-2 and MPEG-4 Visual, H.264 can deliver better image quality at the same
compressed bit rate or at a lower bit rate. The increase in compression efficiency comes at the
expense of increase in complexity, which is a fact that must be overcome. An efficient Co-design
methodology is required, where the encoder software application is highly optimized and
structured in a very modular and efficient manner, so as to allow its most complex and time
consuming operations to be offloaded to dedicated hardware accelerators. The Motion
Estimation algorithm is the most computationally intensive part of the encoder which is simulated using MATLAB. The hardware/software co-simulation is done using system generator tool and implemented using Xilinx FPGA Spartan 3E for different scanning methods.
International Journal of Computational Engineering Research(IJCER)ijceronline
The document discusses image compression using artificial neural networks. It begins with an introduction to image compression and the need for it. Then it reviews various existing neural network approaches for image compression, including backpropagation networks, hierarchical networks, multilayer feedforward networks, and radial basis function networks. It proposes a new approach using a multilayer perceptron with a modified Levenberg-Marquardt training algorithm to improve compression performance. Authentication and protection would be incorporated by exploiting the one-to-one mapping and one-way properties of neural networks. The proposed system is described as compressing images using neural networks trained with a modified LM algorithm to achieve high compression ratios while maintaining image quality.
Ray-casting implementations require that the connectivity
between the cells of the dataset to be explicitly computed
and kept in memory. This constitutes a huge obstacle
for obtaining real-time rendering for very large models.
In this paper, we address this problem by introducing
a new implementation of the ray-casting algorithm for irregular
datasets. Our implementation optimizes the memory
usage of past implementations by exploring ray coherence.
The idea is to keep in main memory the information of
the faces traversed by the ray cast through every pixel under
the projection of a visible face. Our results show that
exploring pixel coherence reduces considerably the memory
usage, while keeping the performance of our algorithm
competitive with the fastest previous ones.
A Comparative Case Study on Compression Algorithm for Remote Sensing ImagesDR.P.S.JAGADEESH KUMAR
This document summarizes research on compression algorithms for remote sensing images. It begins with an abstract describing the challenges of transmitting large remote sensing images from sensors to networks. The document then reviews 18 different research papers on various compression algorithms for remote sensing images, including wavelet-based algorithms, fractal coding methods, and region-based approaches. It evaluates each algorithm's performance in compressing remote sensing images while maintaining quality. The document aims to perform a comparative case study of these different compression algorithms.
IRJET- An Efficient VLSI Architecture for 3D-DWT using Lifting SchemeIRJET Journal
This document proposes an efficient VLSI architecture for 3D discrete wavelet transform (DWT) using the lifting scheme. The lifting scheme implementation of DWT has lower area, power consumption and computational complexity compared to convolution-based DWT. The proposed architecture achieves reductions in total area and power compared to existing convolution DWT and discrete cosine transform architectures. It evaluates the performance in terms of area analysis, timing reports, and output matrices after 1D, 2D and 3D DWT using both convolution and lifting schemes. The results show that the lifting scheme provides better compression performance with less area and delay.
Estimation of Optimized Energy and Latency Constraint for Task Allocation in ...ijcsit
In Network on Chip (NoC) rooted system, energy consumption is affected by task scheduling and allocation
schemes which affect the performance of the system. In this paper we test the pre-existing proposed
algorithms and introduced a new energy skilled algorithm for 3D NoC architecture. An efficient dynamic
and cluster approaches are proposed along with the optimization using bio-inspired algorithm. The
proposed algorithm has been implemented and evaluated on randomly generated benchmark and real life
application such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark
and has been compared with the existing mapping algorithm spiral and crinkle and has shown better
reduction in the communication energy consumption and shows improvement in the performance of the
system. On performing experimental analysis of proposed algorithm results shows that average reduction
in energy consumption is 49%, reduction in communication cost is 48% and average latency is 34%.
Cluster based approach is mapped onto NoC using Dynamic Diagonal Mapping (DDMap), Crinkle and
Spiral algorithms and found DDmap provides improved result. On analysis and comparison of mapping of
cluster using DDmap approach the average energy reduction is 14% and 9% with crinkle and spiral.
Artificial Neural Network (ANN) is a fast-growing method which has been used in different
industries during recent years. The main idea for creating ANN which is a subset of artificial
intelligence is to provide a simple model of human brain in order to solve complex scientific and
industrial problems. ANNs are high-value and low-cost tools in modelling, simulation, control,
condition monitoring, sensor validation and fault diagnosis of different systems. It have high
flexibility and robustness in modeling, simulating and diagnosing the behavior of rotating machines
even in the presence of inaccurate input data. They can provide high computational speed for
complicated tasks that require rapid response such as real-time processing of several simultaneous
signals. ANNs can also be used to improve efficiency and productivity of energy in rotating
equipment
Iaetsd a low power and high throughput re-configurable bip for multipurpose a...Iaetsd Iaetsd
This document presents a reconfigurable low power binary image processor for image processing applications. The processor consists of a reconfigurable binary processing module with mixed-grained architecture providing flexibility, efficiency and performance. Line memories are selected for lower power consumption and clock gating technique is used to reduce their power. The processor supports real-time binary image processing operations like morphological transformations and is suitable for applications like object recognition and tracking.
HOMOGENEOUS MULTISTAGE ARCHITECTURE FOR REAL-TIME IMAGE PROCESSINGcscpconf
The document describes a homogeneous multistage architecture for real-time image processing. It proposes a parallel architecture using multiple identical processing elements connected by different communication links. As an example application, it discusses a multi-hypothesis approach for road recognition, which uses multiple hypotheses to detect and track road edges in video in real-time. Experimental results using a FPGA demonstrate the architecture can detect roadsides in images within 60 milliseconds.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
IRJET- Different Approaches for Implementation of Fractal Image Compressi...IRJET Journal
This document discusses different approaches for implementing fractal image compression on medical images using parallel processing on GPUs. It analyzes fractal image compression algorithms in MATLAB to compress medical images with very low loss in image quality. The key aspects covered are:
1. Fractal image compression uses self-similarity within images to achieve high compression ratios while preserving image quality.
2. Implementing fractal compression in parallel on GPUs can significantly reduce computational time compared to CPU implementations, as the redundant processing can be distributed across multiple processors.
3. The document implements and evaluates different fractal compression algorithms on MATLAB to compress medical images with low signal-to-noise ratio, high compression ratio, and reduced encoding time.
The Computation Complexity Reduction of 2-D Gaussian FilterIRJET Journal
This document discusses reducing the computational complexity of a 2D Gaussian filter for image smoothing. It begins with an abstract that notes 2D Gaussian filters are commonly used for image smoothing but require heavy computational resources. It then proposes using fixed-point arithmetic rather than floating point to implement the filter on an FPGA, which can increase efficiency and decrease area and complexity. The document is divided into sections that cover the theory behind image filtering, image smoothing and sharpening, quality metrics for evaluation, and an energy scalable Gaussian smoothing filter architecture. It concludes by discussing results and benefits of implementing the filter using fixed-point arithmetic on an FPGA.
This document discusses image processing and summarizes several key techniques. It begins by defining image processing and describing how images are digitized and processed. It then summarizes three main categories of image processing: image enhancement, image restoration, and image compression. Specific techniques discussed include contrast stretching, density slicing, and edge enhancement. The document also discusses visual saliency models, motion saliency, and using conditional random fields for video object extraction.
IntelliSuite is a complete design environment for MEMS that provides tools across the entire product development cycle. It includes schematic capture tool Synple, physical design tool Blueprint, process design tools CleanRoom, and multiphysics solvers FastField. IntelliSuite aims to link the entire MEMS organization through a unified platform. It offers a seamless flow from concept to tapeout through integrated tools for simulation, layout, verification, and more. IntelliSuite has established itself as the standard industry tool used by MEMS professionals worldwide.
IRJET- Exploring Image Super Resolution TechniquesIRJET Journal
This document discusses image super resolution techniques. It begins by defining super resolution as a technique that reconstructs a high resolution image from low resolution images. It then provides an overview of different super resolution methods including interpolation-based, reconstruction-based, and example-based (machine learning) techniques. The document evaluates state-of-the-art super resolution generative adversarial network (SRGAN) methods and their ability to generate realistic high resolution images from low resolution inputs. It also reviews the history and compares different super resolution techniques.
This document discusses compression of compound images using wavelet transform. It begins by introducing compound images, which contain different data types like text and graphics. Transmitting high resolution compound images over networks poses challenges due to large file sizes. The document then discusses using wavelet sub-band coding for lossless compression of compound images, which allows for excellent quality of text in compressed images. It provides details on image segmentation techniques like block-based segmentation that classify image blocks to compress according to image type.
An Algorithm for Improving the Quality of Compacted JPEG Image by Minimizes t...ijcga
The Block Transform Coded, JPEG- a lossy image compression format has been used to keep storage and
bandwidth requirements of digital image at practical levels. However, JPEG compression schemes may
exhibit unwanted image artifacts to appear - such as the ‘blocky’ artifact found in smooth/monotone areas
of an image, caused by the coarse quantization of DCT coefficients. A number of image filtering
approaches have been analyzed in literature incorporating value-averaging filters in order to smooth out
the discontinuities that appear across DCT block boundaries. Although some of these approaches are able
to decrease the severity of these unwanted artifacts to some extent, other approaches have certain
limitations that cause excessive blurring to high-contrast edges in the image. The image deblocking
algorithm presented in this paper aims to filter the blocked boundaries. This is accomplished by employing
smoothening, detection of blocked edges and then filtering the difference between the pixels containing the
blocked edge. The deblocking algorithm presented has been successful in reducing blocky artifacts in an
image and therefore increases the subjective as well as objective quality of the reconstructed image.
This document proposes a multi-level block truncation code algorithm for RGB image compression to achieve low bit rates and high quality. The algorithm combines bit mapping and quantization by dividing images into blocks, calculating thresholds, quantizing thresholds, and representing blocks with bit maps. It was tested on standard images like flowers, Lena, and baboon. Results showed improved peak signal-to-noise ratio and mean squared error compared to existing methods, demonstrating the effectiveness of the proposed multi-level block truncation code algorithm for image compression.
Remote HD and 3D image processing challenges in Embedded Systems
The Modern Applications has increased the complexity and demands of the video processing features and subsequent image data transfer.
The Image Processing mission will typically comprise three key elements: data capture, data processing, and data transmission. In addition, applications such as Recognition and data fusion have a need for time sensitivity, spatial awareness, and mutual awareness to correctly understand and utilize the data.
Low-latency processing and transmission are key performance metrics, particularly where there is a human operator and key decision maker situated in a location remote from the point of data gathering. An examination of key considerations – sensor processing location trends, video fusion, and video compression and bandwidth, in addition to Size, Weight, and Power
Comparative Study of Neural Networks Algorithms for Cloud Computing CPU Sched...IJECEIAES
Cloud Computing is the most powerful computing model of our time. While the major IT providers and consumers are competing to exploit the benefits of this computing model in order to thrive their profits, most of the cloud computing platforms are still built on operating systems that uses basic CPU (Core Processing Unit) scheduling algorithms that lacks the intelligence needed for such innovative computing model. Correspdondingly, this paper presents the benefits of applying Artificial Neural Networks algorithms in regards to enhancing CPU scheduling for Cloud Computing model. Furthermore, a set of characteristics and theoretical metrics are proposed for the sake of comparing the different Artificial Neural Networks algorithms and finding the most accurate algorithm for Cloud Computing CPU Scheduling.
Real-Time Implementation and Performance Optimization of Local Derivative Pat...IJECEIAES
Pattern based texture descriptors are widely used in Content Based Image Retrieval (CBIR) for efficient retrieval of matching images. Local Derivative Pattern (LDP), a higher order local pattern operator, originally proposed for face recognition, encodes the distinctive spatial relationships contained in a local region of an image as the feature vector. LDP efficiently extracts finer details and provides efficient retrieval however, it was proposed for images of limited resolution. Over the period of time the development in the digital image sensors had paid way for capturing images at a very high resolution. LDP algorithm though very efficient in content-based image retrieval did not scale well when capturing features from such high-resolution images as it becomes computationally very expensive. This paper proposes how to efficiently extract parallelism from the LDP algorithm and strategies for optimally implementing it by exploiting some inherent General-Purpose Graphics Processing Unit (GPGPU) characteristics. By optimally configuring the GPGPU kernels, image retrieval was performed at a much faster rate. The LDP algorithm was ported on to Compute Unified Device Architecture (CUDA) supported GPGPU and a maximum speed up of around 240x was achieved as compared to its sequential counterpart.
IRJET - Wavelet based Image Fusion using FPGA for Biomedical ApplicationIRJET Journal
This document describes a wavelet-based image fusion system implemented on an FPGA for biomedical applications. The system takes two input images, applies discrete wavelet transforms to both, then fuses the wavelet coefficients to create a single output image. It uses MATLAB and Xilinx System Generator to simulate the design in Simulink and implement it on a Virtex6 FPGA. The results show that wavelet-based fusion can combine the spatial and spectral information from multiple input images into a higher quality fused output image suitable for medical applications like fusing MRI and CT scans.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
This document provides an overview of a project that implemented image filtering using VHDL on an FPGA board. It discusses designing filters like average, Sobel, Gaussian, and Laplacian filters. Cache memory and a processing unit were developed to hold pixel values and apply filter kernels. Different methods for multiplication in the convolution process were evaluated. Results showed the output images after applying each filter both in software and on the FPGA board. In conclusion, FPGAs provide reconfigurable, accelerated processing for image applications like filtering compared to general purpose computers.
Image processing has become under the spotlight recently and leads to a
significant shift in various fields such as biomedical, satellite images, and
graphical applications. Nevertheless, the poor quality of an image is one of
the noticeable limitations of image processing as it restricts efficient data
extraction to be conducted. Conventionally, the image was processed via
software applications such as MATLAB. In spite of the software's ability to
cater to the data extraction of low-quality image issues, it still suffers from the
time-consuming issue. As the ability to obtain a rapid outcome is a favorable
feature of efficient image processing, the use of hardware in image processing
is deemed to keep the addressed issue at bay. Thus, the image enhancement
techniques using hardware have gradually rising interest among researchers
with numerous approaches such as field programmable gate array (FPGA). In
this study, 25 different research papers published from 2016 to 2021 are
studied and analyzed to focus on the performance of FPGA as hardware
implementation in image processing techniques.
A Smart Camera Processing Pipeline for Image Applications Utilizing Marching ...sipij
Image processing in machine vision is a challenging task because often real-time requirements have to be met in these systems. To accelerate the processing tasks in machine vision and to reduce data transfer latencies, new architectures for embedded systems in intelligent cameras are required. Furthermore, innovative processing approaches are necessary to realize these architectures efficiently. Marching Pixels are such a processing scheme, based on Organic Computing principles, and can be applied for example to determine object centroids in binary or gray-scale images. In this paper, we present a processing pipeline for smart camera systems utilizing such Marching Pixel algorithms. It consists of a buffering template for image pre-processing tasks in a FPGA to enhance captured images and an ASIC for the efficient realization of Marching Pixel approaches. The ASIC achieves a speedup of eight for the realization of Marching Pixel algorithms, compared to a common medium performance DSP platform.
IRJET- An Efficient VLSI Architecture for 3D-DWT using Lifting SchemeIRJET Journal
This document proposes an efficient VLSI architecture for 3D discrete wavelet transform (DWT) using the lifting scheme. The lifting scheme implementation of DWT has lower area, power consumption and computational complexity compared to convolution-based DWT. The proposed architecture achieves reductions in total area and power compared to existing convolution DWT and discrete cosine transform architectures. It evaluates the performance in terms of area analysis, timing reports, and output matrices after 1D, 2D and 3D DWT using both convolution and lifting schemes. The results show that the lifting scheme provides better compression performance with less area and delay.
Estimation of Optimized Energy and Latency Constraint for Task Allocation in ...ijcsit
In Network on Chip (NoC) rooted system, energy consumption is affected by task scheduling and allocation
schemes which affect the performance of the system. In this paper we test the pre-existing proposed
algorithms and introduced a new energy skilled algorithm for 3D NoC architecture. An efficient dynamic
and cluster approaches are proposed along with the optimization using bio-inspired algorithm. The
proposed algorithm has been implemented and evaluated on randomly generated benchmark and real life
application such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark
and has been compared with the existing mapping algorithm spiral and crinkle and has shown better
reduction in the communication energy consumption and shows improvement in the performance of the
system. On performing experimental analysis of proposed algorithm results shows that average reduction
in energy consumption is 49%, reduction in communication cost is 48% and average latency is 34%.
Cluster based approach is mapped onto NoC using Dynamic Diagonal Mapping (DDMap), Crinkle and
Spiral algorithms and found DDmap provides improved result. On analysis and comparison of mapping of
cluster using DDmap approach the average energy reduction is 14% and 9% with crinkle and spiral.
Artificial Neural Network (ANN) is a fast-growing method which has been used in different
industries during recent years. The main idea for creating ANN which is a subset of artificial
intelligence is to provide a simple model of human brain in order to solve complex scientific and
industrial problems. ANNs are high-value and low-cost tools in modelling, simulation, control,
condition monitoring, sensor validation and fault diagnosis of different systems. It have high
flexibility and robustness in modeling, simulating and diagnosing the behavior of rotating machines
even in the presence of inaccurate input data. They can provide high computational speed for
complicated tasks that require rapid response such as real-time processing of several simultaneous
signals. ANNs can also be used to improve efficiency and productivity of energy in rotating
equipment
Iaetsd a low power and high throughput re-configurable bip for multipurpose a...Iaetsd Iaetsd
This document presents a reconfigurable low power binary image processor for image processing applications. The processor consists of a reconfigurable binary processing module with mixed-grained architecture providing flexibility, efficiency and performance. Line memories are selected for lower power consumption and clock gating technique is used to reduce their power. The processor supports real-time binary image processing operations like morphological transformations and is suitable for applications like object recognition and tracking.
HOMOGENEOUS MULTISTAGE ARCHITECTURE FOR REAL-TIME IMAGE PROCESSINGcscpconf
The document describes a homogeneous multistage architecture for real-time image processing. It proposes a parallel architecture using multiple identical processing elements connected by different communication links. As an example application, it discusses a multi-hypothesis approach for road recognition, which uses multiple hypotheses to detect and track road edges in video in real-time. Experimental results using a FPGA demonstrate the architecture can detect roadsides in images within 60 milliseconds.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
IRJET- Different Approaches for Implementation of Fractal Image Compressi...IRJET Journal
This document discusses different approaches for implementing fractal image compression on medical images using parallel processing on GPUs. It analyzes fractal image compression algorithms in MATLAB to compress medical images with very low loss in image quality. The key aspects covered are:
1. Fractal image compression uses self-similarity within images to achieve high compression ratios while preserving image quality.
2. Implementing fractal compression in parallel on GPUs can significantly reduce computational time compared to CPU implementations, as the redundant processing can be distributed across multiple processors.
3. The document implements and evaluates different fractal compression algorithms on MATLAB to compress medical images with low signal-to-noise ratio, high compression ratio, and reduced encoding time.
The Computation Complexity Reduction of 2-D Gaussian FilterIRJET Journal
This document discusses reducing the computational complexity of a 2D Gaussian filter for image smoothing. It begins with an abstract that notes 2D Gaussian filters are commonly used for image smoothing but require heavy computational resources. It then proposes using fixed-point arithmetic rather than floating point to implement the filter on an FPGA, which can increase efficiency and decrease area and complexity. The document is divided into sections that cover the theory behind image filtering, image smoothing and sharpening, quality metrics for evaluation, and an energy scalable Gaussian smoothing filter architecture. It concludes by discussing results and benefits of implementing the filter using fixed-point arithmetic on an FPGA.
This document discusses image processing and summarizes several key techniques. It begins by defining image processing and describing how images are digitized and processed. It then summarizes three main categories of image processing: image enhancement, image restoration, and image compression. Specific techniques discussed include contrast stretching, density slicing, and edge enhancement. The document also discusses visual saliency models, motion saliency, and using conditional random fields for video object extraction.
IntelliSuite is a complete design environment for MEMS that provides tools across the entire product development cycle. It includes schematic capture tool Synple, physical design tool Blueprint, process design tools CleanRoom, and multiphysics solvers FastField. IntelliSuite aims to link the entire MEMS organization through a unified platform. It offers a seamless flow from concept to tapeout through integrated tools for simulation, layout, verification, and more. IntelliSuite has established itself as the standard industry tool used by MEMS professionals worldwide.
IRJET- Exploring Image Super Resolution TechniquesIRJET Journal
This document discusses image super resolution techniques. It begins by defining super resolution as a technique that reconstructs a high resolution image from low resolution images. It then provides an overview of different super resolution methods including interpolation-based, reconstruction-based, and example-based (machine learning) techniques. The document evaluates state-of-the-art super resolution generative adversarial network (SRGAN) methods and their ability to generate realistic high resolution images from low resolution inputs. It also reviews the history and compares different super resolution techniques.
This document discusses compression of compound images using wavelet transform. It begins by introducing compound images, which contain different data types like text and graphics. Transmitting high resolution compound images over networks poses challenges due to large file sizes. The document then discusses using wavelet sub-band coding for lossless compression of compound images, which allows for excellent quality of text in compressed images. It provides details on image segmentation techniques like block-based segmentation that classify image blocks to compress according to image type.
An Algorithm for Improving the Quality of Compacted JPEG Image by Minimizes t...ijcga
The Block Transform Coded, JPEG- a lossy image compression format has been used to keep storage and
bandwidth requirements of digital image at practical levels. However, JPEG compression schemes may
exhibit unwanted image artifacts to appear - such as the ‘blocky’ artifact found in smooth/monotone areas
of an image, caused by the coarse quantization of DCT coefficients. A number of image filtering
approaches have been analyzed in literature incorporating value-averaging filters in order to smooth out
the discontinuities that appear across DCT block boundaries. Although some of these approaches are able
to decrease the severity of these unwanted artifacts to some extent, other approaches have certain
limitations that cause excessive blurring to high-contrast edges in the image. The image deblocking
algorithm presented in this paper aims to filter the blocked boundaries. This is accomplished by employing
smoothening, detection of blocked edges and then filtering the difference between the pixels containing the
blocked edge. The deblocking algorithm presented has been successful in reducing blocky artifacts in an
image and therefore increases the subjective as well as objective quality of the reconstructed image.
This document proposes a multi-level block truncation code algorithm for RGB image compression to achieve low bit rates and high quality. The algorithm combines bit mapping and quantization by dividing images into blocks, calculating thresholds, quantizing thresholds, and representing blocks with bit maps. It was tested on standard images like flowers, Lena, and baboon. Results showed improved peak signal-to-noise ratio and mean squared error compared to existing methods, demonstrating the effectiveness of the proposed multi-level block truncation code algorithm for image compression.
Remote HD and 3D image processing challenges in Embedded Systems
The Modern Applications has increased the complexity and demands of the video processing features and subsequent image data transfer.
The Image Processing mission will typically comprise three key elements: data capture, data processing, and data transmission. In addition, applications such as Recognition and data fusion have a need for time sensitivity, spatial awareness, and mutual awareness to correctly understand and utilize the data.
Low-latency processing and transmission are key performance metrics, particularly where there is a human operator and key decision maker situated in a location remote from the point of data gathering. An examination of key considerations – sensor processing location trends, video fusion, and video compression and bandwidth, in addition to Size, Weight, and Power
Comparative Study of Neural Networks Algorithms for Cloud Computing CPU Sched...IJECEIAES
Cloud Computing is the most powerful computing model of our time. While the major IT providers and consumers are competing to exploit the benefits of this computing model in order to thrive their profits, most of the cloud computing platforms are still built on operating systems that uses basic CPU (Core Processing Unit) scheduling algorithms that lacks the intelligence needed for such innovative computing model. Correspdondingly, this paper presents the benefits of applying Artificial Neural Networks algorithms in regards to enhancing CPU scheduling for Cloud Computing model. Furthermore, a set of characteristics and theoretical metrics are proposed for the sake of comparing the different Artificial Neural Networks algorithms and finding the most accurate algorithm for Cloud Computing CPU Scheduling.
Real-Time Implementation and Performance Optimization of Local Derivative Pat...IJECEIAES
Pattern based texture descriptors are widely used in Content Based Image Retrieval (CBIR) for efficient retrieval of matching images. Local Derivative Pattern (LDP), a higher order local pattern operator, originally proposed for face recognition, encodes the distinctive spatial relationships contained in a local region of an image as the feature vector. LDP efficiently extracts finer details and provides efficient retrieval however, it was proposed for images of limited resolution. Over the period of time the development in the digital image sensors had paid way for capturing images at a very high resolution. LDP algorithm though very efficient in content-based image retrieval did not scale well when capturing features from such high-resolution images as it becomes computationally very expensive. This paper proposes how to efficiently extract parallelism from the LDP algorithm and strategies for optimally implementing it by exploiting some inherent General-Purpose Graphics Processing Unit (GPGPU) characteristics. By optimally configuring the GPGPU kernels, image retrieval was performed at a much faster rate. The LDP algorithm was ported on to Compute Unified Device Architecture (CUDA) supported GPGPU and a maximum speed up of around 240x was achieved as compared to its sequential counterpart.
IRJET - Wavelet based Image Fusion using FPGA for Biomedical ApplicationIRJET Journal
This document describes a wavelet-based image fusion system implemented on an FPGA for biomedical applications. The system takes two input images, applies discrete wavelet transforms to both, then fuses the wavelet coefficients to create a single output image. It uses MATLAB and Xilinx System Generator to simulate the design in Simulink and implement it on a Virtex6 FPGA. The results show that wavelet-based fusion can combine the spatial and spectral information from multiple input images into a higher quality fused output image suitable for medical applications like fusing MRI and CT scans.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
This document provides an overview of a project that implemented image filtering using VHDL on an FPGA board. It discusses designing filters like average, Sobel, Gaussian, and Laplacian filters. Cache memory and a processing unit were developed to hold pixel values and apply filter kernels. Different methods for multiplication in the convolution process were evaluated. Results showed the output images after applying each filter both in software and on the FPGA board. In conclusion, FPGAs provide reconfigurable, accelerated processing for image applications like filtering compared to general purpose computers.
Image processing has become under the spotlight recently and leads to a
significant shift in various fields such as biomedical, satellite images, and
graphical applications. Nevertheless, the poor quality of an image is one of
the noticeable limitations of image processing as it restricts efficient data
extraction to be conducted. Conventionally, the image was processed via
software applications such as MATLAB. In spite of the software's ability to
cater to the data extraction of low-quality image issues, it still suffers from the
time-consuming issue. As the ability to obtain a rapid outcome is a favorable
feature of efficient image processing, the use of hardware in image processing
is deemed to keep the addressed issue at bay. Thus, the image enhancement
techniques using hardware have gradually rising interest among researchers
with numerous approaches such as field programmable gate array (FPGA). In
this study, 25 different research papers published from 2016 to 2021 are
studied and analyzed to focus on the performance of FPGA as hardware
implementation in image processing techniques.
A Smart Camera Processing Pipeline for Image Applications Utilizing Marching ...sipij
Image processing in machine vision is a challenging task because often real-time requirements have to be met in these systems. To accelerate the processing tasks in machine vision and to reduce data transfer latencies, new architectures for embedded systems in intelligent cameras are required. Furthermore, innovative processing approaches are necessary to realize these architectures efficiently. Marching Pixels are such a processing scheme, based on Organic Computing principles, and can be applied for example to determine object centroids in binary or gray-scale images. In this paper, we present a processing pipeline for smart camera systems utilizing such Marching Pixel algorithms. It consists of a buffering template for image pre-processing tasks in a FPGA to enhance captured images and an ASIC for the efficient realization of Marching Pixel approaches. The ASIC achieves a speedup of eight for the realization of Marching Pixel algorithms, compared to a common medium performance DSP platform.
HARDWARE SOFTWARE CO-SIMULATION FOR TRAFFIC LOAD COMPUTATION USING MATLAB SIM...ijcsity
Due to increase in number of vehicles, Traffic is a major problem faced in urban areas throughout the
world. This document presents a newly developed Matlab Simulink model to compute traffic load for real
time traffic signal control. Signal processing, video and image processing and Xilinx Blockset have been
extensively used for traffic load computation. The approach used is Edge detection operation, wherein,
Edges are extracted to identify the number of vehicles. The developed model computes the results with
greater degrees of accuracy and is capable of being used to set the green signal duration so as to release
the traffic dynamically on traffic junctions.
Xilinx System Generator (XSG) provides Simulink Blockset for several hardware operations that could be
implemented on various Xilinx Field programmable gate arrays (FPGAs). The method described in this
paper involves object feature identification and detection. Xilinx System Generator provides some blocks to
transform data provided from the software side of the simulation environment to the hardware side. In our
case it is MATLAB Simulink to System Generator blocks. This is an important concept to understand in the
design process using Xilinx System Generator. The Xilinx System Generator, embedded in MATLAB
Simulink is used to program the model and then test on the FPGA board using the properties of hardware
co-simulation tools.
Digital image enhancement by brightness and contrast manipulation using Veri...IJECEIAES
This document describes a proposed method for digitally enhancing images using brightness and contrast manipulation implemented in Verilog hardware description language. The method aims to improve low quality images impacted by low exposure and haze. It involves converting image files to hexadecimal, manipulating pixel brightness and contrast values using algorithms, and converting the output back to image format. The algorithms adjust brightness by adding a constant to pixel values and modify contrast by stretching the dynamic range of values. The method is evaluated on vehicle registration plate images and shows improvements over other enhancement methods based on quantitative and qualitative metrics.
Adaptive Neuro-Fuzzy Inference System (ANFIS) for segmentation of image ROI a...IRJET Journal
The document discusses a proposed system for concurrently performing image segmentation and image retrieval from segmented regions of interest (ROIs). It uses an Adaptive Neuro-Fuzzy Inference System (ANFIS) for segmenting ROIs from images and a probabilistic generative model for retrieving similar images based on keypoints detected within ROIs using the MP-KDD algorithm. The system is able to perform retrieval using features from multiple ROIs within a query image.
Efficient Image Compression Technique using Clustering and Random PermutationIJERA Editor
Multimedia data compression is a challenging situation for compression technique, due to the possibility of loss
of data as well as it require large amount of storage place. The minimization of storage place and proper
transmission of these data need compression. In this dissertation we proposed a block based DWT image
compression technique using genetic algorithm and HCC code matrix. The HCC code matrix compressed into
two different set redundant and non-redundant which generate similar pattern of block coefficient. The similar
block coefficient generated by particle of swarm optimization. The process of particle of swarm optimization is
select for the optimal block of DWT transform function. For the experimental purpose we used some standard
image such as Lena, Barbara and cameraman image. The size of resolution of this image is 256*256. The source
of image is Google
FACE COUNTING USING OPEN CV & PYTHON FOR ANALYZING UNUSUAL EVENTS IN CROWDSIRJET Journal
The document discusses face counting using OpenCV and Python by analyzing unusual events in crowds. It proposes using the Haar cascade algorithm for face detection and counting. Feature extraction is performed using gray-level co-occurrence matrix (GLCM) to extract texture and edge features. Discriminant analysis is then used to differentiate between samples accurately. The system aims to correctly detect and count faces in images using Python tools like OpenCV for digital image processing tasks and feature extraction algorithms like GLCM and discrete wavelet transform (DWT). It is intended to have good recognition accuracy compared to previous methods.
A SURVEY OF NEURAL NETWORK HARDWARE ACCELERATORS IN MACHINE LEARNING mlaij
The use of Machine Learning in Artificial Intelligence is the inspiration that shaped technology as it is today. Machine Learning has the power to greatly simplify our lives. Improvement in speech recognition and language understanding help the community interact more naturally with technology. The popularity of machine learning opens up the opportunities for optimizing the design of computing platforms using welldefined hardware accelerators. In the upcoming few years, cameras will be utilised as sensors for several applications. For ease of use and privacy restrictions, the requested image processing should be limited to a local embedded computer platform and with a high accuracy. Furthermore, less energy should be consumed. Dedicated acceleration of Convolutional Neural Networks can achieve these targets with high flexibility to perform multiple vision tasks. However, due to the exponential growth in technology constraints (especially in terms of energy) which could lead to heterogeneous multicores, and increasing number of defects, the strategy of defect-tolerant accelerators for heterogeneous multi-cores may become a main micro-architecture research issue. The up to date accelerators used still face some performance issues such as memory limitations, bandwidth, speed etc. This literature summarizes (in terms of a survey) recent work of accelerators including their advantages and disadvantages to make it easier for developers with neural network interests to further improve what has already been established.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
COMPOSITE IMAGELET IDENTIFIER FOR ML PROCESSORSIRJET Journal
The document proposes a composite imagelet identifier technique for machine learning processors that uses seam carving to manipulate edges and pixilation in images for processing. It discusses using existing algorithms like SSIM and Dijkstra's algorithm to calculate image energy and identify optimal seam locations for manipulation. The technique is evaluated using test images in MATLAB and is presented as having potential applications in areas like forestry, animal husbandry and safety monitoring.
This document summarizes a research paper that proposes a new approach called DiffP for more energy efficient ad hoc reprogramming of sensor networks. DiffP aims to mitigate the effects of program layout modifications and maximize similarity between old and new software. It also organizes global variables in a novel way to eliminate the effect of variable shifting. The document provides background on challenges with reprogramming deployed sensor networks due to limited energy, processing and memory resources. It reviews related work on dissemination protocols and reprogramming schemes, noting limitations such as producing large patches from layout changes or variable shifts. DiffP is presented as a potential improvement over existing approaches.
Study of Energy Efficient Images with Just Noticeable Difference Threshold Ba...ijtsrd
This document presents a novel method for producing energy-efficient images using a Feature Transform based Just Noticeable Difference Threshold (FTJNDT) model. The proposed method aims to reduce image energy consumption on displays like OLED by lowering pixel luminance below the just-noticeable difference threshold while maintaining perceptual quality. The FTJNDT model determines individual luminance thresholds for each image block based on visual saliency and non-linear modulation functions. An optimization framework is used to estimate modulation parameters and feature values using an objective image quality assessment. Experimental results showed the method reduced image energy consumption by an average of 4.31% compared to original images.
Novel hybrid framework for image compression for supportive hardware design o...IJECEIAES
Performing the image compression over the resource constrained hardware is quite a challenging task. Although, there has been various approaches being carried out towards image compression considering the hardware aspect of it, but still there are problems associated with the memory acceleration associated with the entire operation that downgrade the performance of the hardware device. Therefore, the proposed approach presents a cost effective image compression mechanism which offers lossless compression using a unique combination of the non-linear filtering, segmentation, contour detection, followed by the optimization. The compression mechanism adapts analytical approach for significant image compression. The execution of the compression mechanism yields faster response time, reduced mean square error, improved signal quality and significant compression ratio performance.
(Im2col)accelerating deep neural networks on low power heterogeneous architec...Bomm Kim
This document discusses accelerating deep neural networks on low power heterogeneous architectures. Specifically, it focuses on accelerating the inference time of the VGG-16 neural network on the ODROID-XU4 board, which contains an ARM CPU and Mali GPU. The authors develop parallel versions of VGG-16 using OpenMP for the CPU and OpenCL for the GPU. Several optimizations are explored in OpenCL, including work groups, vector data types, and the CLBlast library. The best OpenCL implementation achieves a 9.4x speedup over the original serial version.
This document discusses face detection on embedded systems. It begins by providing background on face detection applications and existing solutions. It then describes implementing a Viola-Jones face detection algorithm on a PC as a software prototype, achieving 80% accuracy. This implementation is then ported to an embedded system using a Nios II softcore processor. Profile analysis shows the bottleneck is searching locations. The document explores reducing the search space through downsampling images using bicubic interpolation, achieving a 4x speedup with no loss of accuracy on test images.
Region wise processing of an image using multithreading in multi core environIAEME Publication
This document presents a method for region-wise parallel processing of images using multithreading in a multi-core environment. The method divides large images into distinct regions of interest and assigns each region to a separate processing core. Each core then calculates statistical features for its assigned region in parallel. Experimental results on cell images show speedups of up to 600% when using 8 threads on an Intel Xeon processor compared to sequential processing on a single core. The document concludes that region-wise parallel processing provides significantly more efficient results than existing parallel image processing methods. This approach has applications in medical imaging where fast analysis of large images is important.
Region wise processing of an image using multithreading in multi core environIAEME Publication
This document discusses region-wise parallel processing of images using multithreading in a multi-core environment and its applications in medical imaging. It proposes dividing large images into regions of interest and assigning each region to a separate processor core for parallel processing. This approach could provide significantly faster results than existing parallel image processing methods. The document describes calculating statistical features like mean, standard deviation, and variance for each individual region. It presents experimental results showing speedups of around 200% for a core i3 processor and 600% for an Intel Xeon processor compared to sequential processing. The approach and its speed benefits are proposed to have applications in processing large medical images commonly used in areas like CT, PET, and MRI scans.
SPEED-UP IMPROVEMENT USING PARALLEL APPROACH IN IMAGE STEGANOGRAPHYcsandit
This paper presents a parallel approach to improve the time complexity problem associated
with sequential algorithms. An image steganography algorithm in transform domain is
considered for implementation. Image steganography is a technique to hide secret message in
an image. With the parallel implementation, large message can be hidden in large image since
it does not take much processing time. It is implemented on GPU systems. Parallel
programming is done using OpenCL in CUDA cores from NVIDIA. The speed-up improvement
obtained is very good with reasonably good output signal quality, when large amount of data is
processed
Design and Implementation of JPEG CODEC using NoCIRJET Journal
This document describes the design and implementation of a JPEG codec using a Network-on-Chip (NoC) structure. It aims to speed up the image transfer process and provide shorter processing times. The key steps are:
1. The JPEG encoding process includes color space conversion, downsampling, block division, discrete cosine transform, quantization, and entropy coding to compress the image.
2. A NoC is used to transmit the compressed image data packets across the chip to reduce latency during transfer.
3. The JPEG decoding process reverses the encoding steps through entropy decoding, dequantization, inverse discrete cosine transform, and image reconstruction to decompress the image for viewing.
Similar to An Investigation towards Effectiveness in Image Enhancement Process in MPSoC (20)
Redefining brain tumor segmentation: a cutting-edge convolutional neural netw...IJECEIAES
Medical image analysis has witnessed significant advancements with deep learning techniques. In the domain of brain tumor segmentation, the ability to
precisely delineate tumor boundaries from magnetic resonance imaging (MRI)
scans holds profound implications for diagnosis. This study presents an ensemble convolutional neural network (CNN) with transfer learning, integrating
the state-of-the-art Deeplabv3+ architecture with the ResNet18 backbone. The
model is rigorously trained and evaluated, exhibiting remarkable performance
metrics, including an impressive global accuracy of 99.286%, a high-class accuracy of 82.191%, a mean intersection over union (IoU) of 79.900%, a weighted
IoU of 98.620%, and a Boundary F1 (BF) score of 83.303%. Notably, a detailed comparative analysis with existing methods showcases the superiority of
our proposed model. These findings underscore the model’s competence in precise brain tumor localization, underscoring its potential to revolutionize medical
image analysis and enhance healthcare outcomes. This research paves the way
for future exploration and optimization of advanced CNN models in medical
imaging, emphasizing addressing false positives and resource efficiency.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
Neural network optimizer of proportional-integral-differential controller par...IJECEIAES
Wide application of proportional-integral-differential (PID)-regulator in industry requires constant improvement of methods of its parameters adjustment. The paper deals with the issues of optimization of PID-regulator parameters with the use of neural network technology methods. A methodology for choosing the architecture (structure) of neural network optimizer is proposed, which consists in determining the number of layers, the number of neurons in each layer, as well as the form and type of activation function. Algorithms of neural network training based on the application of the method of minimizing the mismatch between the regulated value and the target value are developed. The method of back propagation of gradients is proposed to select the optimal training rate of neurons of the neural network. The neural network optimizer, which is a superstructure of the linear PID controller, allows increasing the regulation accuracy from 0.23 to 0.09, thus reducing the power consumption from 65% to 53%. The results of the conducted experiments allow us to conclude that the created neural superstructure may well become a prototype of an automatic voltage regulator (AVR)-type industrial controller for tuning the parameters of the PID controller.
An improved modulation technique suitable for a three level flying capacitor ...IJECEIAES
This research paper introduces an innovative modulation technique for controlling a 3-level flying capacitor multilevel inverter (FCMLI), aiming to streamline the modulation process in contrast to conventional methods. The proposed
simplified modulation technique paves the way for more straightforward and
efficient control of multilevel inverters, enabling their widespread adoption and
integration into modern power electronic systems. Through the amalgamation of
sinusoidal pulse width modulation (SPWM) with a high-frequency square wave
pulse, this controlling technique attains energy equilibrium across the coupling
capacitor. The modulation scheme incorporates a simplified switching pattern
and a decreased count of voltage references, thereby simplifying the control
algorithm.
A review on features and methods of potential fishing zoneIJECEIAES
This review focuses on the importance of identifying potential fishing zones in seawater for sustainable fishing practices. It explores features like sea surface temperature (SST) and sea surface height (SSH), along with classification methods such as classifiers. The features like SST, SSH, and different classifiers used to classify the data, have been figured out in this review study. This study underscores the importance of examining potential fishing zones using advanced analytical techniques. It thoroughly explores the methodologies employed by researchers, covering both past and current approaches. The examination centers on data characteristics and the application of classification algorithms for classification of potential fishing zones. Furthermore, the prediction of potential fishing zones relies significantly on the effectiveness of classification algorithms. Previous research has assessed the performance of models like support vector machines, naïve Bayes, and artificial neural networks (ANN). In the previous result, the results of support vector machine (SVM) were 97.6% more accurate than naive Bayes's 94.2% to classify test data for fisheries classification. By considering the recent works in this area, several recommendations for future works are presented to further improve the performance of the potential fishing zone models, which is important to the fisheries community.
Electrical signal interference minimization using appropriate core material f...IJECEIAES
As demand for smaller, quicker, and more powerful devices rises, Moore's law is strictly followed. The industry has worked hard to make little devices that boost productivity. The goal is to optimize device density. Scientists are reducing connection delays to improve circuit performance. This helped them understand three-dimensional integrated circuit (3D IC) concepts, which stack active devices and create vertical connections to diminish latency and lower interconnects. Electrical involvement is a big worry with 3D integrates circuits. Researchers have developed and tested through silicon via (TSV) and substrates to decrease electrical wave involvement. This study illustrates a novel noise coupling reduction method using several electrical involvement models. A 22% drop in electrical involvement from wave-carrying to victim TSVs introduces this new paradigm and improves system performance even at higher THz frequencies.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
Bibliometric analysis highlighting the role of women in addressing climate ch...IJECEIAES
Fossil fuel consumption increased quickly, contributing to climate change
that is evident in unusual flooding and draughts, and global warming. Over
the past ten years, women's involvement in society has grown dramatically,
and they succeeded in playing a noticeable role in reducing climate change.
A bibliometric analysis of data from the last ten years has been carried out to
examine the role of women in addressing the climate change. The analysis's
findings discussed the relevant to the sustainable development goals (SDGs),
particularly SDG 7 and SDG 13. The results considered contributions made
by women in the various sectors while taking geographic dispersion into
account. The bibliometric analysis delves into topics including women's
leadership in environmental groups, their involvement in policymaking, their
contributions to sustainable development projects, and the influence of
gender diversity on attempts to mitigate climate change. This study's results
highlight how women have influenced policies and actions related to climate
change, point out areas of research deficiency and recommendations on how
to increase role of the women in addressing the climate change and
achieving sustainability. To achieve more successful results, this initiative
aims to highlight the significance of gender equality and encourage
inclusivity in climate change decision-making processes.
Voltage and frequency control of microgrid in presence of micro-turbine inter...IJECEIAES
The active and reactive load changes have a significant impact on voltage
and frequency. In this paper, in order to stabilize the microgrid (MG) against
load variations in islanding mode, the active and reactive power of all
distributed generators (DGs), including energy storage (battery), diesel
generator, and micro-turbine, are controlled. The micro-turbine generator is
connected to MG through a three-phase to three-phase matrix converter, and
the droop control method is applied for controlling the voltage and
frequency of MG. In addition, a method is introduced for voltage and
frequency control of micro-turbines in the transition state from gridconnected mode to islanding mode. A novel switching strategy of the matrix
converter is used for converting the high-frequency output voltage of the
micro-turbine to the grid-side frequency of the utility system. Moreover,
using the switching strategy, the low-order harmonics in the output current
and voltage are not produced, and consequently, the size of the output filter
would be reduced. In fact, the suggested control strategy is load-independent
and has no frequency conversion restrictions. The proposed approach for
voltage and frequency regulation demonstrates exceptional performance and
favorable response across various load alteration scenarios. The suggested
strategy is examined in several scenarios in the MG test systems, and the
simulation results are addressed.
Enhancing battery system identification: nonlinear autoregressive modeling fo...IJECEIAES
Precisely characterizing Li-ion batteries is essential for optimizing their
performance, enhancing safety, and prolonging their lifespan across various
applications, such as electric vehicles and renewable energy systems. This
article introduces an innovative nonlinear methodology for system
identification of a Li-ion battery, employing a nonlinear autoregressive with
exogenous inputs (NARX) model. The proposed approach integrates the
benefits of nonlinear modeling with the adaptability of the NARX structure,
facilitating a more comprehensive representation of the intricate
electrochemical processes within the battery. Experimental data collected
from a Li-ion battery operating under diverse scenarios are employed to
validate the effectiveness of the proposed methodology. The identified
NARX model exhibits superior accuracy in predicting the battery's behavior
compared to traditional linear models. This study underscores the
importance of accounting for nonlinearities in battery modeling, providing
insights into the intricate relationships between state-of-charge, voltage, and
current under dynamic conditions.
Smart grid deployment: from a bibliometric analysis to a surveyIJECEIAES
Smart grids are one of the last decades' innovations in electrical energy.
They bring relevant advantages compared to the traditional grid and
significant interest from the research community. Assessing the field's
evolution is essential to propose guidelines for facing new and future smart
grid challenges. In addition, knowing the main technologies involved in the
deployment of smart grids (SGs) is important to highlight possible
shortcomings that can be mitigated by developing new tools. This paper
contributes to the research trends mentioned above by focusing on two
objectives. First, a bibliometric analysis is presented to give an overview of
the current research level about smart grid deployment. Second, a survey of
the main technological approaches used for smart grid implementation and
their contributions are highlighted. To that effect, we searched the Web of
Science (WoS), and the Scopus databases. We obtained 5,663 documents
from WoS and 7,215 from Scopus on smart grid implementation or
deployment. With the extraction limitation in the Scopus database, 5,872 of
the 7,215 documents were extracted using a multi-step process. These two
datasets have been analyzed using a bibliometric tool called bibliometrix.
The main outputs are presented with some recommendations for future
research.
Use of analytical hierarchy process for selecting and prioritizing islanding ...IJECEIAES
One of the problems that are associated to power systems is islanding
condition, which must be rapidly and properly detected to prevent any
negative consequences on the system's protection, stability, and security.
This paper offers a thorough overview of several islanding detection
strategies, which are divided into two categories: classic approaches,
including local and remote approaches, and modern techniques, including
techniques based on signal processing and computational intelligence.
Additionally, each approach is compared and assessed based on several
factors, including implementation costs, non-detected zones, declining
power quality, and response times using the analytical hierarchy process
(AHP). The multi-criteria decision-making analysis shows that the overall
weight of passive methods (24.7%), active methods (7.8%), hybrid methods
(5.6%), remote methods (14.5%), signal processing-based methods (26.6%),
and computational intelligent-based methods (20.8%) based on the
comparison of all criteria together. Thus, it can be seen from the total weight
that hybrid approaches are the least suitable to be chosen, while signal
processing-based methods are the most appropriate islanding detection
method to be selected and implemented in power system with respect to the
aforementioned factors. Using Expert Choice software, the proposed
hierarchy model is studied and examined.
Enhancing of single-stage grid-connected photovoltaic system using fuzzy logi...IJECEIAES
The power generated by photovoltaic (PV) systems is influenced by
environmental factors. This variability hampers the control and utilization of
solar cells' peak output. In this study, a single-stage grid-connected PV
system is designed to enhance power quality. Our approach employs fuzzy
logic in the direct power control (DPC) of a three-phase voltage source
inverter (VSI), enabling seamless integration of the PV connected to the
grid. Additionally, a fuzzy logic-based maximum power point tracking
(MPPT) controller is adopted, which outperforms traditional methods like
incremental conductance (INC) in enhancing solar cell efficiency and
minimizing the response time. Moreover, the inverter's real-time active and
reactive power is directly managed to achieve a unity power factor (UPF).
The system's performance is assessed through MATLAB/Simulink
implementation, showing marked improvement over conventional methods,
particularly in steady-state and varying weather conditions. For solar
irradiances of 500 and 1,000 W/m2
, the results show that the proposed
method reduces the total harmonic distortion (THD) of the injected current
to the grid by approximately 46% and 38% compared to conventional
methods, respectively. Furthermore, we compare the simulation results with
IEEE standards to evaluate the system's grid compatibility.
Enhancing photovoltaic system maximum power point tracking with fuzzy logic-b...IJECEIAES
Photovoltaic systems have emerged as a promising energy resource that
caters to the future needs of society, owing to their renewable, inexhaustible,
and cost-free nature. The power output of these systems relies on solar cell
radiation and temperature. In order to mitigate the dependence on
atmospheric conditions and enhance power tracking, a conventional
approach has been improved by integrating various methods. To optimize
the generation of electricity from solar systems, the maximum power point
tracking (MPPT) technique is employed. To overcome limitations such as
steady-state voltage oscillations and improve transient response, two
traditional MPPT methods, namely fuzzy logic controller (FLC) and perturb
and observe (P&O), have been modified. This research paper aims to
simulate and validate the step size of the proposed modified P&O and FLC
techniques within the MPPT algorithm using MATLAB/Simulink for
efficient power tracking in photovoltaic systems.
Adaptive synchronous sliding control for a robot manipulator based on neural ...IJECEIAES
Robot manipulators have become important equipment in production lines, medical fields, and transportation. Improving the quality of trajectory tracking for
robot hands is always an attractive topic in the research community. This is a
challenging problem because robot manipulators are complex nonlinear systems
and are often subject to fluctuations in loads and external disturbances. This
article proposes an adaptive synchronous sliding control scheme to improve trajectory tracking performance for a robot manipulator. The proposed controller
ensures that the positions of the joints track the desired trajectory, synchronize
the errors, and significantly reduces chattering. First, the synchronous tracking
errors and synchronous sliding surfaces are presented. Second, the synchronous
tracking error dynamics are determined. Third, a robust adaptive control law is
designed,the unknown components of the model are estimated online by the neural network, and the parameters of the switching elements are selected by fuzzy
logic. The built algorithm ensures that the tracking and approximation errors
are ultimately uniformly bounded (UUB). Finally, the effectiveness of the constructed algorithm is demonstrated through simulation and experimental results.
Simulation and experimental results show that the proposed controller is effective with small synchronous tracking errors, and the chattering phenomenon is
significantly reduced.
Remote field-programmable gate array laboratory for signal acquisition and de...IJECEIAES
A remote laboratory utilizing field-programmable gate array (FPGA) technologies enhances students’ learning experience anywhere and anytime in embedded system design. Existing remote laboratories prioritize hardware access and visual feedback for observing board behavior after programming, neglecting comprehensive debugging tools to resolve errors that require internal signal acquisition. This paper proposes a novel remote embeddedsystem design approach targeting FPGA technologies that are fully interactive via a web-based platform. Our solution provides FPGA board access and debugging capabilities beyond the visual feedback provided by existing remote laboratories. We implemented a lab module that allows users to seamlessly incorporate into their FPGA design. The module minimizes hardware resource utilization while enabling the acquisition of a large number of data samples from the signal during the experiments by adaptively compressing the signal prior to data transmission. The results demonstrate an average compression ratio of 2.90 across three benchmark signals, indicating efficient signal acquisition and effective debugging and analysis. This method allows users to acquire more data samples than conventional methods. The proposed lab allows students to remotely test and debug their designs, bridging the gap between theory and practice in embedded system design.
Detecting and resolving feature envy through automated machine learning and m...IJECEIAES
Efficiently identifying and resolving code smells enhances software project quality. This paper presents a novel solution, utilizing automated machine learning (AutoML) techniques, to detect code smells and apply move method refactoring. By evaluating code metrics before and after refactoring, we assessed its impact on coupling, complexity, and cohesion. Key contributions of this research include a unique dataset for code smell classification and the development of models using AutoGluon for optimal performance. Furthermore, the study identifies the top 20 influential features in classifying feature envy, a well-known code smell, stemming from excessive reliance on external classes. We also explored how move method refactoring addresses feature envy, revealing reduced coupling and complexity, and improved cohesion, ultimately enhancing code quality. In summary, this research offers an empirical, data-driven approach, integrating AutoML and move method refactoring to optimize software project quality. Insights gained shed light on the benefits of refactoring on code quality and the significance of specific features in detecting feature envy. Future research can expand to explore additional refactoring techniques and a broader range of code metrics, advancing software engineering practices and standards.
Smart monitoring technique for solar cell systems using internet of things ba...IJECEIAES
Rapidly and remotely monitoring and receiving the solar cell systems status parameters, solar irradiance, temperature, and humidity, are critical issues in enhancement their efficiency. Hence, in the present article an improved smart prototype of internet of things (IoT) technique based on embedded system through NodeMCU ESP8266 (ESP-12E) was carried out experimentally. Three different regions at Egypt; Luxor, Cairo, and El-Beheira cities were chosen to study their solar irradiance profile, temperature, and humidity by the proposed IoT system. The monitoring data of solar irradiance, temperature, and humidity were live visualized directly by Ubidots through hypertext transfer protocol (HTTP) protocol. The measured solar power radiation in Luxor, Cairo, and El-Beheira ranged between 216-1000, 245-958, and 187-692 W/m 2 respectively during the solar day. The accuracy and rapidity of obtaining monitoring results using the proposed IoT system made it a strong candidate for application in monitoring solar cell systems. On the other hand, the obtained solar power radiation results of the three considered regions strongly candidate Luxor and Cairo as suitable places to build up a solar cells system station rather than El-Beheira.
An efficient security framework for intrusion detection and prevention in int...IJECEIAES
Over the past few years, the internet of things (IoT) has advanced to connect billions of smart devices to improve quality of life. However, anomalies or malicious intrusions pose several security loopholes, leading to performance degradation and threat to data security in IoT operations. Thereby, IoT security systems must keep an eye on and restrict unwanted events from occurring in the IoT network. Recently, various technical solutions based on machine learning (ML) models have been derived towards identifying and restricting unwanted events in IoT. However, most ML-based approaches are prone to miss-classification due to inappropriate feature selection. Additionally, most ML approaches applied to intrusion detection and prevention consider supervised learning, which requires a large amount of labeled data to be trained. Consequently, such complex datasets are impossible to source in a large network like IoT. To address this problem, this proposed study introduces an efficient learning mechanism to strengthen the IoT security aspects. The proposed algorithm incorporates supervised and unsupervised approaches to improve the learning models for intrusion detection and mitigation. Compared with the related works, the experimental outcome shows that the model performs well in a benchmark dataset. It accomplishes an improved detection accuracy of approximately 99.21%.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
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represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
ACEP Magazine edition 4th launched on 05.06.2024Rahul
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CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
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politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
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pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
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Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
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Chip (NOC) to ensure high efficiency and scalability. The system design of low-cost NoC- based MPSoC
and its applications are implemented using an algorithm to enhance a video based on Super-Resolution (SR)
[4]. A technique to synthesize a heterogeneous architecture, having many processors, to speed up a particular
application is dealt with the presented heterogeneous system synthesis to accomplish a design flow
commercially built on the platform of XtensaTM from Tensilica Inc. This is the first tool integrating
extensible processors for the synthesis of customized MPSoC [5]. Design space exploration is a method
required to assess the different design alternatives for utilizing the immense hardware resources available in
MPSoC efficiently. A solution is developed for the faster result simulation and calculation of the
performance characteristic of MPSoC which reduces the time, and within the procedure of Transaction-level
modeling, a unique way of defining the Programmer's View level is introduced by two complementary
modeling sub levels [6]. The technique of adopting a framework based on high-level power calculation of
MPSoC architectures working upon FPGA is called as event signatures, and it operates on the principle of
abstract execution profiles. To perform a quick validation of the high-level power models when compared to
the of the MPSoC implementations on FPGA, Daedalus is an entirely integrated tool-flow in which system-
level synthesis and FPGA prototyping are carried out [7]. A high-performance FPGA implementation of an
operator is introduced. It is performed by mapping technique of polynomials which are pixel value adaptable.
The Drago operator is suitable for the operation of high-frame-rate and the proposed resource-efficient FPGA
execution [8]. Section 1.1 discusses the background of the existing work reviewed followed by foregrounding
the research problems identified in Section 1.2 and proposed solution in 1.3 Section 2 deals with current
research methodologies most often adopted which have been presented to increase the output efficiency of
the image enhancement system. Section 3 discusses the research gap. Existing research trends highlighting
the models proposed are mentioned in section 3.1. Section 4 highlights the future scope of the evolving
trends in image processing. Finally, Section 6 has the conclusion briefed on it.
1.1. Background
This section discusses the background of image enhancement. The surveillance systems using
Electro-Optical (EO) have the capability of searching, detecting, tracking and monitoring the potential target
designation. Since an issue is posed due to the difficulty in target detecting and detection of it, the proposed
solution would reduce the clutter from the background and atmospheric degradation [9]. The enhancement of
bio-medical images that detect the presence of liver cancer that happens to be world’s sixth most common
tumor, malignant is carried out by comparing the value of PSNR, MSE, algorithms based on contrast
stretching, image histogram, shock filter and contrast limited adaptive histogram equalization [10].
1.2. Research Problem
Due to the growth and demand of cost, efficient image system operating with a minimal amount of
power like video cam recorder, PC camera, and digital camera algorithm implied by it is a necessity.
Algorithms applied for enhancement are critical regarding constraints and hence to maintain the image
appeared in signal processing, these methodologies are utilized. Serial processors being deployed in the
treatment of real-time multimedia image manipulation is problematic with the size of a picture having a
higher resolution. To make the image processing system work efficiently providing the high-performance
parameter in a short span of time is a demanding task. Implying the algorithms for image processing by
hardware architecture is inconvenient in real time situation. Factors namely chip area, computational speed
constraints; design maintained at low power should be adequately optimized. The design modeling should be
carried out by hardware-based languages VHDL, Verilog or Xilinx system generator supporting Digital
Signal Processing (DSP).
1.3. Proposed Solution
An electronic generated digital image can be improved regarding its superiority by enhancing it.
Numerous mechanisms have been presented in the field of image enhancement with Field Programmable
Gate Array (FPGA). Incorporation of Advanced Microcontroller Bus Architecture (AMBA)/Advanced high-
performance bus (AHP) /Advanced Peripheral Bus (APB) /Advanced Extensible Bus (AXI) in the
mechanism would provide a better interface for communication between the memory and medical image
given as an input for enhancement reducing the effect of heterogeneity of MPSoC.
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2. EXISTING RESEARCH TECHNIQUES
This section describes a brief overview of the existent methods that have been conducted to address
the issues in image enhancement technologies. CMOS image sensor can be incorporated to provide lower
power consuming enhanced images at a lesser cost but are majorly affected by the disadvantage of the low-
quality factor [11].Image edges are the most attribute that gives the useful data for image interpretability. The
operation of detecting the image edges is the work of Sobel operator. Software does not operate to meet the
particular requirement of the real-time application as it posse's property of being less sensitive towards noise
and results in lesser accuracy extent for complex edges [12]. Processing a data stream which has different
image size bits is inconvenient. A single serial processor makes it incredibly difficult to handle several
operations on a picture pixel for enhancing it [13]. Mapping of an image enhancement technique from
software to hardware requirement is a demanding task.
The study of Alareqi et al. [14] focused on the use of spatial domain in FPGA and implemented the
digital enhancement technique for real-time hardware in biomedical applications. Regular methods of image
enhancement cannot satisfy the requirement in real-time. The technology was incorporated into hand image
with veins utilizing Open Access Biomedical Image Search Engine. By the use of the DSP tool, an efficient
architecture is built by involving the system generator blocks from it. Performance parameters are evaluated
on FPGA Virtex (XUPV5- LX110T).The various techniques applied to a medical image showed that
brightness control provided the best result and hence it was helpful in determining the data for the vein
pattern. In the study of Salcic and SIvaswamy [15] suggested a way to attain a better speed of computation
for the contrast of an image via low-cost FPGA that focuses on X-ray images. Filtering followed by
histogram modification is the main principle of operation here. Global Histogram Equalization (GHE) was
the idea behind the change of histogram whereas that for the functioning of a filter is High Boost Filter
(HBF). A coprocessor was made to work on FPGA prototype ISA-bus board is the image coprocessor for
enhancement, IMECO that enabled high-efficiency implementation of improvement methodologies and
acquired high-performance, low-cost solutions provided by hardware/software co-design. Operations such as
downloading and uploading an image with the configuration process of equipment. Practical enhancement of
images is possible verifying the low-cost of a RAPROS prototype board. The study of Arici et al. [16]
discussed a general frame work based on the equalization of a histogram for image enhancing purpose. The
challenge of optimization that decreases the effect of the cost was given a solution by constructing a
framework here. It is based on Histogram Equalization (HE) that resulted in contrast enhancement
excessively which created visual artifacts and produced a processed image with an unnatural look. An
algorithm was developed for serving contrast enhancement property that avoided the memory-bandwidth
consuming operation and cumbersome calculations.
The study of Ma et al. [17] presented the design of an Intellectual Property of the APB Bridge that
converted the translation input of AXI4.0- lite into APB 4.0 transactions input levels. The originally
developed standard SoC bus was an initiative made by ARM named as AMBA 4.0.As a result, the
characteristics of AXI4-Lite to APB bridge attained 32-bit AXI and APB interfaces, slave, and master
respectively along with the support of sixteen APB peripherals and response of AXI read/write providing a
result of error transfer results. The study of Paunikar et al. [18] discussed the design of an APB employing
Universal Asynchronous Reception Transmission (UART) as its slave. To ensure data security, Linear
Feedback Shift Register (LFSR) module was involved. Consumption of power with this design adoption was
saved up to 6% and 10% of area optimization for the one interfaced with AMBA2 APM. The study of Zhiwei
et al. [19] proposed a CMOS image sensor architecture, which used APB bus to incorporate image
processing. The issue of color image processing and deals with the changes in the conventional and proposed
architecture employed in the pipeline of digital still cameras. The study involves two efficient auto white
balance techniques together which is a system on the chip. The image quality of raw data can immensely be
improved as FPGA is applied. Results prove that VLSI architecture can be performed on an identical chip.
The study of Li et al. [20] emphasized on the sequence of video for eliminating the unnecessary vibrations in
it. A feature-based technique to stabilize the video in its full frame and an entirely FPGA based architectural
system design pipelined feature was enabled. The presented methodology had the process of initial extraction
from feature points with an algorithm named oriented fast and rotated brief, and later similarity check was
done for frames which are consecutive. Further, the pairs of the points are operated with affine
transformation with the help of random sample consensus-based estimation to determine the robust inter-
frame movement. The evaluated results were integrated to find the parameters of cumulative motion among
reference and present frames, smoothening the translational components via a Kalman filter. Image
mosaicking technique was implied in constructing the mosaicked image, and respectively the display window
was developed. Experimental observations indicated that presented system could deal with PAL input video
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standard involving translation of arbitrating and enhanced viewing experience is seen at 22.37 milliseconds
per frame, attaining real-time performance in processing. The study of Long et al. [21] presented an
algorithm for edge enhancement in an image along with an algorithm implied in the reduction of noise
functioning at 5*5 block on Y channel. The structure of parallel and pipelining was used for processing a
single pixel which resulted in image reduction. The system design was created and validated at a frequency
of 90MHz in Xilinx Virtex2 FPGA. Observations showed that a frame rate of 290 frames per second for
VGA images was obtained. This technique efficiently minimized the effect of two kinds of noise in the
system. The study of Yen et al. [22] dealt with the histogram equalization modified technique to enhance the
property of contrast in the monochrome frame of an image. A lookup was created by the image which was
alternatively sampled and quantized and later the table was applied to acquire the enhanced image. When
comparing the original scheme, the differences found were minute to a viewer's eye. In cases of real-time
processing, the adopted method of sampling and quantization was more appropriate for a hardware pipelining
design. The technique was found suitable for surveillance systems also when the size of the frame was larger
in comparison to the HDTV.
Author Smriti et al. [23] performed the comparative analysis of different image enhancement
mechanisms by considering ultrasound liver image and suggested that shock filter can offer significant
performance than other mechanisms.The pre-processing mechanism for enhancement of wireless capsule
endoscopy image was illustrated in Shahril et al. [24], and it achieves improvement of 20.3% in PSNR and
31.5% in gradient value of the image. Ali et al. [25] used the Gaussian estimation parameter to remove the
noise (i.e., salt & pepper) from the image and found quality enhancement in the image.
In the study of Chiuchisan [26], an implementation methodology to improvise the configurable
system for image enhancement incorporating VHDL and architecture which is reconfigurable was initiated.
For a medical specialist to have an enhanced version of images, a new set of filters were created at the
hardware level. From Xilinx, ISIM simulator and the ISE design program component was implied for
simulation and verification of the Verilog based system complex algorithms that could be rapidly prototyped
with the employment of Verilog Hardware Description Language (HDL) with FPGA implementation. It
shows that an additional processor was not mandatory to dedicate processing of an image.
The algorithms implied in the image enhancement for MPSoC on reconfigurable FPGA hardware
are:
a. Brightness Control Algorithm: The image captured by a digital camera will generate an image
having low brightness and the objects from it would not become visible prominently. By
adding/subtracting the constant value to gray level of each pixel individually, this technique is
effectively implied in increasing the brightness of an image or vice-versa.
b. Contrast Stretching: The intensity range value is expanded to improvise the quality by evolving
the possible existing values. Low-light conditions are affected as a result of low image contrast
value. The stretching is used for linear mapping for input to output values of the image.
c. Image Histogram: This algorithm is used to enhance the image contrast. The equalization would
stretch the uniformly distributed histogram from gray levels at darker ends. It works on two
principles namely, probability mass function and cumulative distribution function.
d. Edge Detection techniques: these are incorporated in the processing an image and vision of a
computer to enable detection of the edges using operators namely Sobel and Prewitt. They
calculate the approximate image function gradient.
a. Sobel operator: the principle of operation here is convolution performed on the image with filter
values in vertical and horizontal directions through the pixels which are original
b. Prewitt operator and other techniques: mostly used for higher frequency changes in the image
produced by gradient approximation, performs the same function as that of the Sobel operator.
e. Mean Filtering: This filtering technique replaces the centre pixel value from the window along
the mean value possessed by all the pixels present in the window. Allows the reduction of the
noise in the images and is held responsible for decreasing the variation in the intensity from one
pixel to the next pixel that smoothens the fed image. In evaluating the mean, shape, and size of
the neighbourhood, the convolutional kernel is initiated.
f. Image Thresholding: It is categorized as an image segmentation technique, which allows the
creation of binary images in gray level. If the input given is lesser than the threshold value, the
image pixel is replaced with the white pixel else black pixel.
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Table 1 shows the summary of Existing Approaches.
Table 1. Summary of Existing Approaches
Authors Problems Technique Outcome Performance
Parameters
Sree and Rao [1] Enhancement of
Retinal Fundus
Image
FPGA based
algorithm
implementation
Comparison of hardware
system with the software
version for complex video
inputs
Slice flip-flops,
LUTs and block
memory has reduced
utilization of 1%,
1%, and 6%
respectively.
Wolf et al. [2] CAD problems in
MPSoC
Survey paper MPSoC is found as a
distinct category of
computer architecture
Improvised
computational speed
Liao et al. [3] Real-time
processing of
images
Application-Specific
Instruction-set
Processor(ASIP)
FullHD(1920x1080)
application is achieved
Technology,
normalized area,
area, cache size,
frequency
Singla et al. [4] Interconnection in
MPSoC
Network on Chip Characterization of
performance
SR Execution time,
Number of
processing elements
and type of
application
Sun et al. [5] Heterogeneity in
MPSoC
Algorithm based on
expected execution
time
First tool for synthesis of
custom MPSoC
Custom area
instruction
Atiallah et al. [6] Resource
utilization of
MPSoC
Timed programmers
view
Speedup factor is 18 Simulation Speedups,
Number of
processors, time of
execution and
number of
contentions
Piscitelli et al. [7] Complexity of
MPSoC
Event signatures Fairly accurate power
estimates are obtained
Power consumption
Popovic et al.[8] Execution of
FPGA
Drago operator Resource efficient FPGA
execution
SSIM, PSNR
Singh et al.[9] Long range
detection of the
target
EO Surveillance
systems
High system speed
performance observed
Utilization of sliced
flip-flops, occupied
slices, slices
containing only one
logic and DSP48s is
11%, 24%,100% and
1% respectively.
Sahu et al.[10] Detection of Liver
Cancer
Shock filter,
CLAHE, Contrast
stretching and Image
histogram
Improvised version of the
visual perception is
observed
MSE and PSNR
value
Jung et al. [11] Requirement of
real-time image
enhancement
CMOS image sensor Low-cost, one chip PC
camera having higher
performance was estimated
Logic gates
optimization
Gou et al. [12] Real-time parallel
processing of
videos
Sobel edge detection
algorithm
Edge of gray image is
located
Utilization of slices,
flip-flops, LUTs,
IOBs, BRAMs, GClk
is 11%, 7%, 9%,
10%,16% , 12%
respectively
Al Ali et al. [13] Real-time
processing of
image using serial
processors
Windowing operator Image of any size can be
traversed for its pixels
Device usage, time
delay, frequency of
clock and total power
Alareqi et al. [14] Real-time image
processing for
biomedical
applications
Inverting image
operation, brightness
control,
segmentation,
contrast stretching
Vein image detected is
clear
MSE,MD,NAE,NCC,
SC,PSNR, AD
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Authors Problems Technique Outcome Performance
Parameters
Salcic and Swamy,
[15]
Computational
speed of image
contrast
IMECO Target applications have
real-time image
enhancement
Speed of computation
Arici et al. [16] Optimization
reducing cost
function
Histogram
equalization
Contrast enhancement is
presented
Enhancement
measure, absolute
mean brightness
error, discrete
entropy
Ma et al. [17] Communication in
bus
Intellectual property
design
High-performance AXI bus
is attained with APB
domain
Read/ write
operations, peripheral
support
Paunikar et al.
[18]
Interfacing
challenges in APB
UART with LFSR APB saves 6% power and
10% area
Power and area
optimization
with/without LFSR
Zhiwei et al. [19] Color image
processing
CMOS image
+sensor APB bus
Possible to implement
VLSI architecture on a
single chip
Efficiency of
transmission, process
timing, minimized
power consumption
Li et al.[20] Vibrations in video
sequences
Oriented fast and
rotate brief algorithm
Viewing experience of
22.37 millisecond per
frame was obtained
PSNR, Usage of
device components
Long et al.[21] Edge enhancement
of an image
Noise reduction
algorithm on Y-
channel is proposed
Two kinds of noises are
effectively reduced
Usage of multipliers,
SRAM and LUT.
Yen et al.[22] Contrast
enhancement
Sample and
quantized image
Frame size larger than
HDTV can be
accommodated
Standard deviation,
efficiency of area
performance, cost of
hardware, throughput
Chiuchisan [23] Configurability of
real-time
processing system
Employing new
series of filters
Rapid prototyping of
complex algorithms is
possible
Brightness
adjustment, contrast
enhancement,
sharpening operation
3. RESEARCH GAP
The following are the categories to be focused on the research gap in image enhancement:
a. Artefacts: For enhancement of bio-medical images, it is essential to remove artifacts like hair, air
bubbles affecting the segmentation accuracy. This gives the need to develop the special aid to
control the illuminated artifact.
b. Pixel lost: In the process of converting the original bio-medical image to the transformed form,
the pixel values may tend to get altered or even get lost and hence to avoid this, a
countermeasure should be adapted to retain the useful data in the pixels.
c. Illuminate misbalancing: The illuminance property of the image might face imbalance as there
are predefined rules for the image transformation and the region of interest may not be
particularly concentrated.
d. Edge degradation: Degraded edges can lead to variation in the enhancement of the image than
the expected output, and since it has a crucial role in the process, it should be maintained at its
initial value.
3.1. Research Trends
The existing research works towards enhancing an image in the field of spatial domain involving the
techniques of histogram equalization, intensity transformation, and spatial filtering are found to have
71 journals, 180 conference publication and one early access article published. Systems implying frequency
domain method for image enhancement include filtering process of low pass, high pass, linear; root and
homomorphic methods had 216 conference publication, 83 journals and magazines, one early access article
and one book and eBook published.
Figure 1 shows the existing Research Trends.
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ImageEnhancementTechniques
Frequency Domain
– low pass, high
pass, linear , root
and homomorphic
filtering technique
216 Conference
83 Journals and
Magazines
Spatial Domain –
spatial filtering,
intensity
transformation ,
histogram
equalization
180 Conference
71 Journals and
Magazines
Figure 1. Existing Research Trends
4. CONCLUSION AND FUTURE WORK
Image enhancement can be applied in different domains, designed using multiple approaches to
obtain images as per the requirement of the user. This paper presents the number of ways in which the
attributes of an image can be enhanced with the FPGA hardware and MPSoC computing. Implementing an
interfacing module consisting of AMBA AHB/APB/AXI, combination of advanced microcontroller bus
architecture would control the operation of creating a communication channel in between the memory and
algorithms developed in the system. Advanced high-performance bus initiates the performance; advanced
peripheral bus provides the input-output peripheral device function. It supports 256 beats of length regarding
burst, need of updated write and read operations and data on component operability. It has sixteen masters
and sixteen slaves interfacing ability. Introducing hybrid algorithms in the future will be successfully able to
overcome the drawbacks observed in the image processing technique. Capacity to boost the factor of contrast
by using the edge filter hypothesis would immensely bring a change in the digital image fields.
In this paper, we have come across the problems of heterogeneity in MPSoC on FPGA that makes it
crucial in designing a model that assures the overall high throughput and will act in increasing the behavior of
an image. Unifying the image enhancement algorithms namely brightness control, contrast stretching,
negative image transformation, gamma correction or power-law transformation, image histogram, mean
filter, Median Filtering, histogram equalization, Sobel operator, Prewitt operator and image thresholding will
initiate a method to rectify the drawbacks in the previous research works introduced in the approval of image
enhancement. AMBA AXI-4 can behave as a bus giving suitable solution for the interfacing non-
convenience between the inputs from the user to the output gained after processing.
REFERENCES
[1] Sree, V. Krishna, and P. Sudhakar Rao. "Hardware implementation of enhancement of retinal fundus image using
Simulink." Microelectronics and Electronics (PrimeAsia), 2013 IEEE Asia Pacific Conference on Postgraduate
Research in. IEEE, 2013.
[1] Wolf, Wayne, Ahmed Amine Jerraya, and Grant Martin. "Multiprocessor system-on-chip (MPSoC) technology."
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27.10 (2008): 1701-1713.
[2] Liao, Hsuanchun, et al. "A reconfigurable high-performance as an engine for image signal processing." Parallel and
Distributed Processing Symposium Workshops & Ph.D. Forum (IPDPSW), 2012 IEEE 26th International. IEEE,
2012.
[3] Singla, Garbi, Felix Tobajas, and Valentin de Armas. "Video super-resolution algorithm implemented on a low-cost
not-based music platform." Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on.
IEEE, 2013.
[4] Sun, Fei, et al. "Synthesis of application-specific heterogeneous multiprocessor architectures using extensible
processors." VLSI Design, 2005. 18th International Conference on. IEEE, 2005.
[5] Atitallah, Rabie Ben, et al. "An MPSoC performance estimation framework using transaction-level modeling."
Embedded and Real-Time Computing Systems and Applications, 2007. RTCSA 2007. 13th IEEE International
Conference on. IEEE, 2007.
[6] Piscitelli, Roberta, and Andy D. Pimentel. "A high-level power model for music on FPGA." Parallel and Distributed
Processing Workshops and Ph.D. Forum (IPDPSW), 2011 IEEE International Symposium on. IEEE, 2011.
[7] Popovic, Vladan, ElievaPignat, and Yusuf Leblebici. "Performance optimization and FPGA implementation of real-
time tone mapping." IEEE Transactions on Circuits and Systems II: Express Briefs 61.10 (2014): 803-807.
[8] Singh, Manvendra, et al. "FPGA based implementation of real-time image enhancement algorithms for Electro-
Optical surveillance systems." Electrical Engineering/Electronics, Computer, Telecommunications and Information
Technology (ECTI-CON), 2015 12th International Conference on. IEEE, 2015.
8. ISSN: 2088-8708
Int J Elec & Comp Eng, Vol. 8, No. 2, April 2018 : 963 – 970
970
[9] Sahu, Smriti. "Comparative analysis of image enhancement techniques for ultrasound liver image." International
Journal of Electrical and Computer Engineering 2.6 (2012): 792.
[10] Jung, Yun Ho, et al. "Design of real-time image enhancement preprocessor for CMOS image sensor." IEEE
Transactions on Consumer Electronics 46.1 (2000): 68-75.
[11] Guo, Zhengyang, Wenbo Xu, and Zhilei Chai. "Image edge detection based on FPGA." Distributed Computing and
Applications to Business Engineering and Science (DCABES), 2010 Ninth International Symposium on. IEEE,
2010.
[12] AlAli, Mohammad I., Khaldoon M. Mhaidat, and Inad A. Aljarrah. "Implementing image processing algorithms in
FPGA hardware." Applied Electrical Engineering and Computing Technologies (AEECT), 2013 IEEE Jordan
Conference on. IEEE, 2013.
[13] Alareqi, Mohammed, et al. "Design and FPGA implementation of Real-Time Hardware Co-Simulation for image
enhancement in biomedical applications." Wireless Technologies, Embedded, and Intelligent Systems (WITS), 2017
International Conference on. IEEE, 2017.
[14] Salcic, Z., and JayanthiSivaswamy. "IMECO: a reconfigurable FPGA-based image enhancement coprocessor
framework." TENCON'97. IEEE Region 10 Annual Conference. Speech and Image Technologies for Computing and
Telecommunications, Proceedings of IEEE. Vol. 1. IEEE, 1997.
[15] Arici, Tarik, SalihDikbas, and YucelAltunbasak. "A histogram modification framework and its application for image
contrast enhancement." IEEE Transactions on image processing 18.9 (2009): 1921-1935.
[16] Ma, Chenghai, Zhijun Liu, and Xiaoyue Ma. "Design and implementation of APB bridge based on AMBA 4.0."
Consumer Electronics, Communications and Networks (CECNet), 2011 International Conference on. IEEE, 2011.
[17] Paunikar, Abhijeet, et al. "Design and implementation of the area efficient, low power AMBA-APB Bridge for SoC."
Green Computing Communication and Electrical Engineering (ICGCCEE), 2014 International Conference on. IEEE,
2014.
[18] Zhiwei, Ge, Yao Suying, and Xu Jiangtao. "Design of on-chip image processing based on APB bus with CMOS
image sensor." ASIC, 2009. ASICON'09. IEEE 8th International Conference on. IEEE, 2009.
[19] Li, Jianan, Tingfa Xu, and Kun Zhang. "Real-time feature-based video stabilization on FPGA." IEEE Transactions
on Circuits and Systems for Video Technology 27.4 (2017): 907-919.
[20] Long, Jinkai, Xiaoxin Cui, and Dunshan Yu. "An adaptive edge enhancement algorithm and hardware
implementation." Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of.
IEEE, 2010.
[21] Yen, Jui-Cheng, et al. "Modified Contrast Enhancement Algorithm and Its Hardware Design for Real-Time
Applications." Computer, Consumer, and Control (IS3C), 2014 International Symposium on. IEEE, 2014.
[22] Smriti Sahu, Maheedhar Dubey, Mohammad Imroze Khan, "Comparative Analysis of Image Enhancement
Techniques for Ultrasound Liver Image," International Journal of Electrical and Computer Engineering (IJECE),
Vol.2, No.6, pp. 792~797, December 2012.
[23] Rosdiana Shahril, Sabariah Baharun, AKM Muzahidul Islam, "Pre-processing Technique for Wireless Capsule
Endoscopy Image Enhancement," International Journal of Electrical and Computer Engineering (IJECE), Vol. 6, No.
4, pp. 1617~1626, August 2016.
[24] Suhad A. Ali, C. Elaf A. Abbood, C. Shaymaa Abdul Kadhm, "Salt and Pepper Noise Removal Using Resizable
Window and Gaussian Estimation Function" International Journal of Electrical and Computer Engineering (IJECE),
Vol. 6, No. 5, pp. 2219~2224, October 2016.
[25] Chiuchisan, Iuliana. "An approach to the Verilog-based system for medical image enhancement." E-Health and
Bioengineering Conference (EHB), 2015. IEEE, 2015.
BIOGRAPHIES OF AUTHORS
Archana H R, Assistant Professor, Department of Electronics & Communication Engineering,
BMSCE, Bengaluru. She has around 8 years of Experience in Teaching and 1 year Industrial
Experience. She has published her papers in 2 international journals, presented at 7 international
conferences and 2 national conferences. She is pursuing her Ph.D. from VTU. Her Research area
is VLSI SOC.
Dr. Vasundara Patel K S, Associate Professor, Department of Electronics & Communication
Engineering, BMSCE, Bengaluru. She has around 17 years of Experience in Teaching; 3 years
Experience in Industry and 10 years in Research. She has published 20 papers in international
journals and presented around 30 papers in international conferences. She has done her Ph.D.
from Bangalore University. Presently working on VLSI.