This document presents a reconfigurable low power binary image processor for image processing applications. The processor consists of a reconfigurable binary processing module with mixed-grained architecture providing flexibility, efficiency and performance. Line memories are selected for lower power consumption and clock gating technique is used to reduce their power. The processor supports real-time binary image processing operations like morphological transformations and is suitable for applications like object recognition and tracking.

1. A Low Power and High Throughput Re-Configurable BIP for Multipurpose Applications
1
. R.Akshara ,2
..Murthy Raju
1
. M.tech, akshara.rentapalli@gmail.com, VLSID, Shri Vishnu Engineering College for Women, Bhimavaram
2
Associate Proff, venkateswara.106@gmail.com, E.C.E, Shri Vishnu Engineering College for Women, Bhimavaram
ABSTRACT: The main objective of this project is
to design a reconfigurable binary image processor to
perform real-time binary image processing. The
processor consists of a reconfigurable binary
processing module, input and output image control
units, and peripheral circuits. The reconfigurable
binary processing module has a mixed-grained
architecture with the characteristics of high efficiency
and performance. The dynamic reconfiguration
approach was used to increase the processor
performance. Basic mathematical morphology
operations and complicated algorithms can easily be
implemented on it because of its simple structure.
The processor, featured by high speed, simple
structure, and wide application range, is suitable for
binary image processing, such as object recognition,
object tracking and motion detection, computer
vision, identification, and authentication. Further this
technique is enhanced to design a reconfigurable low
power processor for image processing applications.
In-order to implement this processor, line memories
are selected for less power consumption. Line
memories power is reduced by using clock gating
technique.
KEYWORDS: mixed-grained architecture, binary
processing module, Reconfigurablility, Image
processing, object recognition, object tracking.
INTRODUCTION: BINARY IMAGE processing is
extremely useful in various areas, such as object
recognition, tracking, motion detection and machine
intelligence [1]–[6], image analysis and
understanding [7], [8], video processing [9],
computer vision [10], [11], and identification and
authentication systems [12]–[15]. Binary image
processing has been commonly implemented using
processors such as CPU or DSP. However, it is
inefficient and difficult to use such processors for
binary image processing [10], [11], [16]. High-speed
implementation of binary image processing
operations can be efficiently realized by using chips
specialized for binary image processing. Therefore,
binary image processing chips have attracted much
attention in the field of image processing.
Application-specific chips and hardware have been
reportedfor various applications. A chip with a 500-
dpi cellular-logic processing array was implemented
to enhance and verify fingerprint images [17]. A
pointing device using a specialized algorithm was
presented for motion detection in [18] .
Reconfigurable binary image processing chips have
been designed to generalize the binary image
applications of a chip. Chips were presented to
perform basic binary morphological operations, such
as dilation, erosion, opening, and closing [16], [20],
[21]. Programmable analog vision processors based
on the cellular neural or nonlinear network universal
machine architecture were proposed for a wide range
of applications such as motion analysis and texture
classification
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2. Literature Survey: [1]. A. J. Lipton, H. Fujiyoshi,
and R. S. Patil, “Moving target classification and
tracking from real-time video,” in Proc. Workshop
Appl. Comput. Vision, 1998, pp. 8–14.
This paper describes an end-to-end method for
extracting moving targets from a real-time video
stream, classifying them into predefined categories
according to image-based properties, and then
robustly tracking them. Moving targets are detected
using the pixel wise difference between consecutive
image frames. A classification metric is applied these
targets with a temporal consistency constraint to
classify them into three categories: human, vehicle or
background clutter. Drawbacks: Even though,
Background subtraction takes place properly, this
method is used for only object extraction for single
image.
[2]. M. R. Lyu, J. Song, and M. Cai, “A
comprehensive method for multilingual video text
detection, localization, and extraction,” IEEE Trans.
Circuit Syst. Video Technol., vol. 15, no. 2, pp. 243–
255, Feb. 2005.
This project deals in security applications. Any
texture or image can be embedded in to any cover
image. Hiding is the main criteria designed in this
project. Drawbacks: This project is used for only
images. But video security can’t be provided by using
this project.
[3]. W. Chan, J. Chang, T. Chen et al., “Efficient
content analysis engine for visual surveillance
network,” IEEE Trans. Circuits Syst. Video Technol.,
vol. 19, no. 5, pp. 693–703, May 2009.
The algorithm incorporates a temporal data
correlation predictor which can exhibit the
correlation between data and reduce computation
based on this correlation.
Drawbacks: Only small scale images can be
compresses and can’t be done for videos.
[4]. R. Dominguez-Castro, S. Espejo, A. Rodriguez-
Vazquez et al., “A 0.8-μm CMOS 2-D programmable
mixed-signal focal-plane array processor with on-
chip binary imaging and instructions storage,” IEEE
J. Solid-State Circuits, vol. 32, no. 7, pp. 1013–1026,
Jul. 1997.
This project designs tiny a processor, which can be
implemented in Cameras. This extra chip has the
capability to increase image quality and can remove
blurring effects also. Less area occupancy and low
latency are the main advantages by using this project.
Drawbacks: It can’t be implemented for shuttering
images. Only single snap shot images can be
processed through this chip.
This project presents a binary image processor that
consists of a reconfigurable binary processing
module, including reconfigurable binary compute
units and output control logic, input and output image
control units, and peripheral circuits. The
reconfigurable binary compute units are of a mixed
grained architecture, which has the characteristics of
high flexibility, efficiency, and performance. The
performance of the processor is enhanced by using
the dynamic reconfiguration approach. The processor
is implemented to perform real time binary image
processing. It is found that the processor can process
pixel-level images and extract image features, such as
boundary and motion images. Basic mathematical
morphology operations and complicated algorithms
can easily be implemented on it. The processor has
the merit of high speed, simple structure, and wide
application range.
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3. Fig1. Architecture of the binary image processor.
The proposed processor is designed for applications
in image or video processing, computer vision,
machine intelligence, and identification and
authentication systems. Such systems should have a
high flexibility and high performance processor for
wide applications; therefore, the processor design is
focused on high flexibility and speed. Some of the
conventional works are designed for specific
applications and some have large areas and high
power consumption. Then, a reconfigurable binary
processing module with high speed and simple
structure is implemented for wide use and consuming
fewer hardware resources. The architecture of the
proposed processor is shown in Fig. 1. The core of
the processor is a reconfigurable binary processing
module consisting of binary compute units and output
control logic. The processor also has two bus
interfaces, the input and output control logic units,
the process control unit, and a configuration register
group.
RECONFIGURABLE BINARY PROCESSING
MODULE:
The diagram of the reconfigurable binary processing
module (RBPM) is given in Fig. 2. It can be divided
into two main parts. The first part is the output
control logic, which selects the output from all the
binary compute unit outputs according to the given
parameters and converts the series data of 1-b binary
images into parallel data.
Fig2. Diagram of the reconfigurable binary
processing module
The second part consists of several binary compute
units that perform binary logic and binary image
operations at a high speed. The binary image
algorithms are realized by the operations in the
individual binary compute units and the connection
pattern of these units. The units can execute binary
image operations in a pipelined or parallel manner.
The operation executed in a binary compute unit is
decided by configurable registers, including logic
operation parameters, image resolution parameters;
mask sizes, input and output selection parameters,
and auxiliary parameters.
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4. The binary compute element comprises two input
control multiplexers, n binary logic elements, a
binary reduction element, and a binary median filter.
The input control multiplexer selects input data for
the binary logic element from the line memories, the
SDRAM, and the parameters in the register group.
When a video image is processed, line memories are
needed to buffer image signals before they are input
to binary logic elements. Line memory structure is
changed to the following structure.
Line memory address generator circuit:
Existing:
Proposed:
In proposed ring counter, power can be halved by
inserting SR control circuitry.
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Proceedings International Conference On Advances In Engineering And Technology
ISBN NO: 978 - 1503304048
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ISBN NO: 978 - 1503304048
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