An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance
In this paper fringe capacitance of double hetero gate Tunnel FET has been studied. The physical model for fringe capacitance is derived considering source gate overlap and gate drain non overlap. Inerface trap charge and oxide charges are also introduced under positive bias stress and hot carrier stress and their effect on fringe capacitance is also studied. The fringe capacitance is significant speed limiter in Double gate technology. The model is tested by comparing with simulation results obtained from Sentauras TCAD simulations.
SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylin...IJECEIAES
We propose a SPICE Drain Induced Barrier Lowering (DIBL) model for sub10 nm Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs. The DIBL shows the proportionl relation to the -3 power of the channel length L g and the 2 power of silicon thickness in MOSFET having a rectangular channel, but this relation cannot be used in cylindrical channel because of the difference in channel structure. The subthreshold currents, including the tunneling current from the WKB (Wentzel-Kramers-Brillouin) approximation as well as the diffusion-drift current, are used in the model. The constant current method is used to define the threshold voltage as the gate voltage at a constant current, (2πR/L g ) 10 -7 A for channel length and channel radius R. The central potential of the JLCSG MOSFET is determined by the Poisson equation. As a result, it can be seen that the DIBL of the JLCSG MOSFET is proportional to the –2.76 power of the channel length, to the 1.76 power of the channel radius, and linearly to the oxide film thickness. At this time, we observe that the SPICE parameter, the static feedback coefficient, has a value less than 1, and this model can be used to analyze the DIBL of the JLCSG MOSFET.
MODELING OF BUILT-IN POTENTIAL VARIATIONS OF CYLINDRICAL SURROUNDING GATE (CS...VLSICS Design
Due to aggressive scaling of MOSFETs the parasitic fringing field plays a major role in deciding its characteristics. These fringing fields are now not negligible and should be taken into account for deriving the MOSFET models. Due to this fringing field effect there are some charges induced in the source/drain extension regions which will change the potential barrier at the source-channel from its theoretical nominal values. In this paper an attempt has been made to model variation of built-in potential variation for a cylindrical surrounding gate MOSFET. The model has been verified to be working in good agreement with the variations of gate length and channel radius.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric ...TELKOMNIKA JOURNAL
This study is to analyze threshold voltage roll-off according to structural parameters of sub-10 nm
asymmetric double gate MOSFET. In case of sub-10nm channel length, because of short channel effects
resulting from the rapid increase of tunneling current, even asymmetric double gate (DG) MOSFET, which
has been developed for reducing short channel effects, will increase threshold voltage roll-off, and this is
an obstacle against the miniaturization of asymmetric DGMOSFET. Especially, since asymmetric
DGMOSFET can be produced differently in top and bottom oxide thickness, top/bottom oxide thickness will
affect the threshold voltage roll-off. To analyze this, thermal emission current and tunneling current model
have been calculated, and threshold voltage roll-off in accordance with the reduction of channel length has
been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is
found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly
according to top/bottom gate oxide thickness, and that threshold voltage roll-off, in particular, is generated
more greatly according to silicon thickness. In addition, it is found that top and bottom oxide thickness have
a relation of inverse proportion mutually for maintaining identical threshold voltage.
Impact of Gouy-Chapman-Stern model on conventional ISFET sensitivity and stab...TELKOMNIKA JOURNAL
Utilizing Gouy-Chapman-Stern model can improve ISFET sensitivity and stability using Stern layer in direct contact with electrolyte in ISFET sensing window. However, this model remains a challenge in mathematical way, unless it’s re-applied using accurate simulation approaches. Here, we developed an approach using a commercial Silvaco TCAD to re-apply Gouy-Chapman-Stern model as ISFET sensing membrane to investigate its impact on sensitivity and stability of conventional ISFET. Sio2 material and high-k Ta2O5 material have been examined based on Gouy-Chapman and Gouy-Chapman-Stern models. Results shows that the ISFET sensitivity of SiO2 sensing membrane is improved from ~38 mV/pH to ~51 mV/pH and the VTH shift stability is also improved. Additionally, the results indicate that the sensitivity of Ta2O5 is 59.03 mV/pH that hit the Nearnst Limit 59.3 mV/pH and achieves good agreements with mathematical model and previous experimental results. In conclusion, this investigation introduces a real validation of previous mathematical models using commercial TCAD approach rather than expensive fabrication that paves the way for further analysis and optimization.
Impact of multiple channels on the Characteristics of Rectangular GAA MOSFET IJECEIAES
Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is compared to a structure with 4 channels in order to highlight the impact of channels number on the device’s DC parameters (drain current and threshold voltage). Our single channel rectangular GAA MOSFET showed reasonable ratio Ion/Ioff of 10 4 , while our four channels GAA MOSFET showed a value of 10 3 . In addition, a low value of drain induced barrier lowering (DIBL) of 60mV/V was obtained for our single channel GAA and a lower value of with 40mv/v has been obtained for our four channel one. Also, an extrinsic transconductance of 88ms/µm have been obtained for our four channels GAA compared to the single channel that is equal to 7ms/µm.
SPICE model of drain induced barrier lowering in sub-10 nm junctionless cylin...IJECEIAES
We propose a SPICE Drain Induced Barrier Lowering (DIBL) model for sub10 nm Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs. The DIBL shows the proportionl relation to the -3 power of the channel length L g and the 2 power of silicon thickness in MOSFET having a rectangular channel, but this relation cannot be used in cylindrical channel because of the difference in channel structure. The subthreshold currents, including the tunneling current from the WKB (Wentzel-Kramers-Brillouin) approximation as well as the diffusion-drift current, are used in the model. The constant current method is used to define the threshold voltage as the gate voltage at a constant current, (2πR/L g ) 10 -7 A for channel length and channel radius R. The central potential of the JLCSG MOSFET is determined by the Poisson equation. As a result, it can be seen that the DIBL of the JLCSG MOSFET is proportional to the –2.76 power of the channel length, to the 1.76 power of the channel radius, and linearly to the oxide film thickness. At this time, we observe that the SPICE parameter, the static feedback coefficient, has a value less than 1, and this model can be used to analyze the DIBL of the JLCSG MOSFET.
MODELING OF BUILT-IN POTENTIAL VARIATIONS OF CYLINDRICAL SURROUNDING GATE (CS...VLSICS Design
Due to aggressive scaling of MOSFETs the parasitic fringing field plays a major role in deciding its characteristics. These fringing fields are now not negligible and should be taken into account for deriving the MOSFET models. Due to this fringing field effect there are some charges induced in the source/drain extension regions which will change the potential barrier at the source-channel from its theoretical nominal values. In this paper an attempt has been made to model variation of built-in potential variation for a cylindrical surrounding gate MOSFET. The model has been verified to be working in good agreement with the variations of gate length and channel radius.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric ...TELKOMNIKA JOURNAL
This study is to analyze threshold voltage roll-off according to structural parameters of sub-10 nm
asymmetric double gate MOSFET. In case of sub-10nm channel length, because of short channel effects
resulting from the rapid increase of tunneling current, even asymmetric double gate (DG) MOSFET, which
has been developed for reducing short channel effects, will increase threshold voltage roll-off, and this is
an obstacle against the miniaturization of asymmetric DGMOSFET. Especially, since asymmetric
DGMOSFET can be produced differently in top and bottom oxide thickness, top/bottom oxide thickness will
affect the threshold voltage roll-off. To analyze this, thermal emission current and tunneling current model
have been calculated, and threshold voltage roll-off in accordance with the reduction of channel length has
been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is
found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly
according to top/bottom gate oxide thickness, and that threshold voltage roll-off, in particular, is generated
more greatly according to silicon thickness. In addition, it is found that top and bottom oxide thickness have
a relation of inverse proportion mutually for maintaining identical threshold voltage.
Impact of Gouy-Chapman-Stern model on conventional ISFET sensitivity and stab...TELKOMNIKA JOURNAL
Utilizing Gouy-Chapman-Stern model can improve ISFET sensitivity and stability using Stern layer in direct contact with electrolyte in ISFET sensing window. However, this model remains a challenge in mathematical way, unless it’s re-applied using accurate simulation approaches. Here, we developed an approach using a commercial Silvaco TCAD to re-apply Gouy-Chapman-Stern model as ISFET sensing membrane to investigate its impact on sensitivity and stability of conventional ISFET. Sio2 material and high-k Ta2O5 material have been examined based on Gouy-Chapman and Gouy-Chapman-Stern models. Results shows that the ISFET sensitivity of SiO2 sensing membrane is improved from ~38 mV/pH to ~51 mV/pH and the VTH shift stability is also improved. Additionally, the results indicate that the sensitivity of Ta2O5 is 59.03 mV/pH that hit the Nearnst Limit 59.3 mV/pH and achieves good agreements with mathematical model and previous experimental results. In conclusion, this investigation introduces a real validation of previous mathematical models using commercial TCAD approach rather than expensive fabrication that paves the way for further analysis and optimization.
Impact of multiple channels on the Characteristics of Rectangular GAA MOSFET IJECEIAES
Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is compared to a structure with 4 channels in order to highlight the impact of channels number on the device’s DC parameters (drain current and threshold voltage). Our single channel rectangular GAA MOSFET showed reasonable ratio Ion/Ioff of 10 4 , while our four channels GAA MOSFET showed a value of 10 3 . In addition, a low value of drain induced barrier lowering (DIBL) of 60mV/V was obtained for our single channel GAA and a lower value of with 40mv/v has been obtained for our four channel one. Also, an extrinsic transconductance of 88ms/µm have been obtained for our four channels GAA compared to the single channel that is equal to 7ms/µm.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Deterioration of short channel effectsijistjournal
In the proposed work, the analytical model for Surface potential and Electric field has been carried out in a
novel structure named dual halo triple material Surrounding-gate metal-oxide-semiconductor field effect
transistor (DHTMSG). The new device has been incorporated with symmetrical dual halo regions near
source and drain ends, while the gate terminal consists of three different metals with different work
functions. The results prove that the device significantly deteriorates the short channel effects which are
studied by analytical model for surface potential and electric field using parabolic approximation method.
The analytical results are endorsed by the simulation results.
Central Electric Field and Threshold Voltage in Accumulation Mode Junctionles...IJECEIAES
Transfer characteristics is presented using analytical potential distribution of accumulation-mode junctionless cylindrical surrounding-gate (JLCSG) MOSFET, and deviation of center electric field at threshold voltage is analyzed for channel length and oxide thickness. Threshold voltages presented in this paper is good agreement with results of other compared papers, and transfer characteristics is agreed with those of two-dimensional simulation. The most important factor to determine threshold voltage is center electric field at source because the greater part of electron flows through center axis of JLCSG MOSFET. As a result of analysis for center electric field at threshold voltage, center electric field is decreased with reduction of channel length due to drain induced barrier lowering. Center electric field is increased with decrease of oxide thickness, and deviation of center electric field for channel length is significantly occurred with decrease of oxide thickness.
DESIGN OF THREE BIT ANALOG-TO-DIGITAL CONVERTER (ADC) USING SPATIAL WAVEFUNCT...VLSICS Design
The spatial wave-function switched field effect transistor (SWSFET) has two or three low band-gap
quantum well channels inside the substrate of the semiconductor. Applied voltage at the gate region of the
SWSFET, switches the charge carrier concentration in different channels from source to drain region. The
switching of electron wave function in different channels can be explained by the device model of the
SWSFET. A circuit model of SWSFET is developed in BSIM 4.0.0. The design of three bit analog-to-digital
converter (ADC) using one three wells SWSFET is explained in this work. Analog-to-digital converter
(ADC) circuit design using less number of SWSFET will reduce the device count in future analog and
digital circuit design
Accurate leakage current models for MOSFET nanoscale devices IJECEIAES
This paper underlines a closed form of MOSFET transistor’s leakage current mechanisms in the sub 100nmparadigm.The incorporation of drain induced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (I sub ) was investigated in detail. The Band-To-Band Tunneling (I BTBT ) due to the source and Drain PN reverse junction were also modeled with a close and accurate model using a rectangular approximation method (RJA). The three types of gate leakage (I G ) were also modeled and analyzed for parasitic (I GO ), inversion channel (I GC ), and gate substrate (I GB ). In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICE exhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper.
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
Simulation of DIBL effect in junctionless SOI MOSFETs with extended gateMahkam Xalilloyev
Short channel effects such as DIBL are compared for trigate SOI Junctionless MOSFET with extended and nonextended
lateral part of the gate.
A trigate SOI JLMOSFET with gate length Lgate, a silicon body width Wtin and thickness of 10 nm are simulated. In order to calculate the
DIBL, the transfer characteristics of JLMOSFETs was simulated at a donor concentration of 5 1019 cm 3 in the silicon body. The equivalent
oxide thicknesses of the HfO2 gate insulator used in simulation was 0.55 nm. Simulation result showed the DIBL for the trigate JLMOSFET
depended on the length of the lateral part of the gate Lext. DIBL is high for devices with gates having extended lateral parts. This is a result
of parasitic source (drain)gate
capacitance coupling which is higher for longer Lext.
The development of IGBT power modules has always been characterized by the continuous increase of the power density for cost reduction and design optimization of the complete frequency converter system. The requirement of higher power density is directly associated with increased current. Among those parameters, the breakdown voltage and on-state resistance rely on the doping concentration of the drift region in the power semiconductor, this effect can be more important for a higher voltage device. The trench structure differs from the conventional planar structure in that the gate oxide and conductive polysilicon gate electrode are formed in a deep narrow trench below the chip surface. When voltage is applied to the gate, a channel forms along the vertical wall of the trench perpendicular to the surface of the chip.
The vertical channel requires less chip area permitting a substantial increase in cell density. The increased cell density produces a greater channel width per unit chip area resulting in a reduction in the Rchannel portion of theIGBT’s on-state voltage drop. The second advantage of the trench structure is complete elimination of the "JFET" resistance (RJFET) which results from the constriction of current flow in the region between adjacent cells in the planar structure. Additionally, there are some less obvious secondary advantages of the trench structure. In particular, the non-uniform current density in the "JFET" region of the planar structure can result in SOA aberrations at high current densities. Physical based 2D simulation study is used to characterized Trench Gate IGBT with Carrier Storage (CS) Layer. Simulation results indicates to a complex nature of interaction between P-well, retrograde CS-layer and trench gate. For some reasons cell current with increasing CS-layer doping start degrades earlier than breakdown voltage.
Performance Analysis of Double Hetero-gate Tunnel Field Effect TransistorIDES Editor
A hetero gate dielectric low band gap material DG
Tunnel FET is presented here. The investigated device is
almost free from short channel effects like DIBL and Vt rolloff.
Simulation of the device characteristics shows significant
improvement over conventional double gate TFET when
compared interms of on current, ambipolar current, roll-off,
miller capacitance and, device delay time. Simulation is done
using TCAD tools.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
Comprehensive identification of sensitive and stable ISFET sensing layer high...IJECEIAES
The ISFET sensing membrane is in direct contact with the electrolyte solution, determining the starting sensitivity of these devices. A SiO2 gate dielectric shows a low response sensitivity and poor stability. This paper proposes a comprehensive identification of different high-k materials which can be used for this purpose, rather than SiO2. The Gouy-Chapman and Gouy-Chapman-Stern models were combined with the Site-binding model, based on surface potential sensitivity, to achieve the work objectives. Five materials, namely Al2O3, Ta2O5, Hfo2, Zro2 and SN2O3, which are commonly considered for micro-electronic applications, were compared. This study has identified that Ta2O5 have a high surface potential response at around 59mV/pH, and also exhibits high stability in different electrolyte concentrations. The models used have been validated with real experimental data, which achieved excellent agreement. The insights gained from this study may be of assistance to determine the suitability of different materials before progressing to expensive real ISFET fabrication.
Modeling and Structure Optimization of Tapped Transformer Yayah Zakaria
In this paper, a simplified circuit model of the tapped transformer structure has been presented to extract the Geometric and technology parameters and offer better physical understanding. Moreover, the structure of planar transformer has been optimized by using changing the width and space of the
primary coil, so as to enlarge the quality factor Q and high coupling coefficient K. To verify the results obtained by using these models, we have compared them with the results obtained by employing the MATLAB simulator. Very good agreement has been recorded for the effective primary
inductance value, whereas the effective primary quality factor value has shown a somewhat larger deviation than the inductance.
SUB TEN MICRON CHANNEL DEVICES ACHIEVED BY VERTICAL ORGANIC THIN FILM TRANSI...VLSICS Design
The channel lengths of the top contact organic thin film transistors are usually defined during their fabrication by optical lithography or by shadow masking during the metal deposition process. Realizing short channel (sub-ten micron channel length) transistors by lithography will require costly lithography equipment. On the other hand, it is extremely challenging to achieve short channel transistors using the low cost shadow mask process. One low cost method of achieving short channel devices is to build vertical transistors with the transistor, where the channel gets defined in the vertical part of the device. This paper shows that vertical channel top contact organic thin film transistor has been successfullyrealized on the vertical edge of trench. This helped in creating the device with channel lengths less than ten microns, much smaller than what could be typically achieved with the use of shadow masks.
Effects of Scaling on MOS Device Performanceiosrjce
This paper presents effects on MOS transistor performance due to scaling of its dimensions. Scaling
theory deals with the change in the device characteristics with the decrease in the dimensions of a MOS
transistor. MOS transistors are continuously scaled down due to the desire for high density and high
functionality VLSI chips. The driving forces behind these developments are increasing the demand for portable
systems requiring high throughput and high integration capacity. Effects of scaling on the performance
characteristics of a MOS device are analyzed in this paper
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Deterioration of short channel effectsijistjournal
In the proposed work, the analytical model for Surface potential and Electric field has been carried out in a
novel structure named dual halo triple material Surrounding-gate metal-oxide-semiconductor field effect
transistor (DHTMSG). The new device has been incorporated with symmetrical dual halo regions near
source and drain ends, while the gate terminal consists of three different metals with different work
functions. The results prove that the device significantly deteriorates the short channel effects which are
studied by analytical model for surface potential and electric field using parabolic approximation method.
The analytical results are endorsed by the simulation results.
Central Electric Field and Threshold Voltage in Accumulation Mode Junctionles...IJECEIAES
Transfer characteristics is presented using analytical potential distribution of accumulation-mode junctionless cylindrical surrounding-gate (JLCSG) MOSFET, and deviation of center electric field at threshold voltage is analyzed for channel length and oxide thickness. Threshold voltages presented in this paper is good agreement with results of other compared papers, and transfer characteristics is agreed with those of two-dimensional simulation. The most important factor to determine threshold voltage is center electric field at source because the greater part of electron flows through center axis of JLCSG MOSFET. As a result of analysis for center electric field at threshold voltage, center electric field is decreased with reduction of channel length due to drain induced barrier lowering. Center electric field is increased with decrease of oxide thickness, and deviation of center electric field for channel length is significantly occurred with decrease of oxide thickness.
DESIGN OF THREE BIT ANALOG-TO-DIGITAL CONVERTER (ADC) USING SPATIAL WAVEFUNCT...VLSICS Design
The spatial wave-function switched field effect transistor (SWSFET) has two or three low band-gap
quantum well channels inside the substrate of the semiconductor. Applied voltage at the gate region of the
SWSFET, switches the charge carrier concentration in different channels from source to drain region. The
switching of electron wave function in different channels can be explained by the device model of the
SWSFET. A circuit model of SWSFET is developed in BSIM 4.0.0. The design of three bit analog-to-digital
converter (ADC) using one three wells SWSFET is explained in this work. Analog-to-digital converter
(ADC) circuit design using less number of SWSFET will reduce the device count in future analog and
digital circuit design
Accurate leakage current models for MOSFET nanoscale devices IJECEIAES
This paper underlines a closed form of MOSFET transistor’s leakage current mechanisms in the sub 100nmparadigm.The incorporation of drain induced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage (I sub ) was investigated in detail. The Band-To-Band Tunneling (I BTBT ) due to the source and Drain PN reverse junction were also modeled with a close and accurate model using a rectangular approximation method (RJA). The three types of gate leakage (I G ) were also modeled and analyzed for parasitic (I GO ), inversion channel (I GC ), and gate substrate (I GB ). In addition, the leakage resources due to the aggressive reduction in the oxide thickness (<5nm) have been investigated. Simulation results using HSPICE exhibits a tremendous agreement with the BSIM4 model. The dominant value of the sub-threshold leakage was due to the DIBL and GIDL effects. Various recommendations regarding minimizing the leakage current at both device level and the circuit level were suggested at the end of this paper.
A coupled-line balun for ultra-wideband single-balanced diode mixerTELKOMNIKA JOURNAL
A multi-section coupled-line balun design for an ultra-wideband diode mixer is presented in this paper. The multi-section coupled-line balun was used to interface with the diode mixer in which it can deliver a good impedance matching between the diode mixer and input/output ports. The mixer design operates with a Local Oscillator (LO) power level of 10 dBm, Radio Frequency (RF) power level of -20 dBm and Intermediate Frequency (IF) of 100 MHz with the balun characteristic of 180° phase shift over UWB frequency (3.1 to 10.6 GHz), the mixer design demonstrated a good conversion loss of -8 to -16 dB over the frequency range from 3.1 to 10.6 GHz. Therefore, the proposed multi-section coupled-line balun for application of UWB mixer showed a good isolation between the mixer’s ports.
Simulation of DIBL effect in junctionless SOI MOSFETs with extended gateMahkam Xalilloyev
Short channel effects such as DIBL are compared for trigate SOI Junctionless MOSFET with extended and nonextended
lateral part of the gate.
A trigate SOI JLMOSFET with gate length Lgate, a silicon body width Wtin and thickness of 10 nm are simulated. In order to calculate the
DIBL, the transfer characteristics of JLMOSFETs was simulated at a donor concentration of 5 1019 cm 3 in the silicon body. The equivalent
oxide thicknesses of the HfO2 gate insulator used in simulation was 0.55 nm. Simulation result showed the DIBL for the trigate JLMOSFET
depended on the length of the lateral part of the gate Lext. DIBL is high for devices with gates having extended lateral parts. This is a result
of parasitic source (drain)gate
capacitance coupling which is higher for longer Lext.
The development of IGBT power modules has always been characterized by the continuous increase of the power density for cost reduction and design optimization of the complete frequency converter system. The requirement of higher power density is directly associated with increased current. Among those parameters, the breakdown voltage and on-state resistance rely on the doping concentration of the drift region in the power semiconductor, this effect can be more important for a higher voltage device. The trench structure differs from the conventional planar structure in that the gate oxide and conductive polysilicon gate electrode are formed in a deep narrow trench below the chip surface. When voltage is applied to the gate, a channel forms along the vertical wall of the trench perpendicular to the surface of the chip.
The vertical channel requires less chip area permitting a substantial increase in cell density. The increased cell density produces a greater channel width per unit chip area resulting in a reduction in the Rchannel portion of theIGBT’s on-state voltage drop. The second advantage of the trench structure is complete elimination of the "JFET" resistance (RJFET) which results from the constriction of current flow in the region between adjacent cells in the planar structure. Additionally, there are some less obvious secondary advantages of the trench structure. In particular, the non-uniform current density in the "JFET" region of the planar structure can result in SOA aberrations at high current densities. Physical based 2D simulation study is used to characterized Trench Gate IGBT with Carrier Storage (CS) Layer. Simulation results indicates to a complex nature of interaction between P-well, retrograde CS-layer and trench gate. For some reasons cell current with increasing CS-layer doping start degrades earlier than breakdown voltage.
Performance Analysis of Double Hetero-gate Tunnel Field Effect TransistorIDES Editor
A hetero gate dielectric low band gap material DG
Tunnel FET is presented here. The investigated device is
almost free from short channel effects like DIBL and Vt rolloff.
Simulation of the device characteristics shows significant
improvement over conventional double gate TFET when
compared interms of on current, ambipolar current, roll-off,
miller capacitance and, device delay time. Simulation is done
using TCAD tools.
CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELLVLSICS Design
In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).
Comprehensive identification of sensitive and stable ISFET sensing layer high...IJECEIAES
The ISFET sensing membrane is in direct contact with the electrolyte solution, determining the starting sensitivity of these devices. A SiO2 gate dielectric shows a low response sensitivity and poor stability. This paper proposes a comprehensive identification of different high-k materials which can be used for this purpose, rather than SiO2. The Gouy-Chapman and Gouy-Chapman-Stern models were combined with the Site-binding model, based on surface potential sensitivity, to achieve the work objectives. Five materials, namely Al2O3, Ta2O5, Hfo2, Zro2 and SN2O3, which are commonly considered for micro-electronic applications, were compared. This study has identified that Ta2O5 have a high surface potential response at around 59mV/pH, and also exhibits high stability in different electrolyte concentrations. The models used have been validated with real experimental data, which achieved excellent agreement. The insights gained from this study may be of assistance to determine the suitability of different materials before progressing to expensive real ISFET fabrication.
Modeling and Structure Optimization of Tapped Transformer Yayah Zakaria
In this paper, a simplified circuit model of the tapped transformer structure has been presented to extract the Geometric and technology parameters and offer better physical understanding. Moreover, the structure of planar transformer has been optimized by using changing the width and space of the
primary coil, so as to enlarge the quality factor Q and high coupling coefficient K. To verify the results obtained by using these models, we have compared them with the results obtained by employing the MATLAB simulator. Very good agreement has been recorded for the effective primary
inductance value, whereas the effective primary quality factor value has shown a somewhat larger deviation than the inductance.
SUB TEN MICRON CHANNEL DEVICES ACHIEVED BY VERTICAL ORGANIC THIN FILM TRANSI...VLSICS Design
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An Analytical Model for Fringing Capacitance in Double gate Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012
DOI : 10.5121/vlsic.2012.3101 1
An Analytical Model for Fringing Capacitance in
Double gate Hetero Tunnel FET and Analysis of
effect of Traps and Oxide charges on Fringing
Capacitance
Brinda Bhowmick1
and Srimanta Baishya2
1
Department of Electronics and Communication Engineering, National Institute of
Technology Silchar, Silchar, India
brinda_bh@yahoo.co.in
2
Department of Electronics and Communication Engineering, National Institute of
Technology Silchar, Silchar, India
baishya_s@rediffmail.com
ABSTRACT
In this paper fringe capacitance of double hetero gate Tunnel FET has been studied. The physical model
for fringe capacitance is derived considering source gate overlap and gate drain non overlap. Inerface trap
charge and oxide charges are also introduced under positive bias stress and hot carrier stress and their
effect on fringe capacitance is also studied. The fringe capacitance is significant speed limiter in Double
gate technology. The model is tested by comparing with simulation results obtained from Sentauras TCAD
simulations.
KEYWORDS
Band-to-band tunnelling, hetero-gate, parasitic fringe capacitance.
1. INTRODUCTION
As MOSFETs are scaled to nanometer dimensions, various short channel effects such as DIBL,
VT roll-off, sub 60mV/decade subthreshold swing etc are coming into picture. Subthreshold
swing can not be scaled and hence off state characteristics will be degraded [1]. To overcome
short channel effects, one needs to design a device which uses other mode of carrier transport so
that a lower subthreshold swing can be achieved. The other modes are based on impact ionization
[2] and interband tunneling [3]. Sub 60mV/decade value of subthreshold swing is possible for
these two modes of carrier transport [4]. The impact ionization MOSFET appeared to be very
promising due to its near ideal switching characteristics [5]. But problems like threshold voltage
shift caused by hot carrier injection, non-rail to rail voltage swings, and high operating voltage
requirements will arise in Impact ionization MOSFETS [2]. However, devices based on these
mechanisms fail to meet the ITRS requirements [6].
Here a hetero gate tunnel FET based on band-to-band tunneling is considered for which a good
trade off between SCEs , parasitic fringe capacitance, and parasitic series resistance is achieved
[7]-[8] . The fringe capacitance (Cf) for this device includes the inner and outer components.
Unlike MOSFET, tunnel FET has asymmetrical source and drain [8]. The gate is extended over
the source but gate on the drain side is shorten. This is due to increase the gate coupling i.e to
increase the control of gate over the source channel junction. Models for Cif and Cof for the double
MOSFETS are already defined [9]. In nano scale DG MOSFETS the models are defined
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012
2
considering weak inversion and strong inversion of channel [10]. Since tunnel FET operation is
completely different from MOSFET, the derivations for inner and outer fringe capacitance is also
different. For the first time, the inner and outer components of parasitic fringe capacitance is
modelled for tunnel FET. The model is verified by comparing with simulated data for varying
silicon layer thickness, oxide thickness, drain voltage, and gate voltage.
In this paper, we report first time the effect of positive bias stress and hot carrier stress on the
fringe capacitor of double hetero gate tunnel FET. To simulate this, interface traps (QIT) and
oxide charges (QOT) are introduced with various distributions. The oxide charge is dominant in
case of hot carrier stress and the interface traps are dominant in case of positive bias stress [11].
2. Device structure and parasitic capacitances
The device is a heterogate dielectric double gate device as shown in Figure. 1. It can operate both
in n and p channel modes . In p mode, gs AV V< and in n mode, gs AV V> , where AV is a
reference voltage required to align the +
P valence band and channel conduction band. In n-
channel mode, tunneling occurs in the source side while in p-channel mode, tunneling occurs in
the drain side. An electron inversion layer is created in the channel at the interface with the gate
dielectric when a gate voltage greater FV is applied. Tunneling takes place from the source
valence band to the conduction band in the inversion layer of the channel [3]. As mentioned, we
have used heterogate dielectric. A low-K gate oxide (SiO2 with dielectric constant 3.9) at the
drain side and high-K oxide (HfO2 with dielectric constant 25) at the tunneling junction are used.
To reduce the ambipolar current at the drain side, low-K gate oxide is used. The EOT of high-K
gate oxide is less so it increases the control over the tunneling junction and here tunneling takes
place between source and channel [12]. The on current of the device is of the order of mA range
and off current is in pico amp range. This agrees with ITRS requirement. The fringe capacitance
effect is studied to investigate its effect on drain current. Also, the effect of trap and oxide charges
are observed on the fringe capacitance model.
The fringe capacitance ( )fC of double heterogate tunnel FET includes inner ( )i fC and outer
components ( )o fC as shown in Figure. 1. There is a choice to be made between attaining the best
characteristics possible by finding the precise alignment of the gate that produces the thin tunnel
barrier at on-state, and stabilizing characteristics by overlapping the gate to the source region.
There is no gate drain overlapping .Hence, the fringe capacitance at the source side is assumed to
be dominant compare to the drain side. In the Fig. 2, the fringe capacitance of only one gate is
shown. The other gate is also symmetric about X direction and having the similar fringing effect.
This paper is organized as follows – first the inner and outer fringe capacitances are modelled.
Next the influence of variation of tsi ,tox on fringe capacitance model is compared with simulated
data. The effect of fringe capacitance on the total gate capacitance is also observed. The trap and
oxide charges are introduced and their effect on fringe capacitance is analyzed.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012
3
Figure 1. Hetero double gate dielectric tunnel FET with fringe capacitance components.
3. PHYSICAL MODEL
3.1. Model of ofC
Assume outer fringing field is Y directional. Dotted line is showing Gaussian surface. oxt is the
oxide thickness, sit is body layer thickness.
( )2 , (1)of si y fQ E x y Lε=
1 2( ) 2 ( ) (2)yE a x a x y= +
( ,0) ( )
( , ) { ( ) }
(3)
{ ( ) }( ,0)
s
si ox s
si ox
ox s
si ox
x x
d x t x
dy t
xd x
dy t
ψ ψ
ψ ε ψ ν
ε
ε ψ νψ
ε
=
−
= −
−
=
the coefficients 1( )a x , and 2 ( )a x are determined from this solution under the boundary
conditions for potentials are given in (3).
( )s xψ is the surface potential, ν is the difference of GS FBV and V .
( , )
2 (4)
y
of si f
GS
dE x y
C L
dV
ε=
Using (2) and (3) we get,
2
2 1 (5)ox
of f
ox si
y
C L
t t
ε
= − −
3.2. Model of ifC
Inner fringing field is assumed to be X directional as shown in Figure.1. Applying Gauss’s law
we get,
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012
4
( )
( )si0, t
2 - 2 ,0 (6)
2
si x
if si y f
E y
Q E x L
ε
ε= −
The second term is very small compare to the first term.
2( ) 1
2
( ) ( )
(7)
s s
ox ox
s
x
si ox si ox si
d x
E y
dx t t t
d x d x
dx dx
y
ε ε
ψ
ε ε
ψ ψ
υ υ
= + −
− −
(0, )
(8)x
if si si
GS
dE y
C t
dV
ε=
2(0, ) 1
= - y + y (9)
2
x ox ox
GS si ox si ox si
dE y
dV t t t
ε ε
ε ε
3.3 Model of fringe capacitance considering interface traps and oxide charges
To study the reliability performance of double gate tunnel FET, we simulate the fringe
capacitance considering various traps and oxide charges. Any traps and/or charge near the
tunnelling junction will modify the tunnelling field [13].
Considering above equations we can modify the fringe capacitance by modifying the
gs
dE
dV
.
2 2(0, ) 1 1
= - y + y - - y + y (10)
2 2
x ox ox ox oxFB
GS si ox si ox si GS si ox si ox si
dE y dV
dV t t t dV t t t
ε ε ε ε
ε ε ε ε
( , ) 2 2
= - 1 + 1
y ox oxFB
GS si ox si GS si ox si
dE x y dVy y
dV t t dV t t
ε ε
ε ε
− −
1
= - (11)GS GSFB
GS o
OT IT
dE dE
dV dVdV
dE dEdV C
dQ dQ
+
where Co is the oxide capacitance.
It is already established that both the factor in (11) are nearly independent on VG, leading to
parallel shift .A small modification in E may cause a large change in the tunneling current Id. In
order to keep a constant ID, the gate voltage VG should be modified [11]. The change in gate
voltage induced by interface generation and by oxide charge to keep the drain current constant is
given by
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012
5
DGS at I =0V = - (12)
ITIT
IT
IT
G
dE
dQ dQ
N
dE dN
dV
∆
∆ ∆
DGS at I =0V = - (13)oT
oT
G
dE
dQ
Q
dE
dV
∆
∆ ∆
IT
IT
dQ
dN
is the charge filling factor of traps.
Both the factors in [ ] are nearly independent on VGS . The variation in flat band voltage with
respect to gate voltage can be obtained by using (12) and (13).
3. Result and Discussions
In this paper simulation is done using Synopsys TCAD tools. Band gap narrowing is activated.
The device is a hetero gate dielectric double gate Tunnel FET for which fringing capacitance is
considered only at the source side since there is no gate drain overlap. In Figure. 2, the variation
of body layer thickness on external fringe capacitance is observed. With the increasing tsi, Cof
increases. Cif is also increases with tsi. The model and the simulated data shows good agreement.
But for increasing tsi , model becomes less accurate. This is because of neglecting the second term
in (6). The fringe capacitance components are decreasing with the increase of oxide thickness.
Hence there is a trade off between oxide thickness and the silicon body layer thickness. Therefore
optimized value of silicon layer thickness 15 nm to 20 nm and for tox, the optimized value should
lie in-between 2.5 nm to 3 nm to get minimum fringe capacitance Cf. The effect of fringe
capacitance on the total gate capacitance is shown in Figure. 6. The effect of oxide and trap
charge on capacitance voltage characteristic including fringe capacitance is also analyzed and it is
observed that Cf is a significant speed limiter in double gate technology [14]-[15]. Therefore, Cf
should be minimized. Using the results of the derived model and simulation shows that the tox, tsi
should be optimized.
Here the effect of trap charges and oxide charges are also studied. To realize the effects , we
simlulate the electric field under the positive bias stress ( VG = 3.5V, VS = VD = 0) and hot carrier
stress ( VG=VD=3.5V, Vs=0). In Figure. 7, ID-VGS characteristics considering Positve bias stress
and hot carrier stress (HC) is compared.
The variation of Ey and Ex along the channel are shown in Figure.8 and Figure. 9 under positive
bias stress and HC stress.The peak in the y component of electric field in the source channel
junction leading to the fact that P+ doping of source which gives rise to more negative VFB in the
source gate overlapping region compared to channel gate region [16]-[18]. Ex peak is also in the
source channel junction. Hence Ey peak will induce large interface traps and tunneling charge in
the tunneling path and oxide charge is more likely generated under HC stress [11]. Considering
the effects of interface traps and oxide charges, the model of fringe capacitance in (5) and (8) are
modified. This modified model includes the
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012
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FB
GS
dV
dV term. The flat band voltage is a function of interface and oxide charges. In Figure. 10, the
variation of inner and outer fringe capacitance considering interface trap and oxide charges with
the silicon layer thickness is shown. The effect of trap and oxide charge on inner fringe
capacitance is almost same. But in case of outer fringe capacitor, the effect of interface trap
charge is more compare to oxide charge because Ex exhibits higher value under HC stress.
Figure. 2 Outer fringing capacitance increases with body layer thickness.
Figure. 3 Inner fringing capacitance for model and simulated data are plotted for various tsi
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Figure. 4 Outer fringe capacitance decreases with increase in oxide thickness.
Figure . 5 There is close match between the model and simulated values.
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Figure. 6 Capacitance voltage characteristic
Figure. 7 Effect of interface trap and oxide charge on the degradation of drain current at
VDS=1V.. The ID degradation is mainly induced by interface traps and oxide charges within 10
nm range above the tunneling region along the X-direction .
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Figure. 8 The tunnel junction is x =70nm.
Figure. 9 EX peak is located near the source channel junction which may induce impact
ionization.
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Figure. 10
4. CONCLUSIONS
In this paper, the degradation in the drain current due to interface trap and/or oxide charges is
investigated. For the first time the inner and outer fringe capacitance of a hetero double gate
dielectric is modelled and optimized considering the variation of silicon layer thickness and oxide
thickness. It is found that optimised value of silicon body thickness is 15 to 20 nm and the same
for gate oxide is 2.5 to 3 nm. Also, the effect of trap and oxide charge is analyzed on inner and
outer fringe capacitance model and shows degradation in drain current as well as capacitance
voltage characteristics. The results obtained could be useful while considering for the reliability
issues.
ACKNOWLEDGEMENTS
This work was supported by ALL INDIA COUNCIL FOR TECHNICAL EDUCATION
(AICTE), under Grant 8023/BOR/RID/RPS-253/2008-09.
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Authors
Brinda Bhowmick is an Assistant Prof. in Electronics and Communication Engineering Deptt. NIT Silchar,
Deemed university, ASSAM, India. She is doing research in semiconductor device modelling.
Dr. Srimanta Baishya is a Professor of ECE Deptt. NIT Silchar, Deemed university, ASSAM, India. He is a
member of IEEE. His research interest includes semiconductor device modelling, process integration and
technology development. He has more than thirty International conference and Journal papers.