Adv mp&arm.pdf

AdvancedMicroprocessors&ARM Processor
JSR, CSE, AMCEC 2
AMC ENGINEERING COLLEGE
DEPARMENT OF
COMPUTER SCIENCE AND ENGINEERING
Advanced Microprocessors
And Arm Processor
PREPARED BY- JAYASHUBHA J.,
DEPARTMENT OF COMPUTER SCIENCE,
AMCEC

JSR, CSE, AMCEC 3
Advanced Microprocessors and Arm Processor
Table of Contents
Sl.No. Contents Page No.
Chapter 1
Introduction,
Microprocessor Architecture
4
Chapter 2
Addressing Modes
20
Chapter 3
Instructions
42
Chapter 4
Logical Instructions
66
Chapter 5
Hardware Specification,
Memory Interface – I 74
Chapter 6
I/O Interface, Interrupts
And DMA
90
Chapter 7 ARM Processor Basics 106
Chapter 8
ARM Instructions
126

JSR, CSE, AMCEC 4
CHAPTER - 1
Introduction, Microprocessor Architecture
Historical Background:
Provides a historical perspective of the fast-paced evolution of the computer.
The Mechanical Age:
The Babylonians during 500 B.C. got the idea of calculating with a machine and invented
the abacus- the first mechanical calculator. It had strings of beads to calculate, the
Babylonian priests used this to keep track of their vast store houses of grain.
Then during 1642, mathematician Blaise Pascal invented a calculator with gears and
wheels. Each gear contained 10 teeth after one complete revolution; it proceeds to the
second gear. This is the basis of all mechanical calculators. Also the PASCAL
programming is named in honour of Blaise Pascal for the mechanical calculator and his
pioneering work in mathematics.
During early 1800’s the first practical geared mechanical machines came for automatic
computing. By 1823 Charles Babbage was commissioned to produce a programmable
calculating machine, which was to generate navigational tables for the Royal Navy. This
was called as Analytical Engine and it was a steam powered mechanical computer to
store 1000 twenty-digit decimal numbers and a variable program to modify the functions
suitably.
The input had to be given through punched cards. But Babbage could not build the
engine as those day mechanics were not able to create the mechanical parts to complete
his engine.
Electrical Age:
Later in 1800’s the electric motor was invented. Using this many types of motor-driven
adding machines came. All these were based on Pascal’s mechanical calculator. These
electrical driven mechanical calculators were commonly used in offices till 1970’s as by
then the small hand-held electronic calculator was launched by Bomar- Corporation and
called it Bomar Brain.
In 1889, Herman Hollerith developed a mechanical machine for tabulating using
punched cards. These punched cards are called Hollerith cards and the 12-bit code on a
punched card is called Hollerith code.
Electronic Age:
In 1941 the first electronic calculating machine was invented by Konard Zuse. Zuse first
constructed a mechanical system in 1936 and later constructed his first
electromechanical computer system in 1939 and called it Z2. His next version i.e. Z3-
calculating computer was used in aircraft and missile design during World War II for the
German war.
Z3 was a relay logic machine with a 5.33Hz clock. (Recently it was discovered that the
first electronic computer was invented by Alan Turing and he called it as Colossus. It was
not programmable, it was a fixed program computer also called as a special-purpose
computer.)
The first programmable electronic computer was developed in 1946 at the University of
Pennsylvania and it is called the ENIAC- Electronic Numerical Integrator and Calculator.

JSR, CSE, AMCEC 5
It was very huge and contained more than 17,000 vacuum tubes and over 500 miles of
wires which weighed over 30 tons. It could perform about 100,000 operations per second.
ENIAC was programmed by reviewing its circuits by many workers. Also the vacuum
tubes needed frequent maintenance.
In December 23, 1947 transistor was developed at the Bell Labs by John Bardeen,
William Shockley and Walter Brattain.
Then the Integrated Circuit was invented by Jack Kilby of Texas instruments in 1958.
This led to the development of Digital Integrated circuits in 1960. Later in 1971 the first
microprocessor was developed by Intel Corporation and was called 4004.
Programming Advancements:
Programs and programming languages were needed for the programmable machines to
control the computer. The first programming language was the Machine language. It
was built of ‘ones’ and ‘zeros’ using binary codes that were stored in the computer
memory system as groups of instructions called as a program. Machine language was
much better than rewiring a machine to program it. But it consumed a lot of time to
develop a program. Then John Von Neumann developed a system which accepted
instructions and stored them in memory.
In 1950’s with the arrival of UNIVAC systems, assembly language was developed. This
allowed the programmer to use mnemonic codes like ADD for addition instead of a binary
number. Then in 1957 Grace Hopper developed the first high-level programming
language called FLOWMATIC which made programming easier.
FORTAN (Formula Translator) was developed by IBM in the same year which could be
used by programmers to develop programs to solve mathematical programs using
formulas.
Almost a year later a similar language called ALGOL (ALGOrithmic Language) was
developed. The first successful programming language for business applications was
COBOL (Computer Business Oriented Language).
One more business language is RPG (Report Program Generator), it was programmed by
specifying the form of input-output and calculations.
A few common additional languages are BASIC, JAVA, C#, C/C++, PASCAL and ADA.

JSR, CSE, AMCEC 6
The Microprocessor Age:
Started from 1971. The first microprocessor was the Intel 4004. It was a 4-bit
microprocessor which could be programmed and controlled.
No. Of addresses- 4096 of 4-bit wide memory locations.
No. Of instructions- 45
Speed- 50 kilo-instructions per sec –KIPS.
ENIAC- 100,000 instructions per sec.
4004 – with higher speed and same word length.
4-bit ps are used even now for low-end applications like microwave oven and small
control systems. Most of the calculators are 4-bit BCD microprocessors.
Then Intel released 8008- with 8 bit word length, 16KB of memory sizes and 48
instructions. This could be used in advanced systems. In 1973 Intel released the 8080
the first modern microprocessor. Six months later Motorola introduced MC6800
microprocessor.
8080- had 4 times memory and its speed was 10 times faster than 8008. I.e. 64KB of
memory.
8085- Was introduced by Intel in 1977. It was also an 8 bit processor which could
execute software at a higher speed and costed less.
The Modern Microprocessors:
8086- Was released by Intel in 1978 and was followed with the 8088. Both are 16-bit
processors with a speed of 2.5 MIPS. They address 1Mbyte of memory. 8086/88 has
instruction queue to pre-fetch instructions to speed up the operations.
Additional features of 8086/88 are:
1. Queue/cache memory.
2. Large memory of 1M byte.
3. Instructions set included multiply and divide instructions.
4. No. Of instructions increased to 20,000 variations.
5. 8086/88 is called CISC- Computer instructions set computers.
6. Bigger Internal memory.
In 1981, IBM used 8088 µp in its personnel computer. But its memory was limiting the
use of applications like spreadsheets, word processors etc. Hence in 1983- Intel brought
out the 80286 µp.
80286:
 Similar to 8086/88 with huge memory of 16MB.
 Similar instruction set with a speed of 4.0 MIPS.
 16 bit µp processor.
80386:
 Arrived in 1986, the first 32 bit µp.
 Have a 32-bit data bus and a 32-bit memory address.
 Addressed up to 4GB memory.

JSR, CSE, AMCEC 7
80486:
 1989
 Have 8KB cache memory, a numeric coprocessor 80387 and a microprocessor like
80386.
 Speed of 50 MIPS.
Pentium:
 Operated with 60MHz clock at speed of 110 MIPS.
 Cache of 16KB.
 64-bit processor.
 Executes two instructions simultaneously i.e. dual integer processor.
 Pentium can replace the RISC- Reduced Instruction Set Computer.
Pentium Pro Processor:
 150 MHz clock.
 2 levels cache (16+256).
 64GB memory.
Pentium II:
 64 bit bus, 64GB memory, 2 levels of cache (32+256).
Pentium III:
Pentium 4:
Core 2:
 64 bit bus, 1TB memory, 2 levels of cache (32+2/4MB).
Conceptual views of 80486, Pentium pro, Pentium-II, Pentium-III, Pentium-4
and core-2 Microprocessors

JSR, CSE, AMCEC 8
Microprocessor-Based Personal Computer System:
The developments in the computer system mainly focused on reducing the size of the
computer and increase its memory capacity, processing speed and power.
All these were possible only with the advances of the microprocessors.
Initially two types of computer systems were built i.e. the
1. Mainframe Computer System (MCS).
2. Personal Computer System (PCS).
The PCs built with microprocessors are called microprocessor based personal computer
system.
Block Diagram:
The Memory System:
The memory system is divided into 3 main parts;
1. Transient Program Area.
2. System area.
3. XMS- Extended Memory System.
The computer based 8086/88 has TPA and system area only. It does not have extended
memory area. TPA is of 640 KB and system memory is of 384KB. The first 1MB of memory
is called as real or conventional memory system as the microprocessor functions in this
area
using real mode of operation. Computer systems based on the 80286 to core 2 contain
the extended memory area along with TPA and system area as shown in the following
diagram

JSR, CSE, AMCEC 9
TPA: The transient program area holds the disk operating system (DOS) and other control
programs. It also stores any currently active or inactive DOS application programs.
A portion of TPA holds DOS as below.
MS DOS occupies 12KB of the TPA and the remaining 628KB can be used for application
software.
Interrupt Vectors access many features of the DOS, BIOS (Basic I/O system) and
applications.
System BIOS is a collection of programs stored in ROM or Flash memory (flash memory
operates many I/O devices).
The system BIOS and DOS have the transient data used by programs to access I/O
devices and other internal features of the computer. This helps to change these data as
the DOS operates.
IO.SYS loads into the TPA from the disk when the MSDOS system is started.
It has the programs which allow DOS to use the keyboard, video display, printer and
other I/O devices.
It links the DOS to the programs stored in BIOS ROM.
Drivers control the I/O devices like mouse, disk cave, scanner, CD ROM memory, DVD
etc..
COMMAND.COM controls the operation of the computer from the keyboard during DOS
operation mode.

JSR, CSE, AMCEC 10
System Area:
System area contains programs on ROM or flash memory and areas of read/write (RAM)
for data storage.
BIOS.SYSTEM ROM : controls the operation of only basic I/O devices connected to the
computer.
Basic Langauge ROM : is free in latest computer system
Free Area: used for expanded memory system(EMS) in PC/XT , and for the upper
memory in AT system
Video BIOS & Video RAM: contain video display RAM and video control programs on
ROM/Flash memory
I/O SYSTEM/SPACE: I/O space in a computer starts from I/O port 0000H to port
FFFFH.
-I/O devices help the microprocessor to communicate between itself and the user.
-It allows the computer to access upto 64,000 different 8-bit I/O devices, 32,000
different 16-bit devices or 16,000 different 32 bit I/O devices.
-I/O space from 0000H to 0400H is reserved fro specific I/O devices & the space above
that is available for I/O expansion.
-Most I/O accessing is done through DOS or BIOS.

JSR, CSE, AMCEC 11
THE MICROPROCESSOR : It is an integrated circuit which is the heart of the
microprocessor based computer system. It is also referred as the CPU-the Central
Processing Unit as it controls memory and I/O through buses.
The 3 main tasks of a microprocessor are:
1) Data transfer between itself and memory or I/O systems
2) Perform Simple arithmetic and logical operations
3) Control Program flow through simple decisions.
The power of a microprocessor is in its execution capability. That is billions of millions
of instructions per second from a program or software stored in the memory. This is the
stored program concept.
The decision making ability of a microprocessor also makes it powerful i.e. the
microprocessor can decide if a number is zero, or positive and so on.
The basic arithmetic and logical operations executed by Intel microprocessors are:
Arithmetic: Addition, Subtraction, Multiplication, Division, Negate
Logical: AND, OR, NOT, SHIFT, ROTATE.
Data widths for these operations can vary as below:
BYTE: 8 bits
WORD: 16 bits - 8086 and above
Double Word-DWORD: 32 bits-80386 and above
Quad Word-QWORD:64 bits-Pentium and above
BUSES: A bus is a common group of wires that interconnect components in a
computer system.
Bus transfers address data and control information between the microprocessor and
its memory and I/O systems.
A microprocessor based PC system contains 3 buses for transfer of information i.e.
Address Bus, Data bus and Control Bus. The interconnection of buses are as shown
below:

JSR, CSE, AMCEC 12
Address Bus:
Requests a memory location from the memory or an I/O location.
If I/O is addressed, the address bus has a 16-bit I/O address between 0000H to FFFFH.
This 16-bit I/O address selects one of the 64K different I/O devices.
If memory is addressed the address bus has a memory address of 20-bit 8086 and 8088
microprocessors and it ranges between 00000H to FFFFFH. For 80266 and 80386Sx the
address of memory will be 24-bits ranging between 000000H- FFFFFFH.
Data Bus:
Transfers information between the microprocessor and its memory and I/O address
space. The size of data transfer varies with each microprocessor.
Ex: 8088 has 8-bit data bus and transfers 8-bit at a time. But 8086, 80286, 80386Sx,
80386Ex transfer 16 bits of data etc.
The Control Bus: has a line which selects the memory or I/O and makes them to perform
a read or write operation.
There are usually four control bus connections:
MRDC- Memory Read Control
MWTC- Memory Write Control
IORC- I/O Read Control
IOWC- I/O Write Control
The bar indicates that these lines are active when a logic zero appears on the control line.
The microprocessor first sends the address of the location through the address bus and
immediately sends a control signal MRDC to that location and makes the memory to read
the data. This data read from the memory is then passed to the microprocessor through
the data bus.
Microprocessor and its Architecture:
Internal Microprocessor Architecture: In a multiple core microprocessor each core
contains the same programming model.
Programming Model: The programming model of 8086 to the core 2 considered as
program visible because its registers are used for application programming and are
specified by the user, through instructions.
A few registers which are detailed later are programming invisible as they are not
addressable directly during application programming.
The programming model for the Microprocessors from 8086-to-core-2 are shown
below: The shaded portion is the below diagram represents the register set of 8086
microprocessor.
The earlier 8086, 8088 and 80286 have 16-bit internal architectures shown with shading
in the above figure. These 16-bit registers are upward compatible to 80386 through the
core 2 microprocessors.
The 8-bit registers are: AH, AL, BH, BL, CH, CL, DH and DL.
These are used when an instruction is of 2 letter designation.
Ex: ADD AL, AH

JSR, CSE, AMCEC 13
The 16-bit registers have a pair of 8-bit registers i.e. AX has AH and AL. These registers
are referred with 2-letter designations like AX.
Ex: ADD DX, CX
The 32-bit registers are EAX, EBX, ECX, EDX, ESP, EBP, EDI, ESI, EIP and EFLAGS.
These are available only in 80386 and above microprocessors.
Ex: ADD ECX, EBX
The registers EAX, EBX, ECX, EDX, EBP, EDI and ESI are the general purpose or
multipurpose registers. These registers can hold data of various sizes i.e. bytes, words or
double words and they can be used for any purpose.
The RAX, RBX etc are the 64-bit registers. R8 through R15 are the additional 64-bit
registers. The available register space is multiplied by more than 8 times in the P4 and
core 2 when compared to the 8086 architecture.
Overrides used to access a particular of a 64-bit register.
Register
Size
Override Bits
Accessed
Example
8 bits B 7-0 MOV R9B, R10B
16 bits W 15-0 MOV R10W, AX
32 bits D 31-0 MOV R14D, R15D
64 bits - 63-0 MOV R13, R12

JSR, CSE, AMCEC 14
To access the lower byte of the R8 register use R8B.
Similarly to access lower word of R10 register use R10W.
Use D to access the lower double word.
Multipurpose Registers:
RAX (accumulator):
RAX for 64-bit, EAX for 32-bit, AX for 16-bits or AH/AL for 8-bit registers. Accumulator
is used to store one of operands for instructions like multiplication, division and
adjustment instructions. Else it is a general purpose or multipurpose register.
RBX(Base Index):
RBX holds the Base address or the starting address for array type of data. It is also
addressable as RBX, EBX, BX, BH or BL w.r.t data size. BX register may sometimes hold
the offset address of a location in the memory.
RCX(Count):
Can also be addressed as ECX, CX, CH or CL. This is a general purpose register and it
also holds the count for several instructions. The repeated string instruction(REP) shift,
rotate and LOOP instructions use the count register.
RDX(Data):
Also addressed as EDX, DX, DH, DL. It is a general purpose register which holds a part
of the result after a multiplication or part of the dividend before a division.
RBP(Base Pointer):
Also addressed as EBP OR BP. This points to a memory location to transfer the data.
RDI(Destination Index):
Also addressed as EDI or DI. If often addresses string destination data for the string
instructions.
RSI(Source Index):
Also addressed as ESI or SI. This often addresses the source string data for the string
instructions. RDI and RSI also work as general purpose registers.
R8 through R15:
These are present only in Pentium 4 and core 2 when 64-bit extensions are enabled.
These registers can be addressed as 64, 32, 16/8 bit sizes and are general purpose
registers. The 8-bit portion is the right most 8-bit only. Bits 8-15 cannot be directly
addressed as a byte.
Special-Purpose Registers:
Are RIP, RSP and EFLAGS.
RIP(Instruction Pointer):
This contains the address of the next instruction present in the code segment. In the
8086 microprocessor this register is called IP and is 16 bits, which operates in the real
mode. In the 80386 and above it is EIP, 32-bits long and operates in protected mode.
RSP(Stack Pointer):
Is used to address the stack memory area. The data is stored into the stack memory
through this stack pointer. It is used as SP for a 16-bit register and ESP for a 32-bit
register.
RFLAGS:
Indicate the condition or status of the microprocessor and also control its operation.

JSR, CSE, AMCEC 15
The bit details of the RFLAG is shown below:
The 8086-80286 contain a FLAG register of 16 bits and 80386 and above contain EFLAG
register of 32-bits. The 64-bit RFLAGS have the EFLAG register without any changes in
the 64-bit version.
The right most five flag bits and the overflow flag will change after many arithmetic and
logic instructions execute. But they do not change for data transfer or program control
operations.
C (Carry):
Holds the carry after addition or the borrow after subtraction. It is also used to indicate
error condition by some programs.
P(Parity);
Parity is the count of ones in a number. It is referred as even or odd parity. Odd parity is
indicated by logic 0 and even parity is indicated by logic 1.
A (Auxiliary Carry):
Holds the carry after addition or borrow after subtraction between the bit positions 3 and
4 of the result. This flag bit is tested by the instructions DAA and DAS to adjust the value
of AL after a BCD addition or subtraction.
Z(Zero):
Is used to indicate if the result of an arithmetic or logic operation is zero. Z=1 if the result
is 0 and Z=0 if the result is not zero.
i.e. Z=1 for R=0 and Z=0, R≠0 R-result.
S(Sign):
Sign flag holds the arithmetic sign of the result after arithmetic or logic instruction is
executed.
S=1 if the sign bit is negative(MSB or left most bit).
S=0 if sign bit is positive or cleared.
T(trap):
Trap flag provides step-by-step debugging feature. If the T flag is 1, it is enabled and
the microprocessor interrupts the flow of the program as indicated by the debug
registers and control registers. If T=0 trapping is disabled.
I(Interrupt):
This interrupt flag controls the operation of the INTR(interrupt request) input pin. If I=1,
INTR is enabled.
If I=0, INTR pin is disabled. This flag bit can enabled or disabled by the instructions STI-
Set I-flag and CLI- Clear I-flag.

JSR, CSE, AMCEC 16
D(Direction):
Direction flag either increments or decrements the DI, SI registers during string
instructions.
If D=1, the registers are automatically decremented.
If D=0, the registers are automatically incremented.
The D flag can be set with the instruction STD- Set direction and CLI- Clear direction.
O(Overflow): Overflow occurs when the signed numbers area added/subtracted. If O=1,
it indicates an overflow, i.e. the result has exceeded the capacity of the data size. This is
not used for unsigned operations.
IOPL(I/O Privilege Level):
Is used to select the privilege level for I/O devices in the protected mode operation. If the
IOPL is higher than the I/O executes without disturbance. If the IOPL is lower than the
current privilege level, then an interrupt occurs and suspends the execution.
IOPL of 00 is the highest or most trusted.
IOPL of 11 is the lowest or least trusted.
NT(Nested Task):
This flag tells that the current task is nested within another task in the protected mode
operation. NT=1, when the task is nested.
RF(Resume):
This flag is used with debugging to control the resumption of execution after the next
instruction.
VM(Virtual Mode):
This flag selects virtual mode operation in a protected mode system. Virtual mode allows
multiple DOS memory partitions.
AC(Alignment Check):
This flag is set if a word or double word is addressed on a non-word or non-double word
boundary. Present only in 80486Sx.
VIF(Virtual Interrupt):
Is a copy of interrupt flag available in the Pentium-Pentium 4 microprocessor.
VIP(Virtual Interrupt Pending):
Provides information of a virtual mode interrupt for the Pentium-Pentium 4
microprocessors. Used in multitasking environments.
ID(Identifications):
This flag indicates that the Pentium-P4 microprocessor support the CPUID instruction.
CPUID provides the information about the Pentium microprocessor like its version
number and manufacturer.
Segment Registers:
These registers generate memory addresses when combined with other registers.
Depending on the version of the microprocessor there will be either 4 or 6 segment
registers. Segment registers operate in a different manner in real mode when compared
to protected mode.
CS(Code Segment):
Holds the code i.e. programs and procedure used by the µp.
CS defines the starting address of the memory location which is holding the code.
In real mode operation CS defines the beginning of a 64KB memory operation.
In protected mode it selects a descriptor which describes the starting address and length
of a memory section that is holding the code.

JSR, CSE, AMCEC 17
CS is 64KB in 8086/88-80286 and 4GB in 80386 and above when it is operating in
protected mode.
DS(Data Segment):
Holds most of the data used by a program. The data in the data segment are accessed by
an offset address or through the contents of the other registers which hold the offset
address.
Data segment- 64KB in 8086-80286, 4GB in 80386 and above.
ES(Extra Segment):
Is an additional data segment which is used by some string instructions to hold the
destination data.
SS(Stack Segment):
The portion of memory which is used for stack is called stack segment.
The starting/entry point of a stack segment and the stack pointer registers.
The BP also addresses the data within the stack segment.
FS and GS:
These are supplemented segment registers available in 80386- to core 2 µp’s.
These allow 2 additional memory segments for access by programs.
Windows uses these segments for internal operation.
Real Mode Memory Addressing:
Real mode operation allows the µp to address only the first 1MB of the memory in any
version of the µp. The first 1MB of the memory is called the real memory or conventional
memory or DOS memory system. 8086 and 8088 operate only in real mode while all
others operate either in real mode or protected mode.
The P4 and core 2 µp’s cannot operate in real mode when they are using the 64-bit
processing mode. Windows does not use the real mode. For the µp’s 80286 and above an
application software is written for the 8086/88 [1MB] to function in real mode.
Segments and Offsets:
Segment Address:
Is present in one of the segment registers. It defines the starting address of any 64KB
memory segment.
Offset Address:
Can select any portion/location within this 64KB memory segment.
All segments in the real mode will be of 64KB size.
The segment and offset address are added to access a particular memory location in the
real mode. All real mode memory addresses must have a segment address and an offset
address.
Ex: Memory segment starts at 10000H and ends at 1FFFFH -which is of 64KB length.
To select a memory location 1F000H, add segment address and offset address.
i.e. Start of segment address 10000H
+ offset address(displacement) F000H
1F000H
Hence it shows that offset or displacement is the distance above the starting point of a
segment.

JSR, CSE, AMCEC 18
Diagram showing the addresses
As shown in the above figure, the segment register has 1000h, but is pointing to a starting
segment location of 10000H.
This is because in real mode each segment register internally appends with 0H to the
right most end. This forms a 20-bit memory address to access within the first 1MB of
memory. Ex:
Segment register
has
Actual starting
address
Ending address
2000H 20000H 2FFFFH[SA+FFFF]
1400H 14000H 23FFFH
2104H 21040H 3103FH
Real mode segments can begin only at a 16-byte boundary in the memory system [16-
byte boundary is also called a paragraph]. This is done since segment registers are
internally appending 0H.
Since any real memory segment is of 64K in length, the ending address is found by adding
FFFFH with the starting address.
i.e. SA-Starting Address 14000H
+ 64K i.e. FFFFH
23FFFH
To address a memory location, add the offset address to the start of the segment
address, i.e. if the segment address is 1500H and offset address is 3000H then
due to the internal appending
segment address is 15000H
+ offset address is 3000H
Actual address location 18000H
The segment and offset address are also written as 1500 : 3000
(seg.addr.) : (offset addr.)
Default Segment and Offset Registers:
A set of rules have to be applied to segments during memory addressing.
These rules apply for both real mode and protected mode and they define the segment
register and offset address combination.
Ex: code segment is always used with the Instruction Pointer to address the next
instruction, i.e. CS:IP or CS:EIP.

JSR, CSE, AMCEC 19
CS-> defines thaw start of the code segment.
IP->locates the next instruction within the code segment.
If CS=1400H and IP/EIP=1200H, the µp fetches the next instruction from the memory
location 14000H+1200H=15200H.
SS:SP or SS:BP is one more default combination.
SS-> refers the stack segment address.
SP->refers the actual location of the data within SS.
Ex: if SS=3000H and BP=1500H, the µp addresses the location 315000H for the stack
segment memory location.
Segment Offset Special Purpose
CS IP Instruction Address.
DS DI, SI, BX or 8/16 bit
no.
Data Address.
SS SP or BP Stack Address.
ES DI for string
instructions
String Destination
Address.
Segment and Offset Addressing Scheme Allows Relocation:
A relatable program is one that can be placed into any area of memory and executed
without any change. Since memory is addressed within a segment by an offset address,
the memory segment can be moved to any position/place in the memory system without
changing any of the offset addresses. This is done by moving the entire program as a
block to a new area and then changing only the contents of the segment registers.
Ex: If an instruction is 4 bytes above the start of the segment its offset address is 4. If
the entire program is moved to a new area of memory, the offset address of 4 still points
to 4 bytes above the start of the segment. Only the contents of the segment register must
be changed with the new memory area.

JSR, CSE, AMCEC 20
CHAPTER - 2
ADDRESSING MODES
INTRODUCTION TO PROTECTED MODE MEMORY ADDRESSING:
Protected mode memory addressing helps to access the data and programs stored in the
extended memory and the first 1MByte of memory (Real Memory).
To address data and programs in the extended memory, the offset is also used along with
the segment address. But in protected mode the segment address is replaced by a
selector. A selector selects a descriptor table. This descriptor gives the memory segment’s
location, length and access rights. The protected mode instructions are similar to real
mode instructions.
The modes are different only in the way the segment register is interpreted by the
microprocessor to access the memory segment. Also in 80386 and above the offset
address can be 32-bit number instead of 16-bit number.
Selectors and Descriptors:
The selector present in the segment register selects any one of 8192 descriptors from one
of the two tables of descriptors.
The descriptor describes the location, length and access rights of the segment of memory.
The two descriptor tables used with the segment registers are:
1. Global descriptors.
2. Local descriptors.
Global Descriptors:
Contain segment definitions that apply to all programs. Also called as system descriptor.
Local Descriptors:
Are unique to an application and hence also called as application descriptor.
Each descriptor table contains 8192 descriptors. So totally 16,384 total descriptors are
available to an application at any time i.e. 16,384 memory segments can be described for
each application.
The Descriptors for 80286, 80386 and P4 are shown below:
The descriptors for 80286 and 80386-core 2 differ slightly, but the 80286 descriptor is
upward compatible.
The Base Address portion gives the starting location of the memory segment.

JSR, CSE, AMCEC 21
The Segment Limit has the last offset address of that segment.
Ex: If segment begins at F00000H and ends at location F000FFH, the base address is
F00000H and the limit is FFH. 80286 has a 16-bit limit while 80386 through P4 have a
20-bit limit i.e. 80286 can access memory segments between 1 and 64Kbytes in length
and 80386 and above can access memory segments between 1 and 1Mbyte or 4K and 4G
bytes in length.
G-bit:
Found in 80386 through P4 is the granularity bit. If G=0, the limit specifies a segment
limit of 00000H to FFFFFH.
If G=1, the value of the limit is multiplied by 4Kbytes i.e. the limit is appended with FFFH.
Hence the actual limit now varies from 00000FFFH to FFFFFFFFH, if G=1.
In the 64-bit descriptor, the L-bit is used to select the 64-bit addresses in P4 or core 2
i.e. if L=1 it selects 64-bit extensions and if L=0 it selects 32-bit compatibility mode. In
64-bit protected mode there is no limit or base address, it only has the access rights byte
and the control bits.
Ex: 1.Base=start=10000000H
G=0
End=base + limit= 10000000H + 1FFH = 100001FFH.
2.Base=start=10000000H
G=1 (append FFFH to limit)
End =base + limit= 10000000H + 001FFFFFH = 101FFFFFH.
AV bit:
In 80386 and above is by the OS to indicate if the segment or not available. If
AV=1=Available, if AV=0=not-available.
D bit:
Indicate the size of instructions in the register memory. D bit is present in 80386 to core
2.
If D=0, the instructions use 16-bit offset and 16-bit registers by default. This mode is
also called as DOS mode.
If D=1, the instructions are 32-bit and all offset addresses and registers are also 32-bit
by default.
The Access Rights byte controls access to the protected mode segment. It describes the
functions of the segment and also allows to control the segment. AV is present in 80386
and above microprocessors and used by some OS to indicate that segment is available if
AV=1, and the segment is not available if AV=0.
Segment Register:
The descriptors are chosen by the segment register from the descriptor table.

JSR, CSE, AMCEC 22
Contents of segment register in procted mode operation is as shown below:
DS register used to select a descriptor from the global descriptor table:
DS contains 0008H, this accesses the descriptor no.1 from the global descriptor table
with a privilege level of 00. The descriptor 1 , has the address of the segment with a base
address and its limit.
Program Invisible Registers:
The global descriptor table and the local descriptor table are present in the memory. To
access and specify these tables the 80286-core 2 has program invisible registers.
Because the software cannot address these program invisible registers directly, they are
called invisible.

JSR, CSE, AMCEC 23
GDTR: Global Descriptor Table Register
IDTR: Interrupt Descriptor Table Register
LDTR: Local Descriptor Table Register
TR: Task Register
Each segment register contains a program invisible portion used in the protected mode.
These program invisible portions of the segment registers are loaded with the base
address, limit and access rights each time the number in the segment register is changed.
When a new segment number is placed in the segment register, the microprocessor will
access a descriptor table and load the descriptor into the program invisible portion of the
segment register, then using this, the memory segment is accessed until the number is
changed again. Thus the microprocessor can repeatedly access a memory segment
without referring to the descriptor table. Hence these program invisible registers are
termed as cache.
GDTR and IDTR hold the base the base address of the descriptor table and its limit. The
location of local descriptor table is selected from the global descriptor table through one
of the global descriptors. The LDTR is loaded with a selector to access the LDT, then this
selector goes to GDT and loads the address, limit and access rights of the LDT into the
cache portion of the LDTR.
TR-task register holds a selector to access a descriptor that defines a task. Task is a
procedure or application program and its descriptor is stored in the GDT.
MEMORY PAGING: [80386 and above]
This mechanism allows any physical memory location to be assigned to any linear
address. Linear address is the address generated by a program. Physical address is the
actual memory location accessed by a program.
The memory paging unit invisibly translate the linear address to any physical address.
This allows an application to be relocated through paging mechanism and also allows
memory to be placed into areas where no memory exists.
Paging Registers:

JSR, CSE, AMCEC 24
Memory paging and paging to the hard disk drive is done through the paging unit.
This paging unit is controlled by the contents of the microprocessor’s control register.
The Control Register structure of the Microprocessor
The register CR0 and CR3 are important to the paging unit. The left most bit PG- selects
paging when it is 1.
And if PG=0, the linear address generated by the program itself will be the physical
address which is used to access the memory. If PG=1, the linear address is converted to
physical address through paging. Paging functions in both real and protected modes.
CR3 has the page directory base or root address and the PCD and PWT bits. Etc
The PCD and PWT bits control the operation of PCD and PWT pins on the microprocessor.
If PCD bit is set (1), the PCD pin becomes logic one during bus cycles that are not paged.
This allows the external hardware to control the level 2 cache memory. Level-2 cache
memory is an internal high-speed memory and acts as a buffer between the
microprocessor and the main DRAM memory.
PWT bit appears on the PWT pin during bus cycles that are not paged to control the write-
through cache in the system.
The page directory base address locates the directory for the page translation unit. The
page directory entry address is a page table contains 1024 entries.
P-Present
W-Writable
U-User defined
PWT-Write-through
PCD-Cache disable
A-Accessed
D-Dirty (0 in page directory)
The linear address i.e. generated by the software, is divided into 3 sections to access the
page directory entry, page table entry and memory page offset address.

JSR, CSE, AMCEC 25
The Paging Mechanism in 80386 – to - Core2 Microprocessors
The Paging Directory and Page Table:
The paging mechanism figure shows the page directory, a few page tables and some
memory pages. A system contains only one page directory. This page directory contains
1024 double word addresses that locate up to 1024 page tables. Each entry in the page
table addresses 4KB of physical memory.
FLAT MODE MEMORY: The 64-bit Flat mode memory model
Pentium based computer have a memory
system which uses a flat mode memory system.
In FLAT Memory Mode there is no
segmentation. The address of the first byte in
the memory is at 0000000000H and the last
location is at FFFFFFFFFFH (address is 40
bits).
The flat model does not use a segment register
to address a location in the memory.
Here the CS segment register is used to select
a descriptor from the descriptor table which
defines the access rights of only a code
segment.
The flat mode does not select the memory
address of a segment using the base and limit
in the descriptor. The offset address is the actual physical address in 64-bit mode. This
form of addressing is easy to understand but offers protection to the system, through the
hardware.

JSR, CSE, AMCEC 26
DATA ADDRESSING MODES DEFINITIONS
Opcode tells the microprocessor which operation to operation to perform. In any
instruction the source is to the right and the destination is to the left, next to the opcode.
The direction of flow is from right to left.
A comma separates the destination from the source in any instruction.
Data can be moved from memory-to-memory using the only MOV instruction. MOV is
used to move data between registers and memory.
Example:
1. Register Addressing:
Transfers a copy of a byte or word from the source register or contents of a memory
location to the destination register/memory location.
Ex:
MOV CX, DX - copies the word-sized contents of DX to CX.
MOV ECX, EDX- copies a double word-sized contents of EDX to ECX.
2. Immediate Addressing:
Transfers the source i.e. an immediate byte, word, double word of data into the
destination register or memory location.
Ex:
MOV AL, 22H – copies 22H into AL.
MOV BX, 22446688H- copies 22446688H into EBX.
Immediate MOV CH, 4DH
3. Direct Addressing:
Moves a byte or word between memory location and a register.
Ex:
MOV CX, ABC – copies the contents of ABC- memory location into the CX register.
MOV ESI, ABC – copies double word-size data from ABC location is copied into ESI.
4. Register Indirect Addressing:

JSR, CSE, AMCEC 27
Transfers a byte or word between a register and a memory location addressed by an index
or base register. The index and base registers are BP, BX, DI and SI.
Ex:
MOV AX, [BX] – copies the data from the data segment offset address indexed by BX into
the register AX.
5. Base-Plus-Index Addressing:
Transfers a byte/word between a register and the memory location addressed by a base
register (BP/BX) plus an index register(DI/SI).
Ex:
MOV [BX+DI], CL – copies the data in CL register to the data segment memory location
addressed by BX+DI.
Base+ Index: MOV [BX+SI], BP
6. Register Relative Addressing:
Moves data between a register and the memory location addressed by an index/base
register plus a displacement.
Ex:
MOV AX, [BX+4]- copies the content of data segment address given by BX+4 into the AX
register.
7. Base Relative-Plus-Index Addressing:
Transfer data between a register and the memory location addressed by a base and index
register plus a displacement.
Ex:
MOV AX, [BX+DI+4] - copies the data from the memory location given by adding BX, DI
and 4 into the AX register.
8. Scaled-Index Addressing:

JSR, CSE, AMCEC 28
This is available only in 80386 to P4 microprocessors. Here the second register of a pair
of registers is modified by the scale factor of 2x, 4x or 8x to generate the operand memory
address.
Ex:
MOV EDX, [EAX+4xEBX] - loads EDX with the contents of the data segment memory
location addressed by EAX+ 4 times EBX.
Scaling factor access to word (2x), double word (4x) or quad word (8x) memory array data.
9. RIP Relative Addressing:
Is available only for 64-bit extensions on the P4 to core 2 microprocessors.
This mode allows access to any location in the memory system by adding a 32-bit
displacement to the 64-bit contents of the 64-bit instruction pointer.
Ex: If RIP=1000000000H and a 32-bit displacement is 300H, then the location accessed
is 1000000300H.
Data Addressing Modes explanation:
1) Register Addressing:
Is for data addressing through registers.
The 8-bit registers are AH, AL, BH, BL, CH, CL, DH and DL.
The 16-bit registers are AX, BX, CX, DX, SP, BP, SI and DI.
In 80386 and above 32-bit registers are EAX, EBX, ECX, EDX, ESP, EBP, ESI and EDI.
In Pentiums, 64-bit registers are RAX, RBX, RCX, RDX, RSP, RBP, RDI, RSI and R8
through R15.
While addressing:
 Do not mix an 8-bit register with a 16-bit register, an 8-bit register with 32-bit
register or a 16-bit register with a 32-bit register.
1. Never mix registers of different sizes. Ex: MOV BL,DX.
2. Never MOV data between two segments. Ex: MOV ES,DS.
3. Never use code segment register as destination register. Ex: MOV CS, AX.
Ex: For register addressed instructions:
MOV AL, BL - copies contents of BL to Al.
MOV CH, CL- copies contents of CL to CH.
MOV R8B, CL – copies CL to byte portion of R8 in 64-bit mode.
MOV R8B, CH – not allowed.
MOV AX, CX – copies CX to AX.
MOV SP, BP – copies BP to SP.
MOV BP, R10W – copies R10 into BP (64-bit mode).
MOV ES, DS – not allowed (segment-to-segment).
MOV BL, DX – not allowed (mixed sizes).
MOV CS, AX – not allowed (code segment should not be the destination register.)
Example instructions:
MOV AX, BX - copies contents of BX to AX.

JSR, CSE, AMCEC 29
MOV EBX, EAX - copies contents of EBX to EAX.
MOV AX, CS - copies contents of CS to DS (two steps).
MOV CS, AX - copies contents of CS (causes problems).
2) Immediate Addressing:
Immediate implies that the data immediately follows the register. Immediate data is a
constant data but the data transferred from a register or memory location is a variable
data.
Ex: MOV EAX, 13456H.
This MOV instruction copies the data 13456H into the register EAX.
The letter H appends hexadecimal data. If an hexadecimal data begins with an alphabet,
then the assembler needs this data to start with ‘0’ (zero).
Ex: To give hexadecimal data F2, it should be given as 0F2H i.e.
MOV AH, 0F2H.
An ASCII-coded can be represented in the immediate form if the ASCII data are enclosed
in apostrophes.
Ex: MOV BH, ‘A’ - moves the ASCII code of ‘A’[41H] to BH.
Note: Use the apostrophe (‘ ‘) and not the single quote (‘).
Example Program:
Label 1 Opcode Operand Comment
DATA1 DB 23H Define DATA1 as a byte of 23H.
DATA2 DW 1000H Define DATA2 as a word of 1000H.
START: MOV
MOV
MOV
AL, BL
BH,AL
CX,200
Copy BL into AL.
Copy AL into BH.
Copy 200 into CX.
Label: Field stores a symbolic name for the memory location. All labels must start with
an alphabet or any of special characters @, $, - or ? The length of label can vary between
1 to 35 characters. A label is used in a program to identify the name of a memory location
for storing data. The next field is the opcode field. Opcode field is designed to hold the
instruction or opcode. Ex: MOV is an opcode.
The next field is the operand field. It contains the information which is used by the
opcode. Ex: MOV AL, BL – here AL, BL are the operands.
The last field is the comment field. This has a comment about an instruction or a group
of instructions. A comment always begins with a semicolon (;).
Program showing various immediate instructions.
.MODEL TINY – choose single segment model.
.CODE – start of code segment.
.START UP – start of program.
MOV AX, 0 – place 0000H into AX.
MOV BX, 0 – place 0000H into BX.
MOV CX, o – place 0000H into CX.
MOV SI, AX – copy AX into SI.
MOV DI, AX – copies AX into DI.
MOV BP, AX – copies AX into BP.
.EXIT - -exit to DOS.
END – end of program.
3) Direct Data Addressing:

JSR, CSE, AMCEC 30
Is applied to many instructions in a program. There are two basic forms of direct data
addressing.
1. Direct Addressing.
Direct Addressing applies to a MOV instruction between a memory location and Al, AX
or EAX.
2. Displacement Addressing.
Displacement Addressing applies to any instruction. In both the cases, the address is
formed by adding the displacement to the default data segment address or any other
segment address.
In 64-bit operation, direct–addressing instructions are with a 64-bit linear address to
access any memory location.
Direct Addressing:
Direct addressing with a MOV instruction transfers data between a memory location
within a data segment and the Al, AX or EAX register.
Ex:
MOV AL, DATA – loads AL from the data segment memory location DATA (1234H). DATA
is a symbolic memory location, while 1234H is the actual location. This instruction is
also written as MOV AL, [1234H].
[1234H] is the actual or absolute memory location, which is not allowed by all assembler
programs. This may be written as MOV AL, DS:[1234H] in some assemblers, to show that
the address is in the data segment.
The operation of the MOV AL,[1234H] instruction when DS=1000H
The effective address is got by adding
Offset address = 1234H
+ 10x data segment address = 10000H
11234H
Ex: Direct addressed instructions. These are always 3-byte long instructions.
MOV AL, NUM 8-bits copies the content of data segment memory
location NUM into AL.
MOV AX, RES 16-bits from memory location (word contents) RES to AX.
MOV EAX, MESS 32-bits copies double word contents from memory
location MESS to EAX.
MOV NEWS, AL 8-bits copies AL into byte memory location NEWS.
MOV ES: [2000H], AL 8-bits copies AL into extra segment memory at offset
address 2000H.
Displacement Addressing:

JSR, CSE, AMCEC 31
This is similar to direct addressing except that the instruction is 4 bytes wide instead of
3 bytes. In 80386 to P4, this instruction can be 7 bytes wide if both 32-bit register and a
32-bit displacement is more flexible.
Ex: MOV AL, DS: [1234H] 0000 A0 1234 R -3byte machine code.
MOV CL, DS: [1234H] 0003 BA 06 1234 R-4 byte machine code.
Ex: MOV instructions using displacement form of direct addressing.
MOV CH, FOG 8-bits Copies the byte contents of DS memory FOG to
CH.
MOV CH, DS:[1000H] 8-bits Copies the contents of DS memory offset address
1000H to CH.
MOV ES, DATA2 16-bits Copies word contents of DS memory DATA2 to ES.
MOV DATA3, BP 16-bits Copies BP into DS memory DATA3.
MOV DATA4, EAX 32-bits Copies EAX into DS memory DATA1.
.MODEL SMALL – choose small model.
.DATA - start data segment.
DATA1 DB 10H - put 10H into DATA1.
DATA2 DB 0 - put 0 into DATA2.
DATA3 DW 0 - put 0 into DATA3.
DATA4 DW 0AAAAH – put AAAAH in DATA4.
.CODE - start code segment.
.STARTUP - start program.
MOV AL, DATA1 – copy DATA1 to AL.
MOV AH, DATA2 – copy DATA2 to AH.
MOV DATA3, AX – copy AX to DATA3.
MOV BX, DATA4 – copy DATA4 to BX.
.EXIT - exit to DOS.
END – end program listing.
.MODEL TINY – directs the assembler to assemble the program into a single
code segment.
.MODEL SMALL – allows one data segment and one code segment to be
present in the program.
4) Register Indirect Addressing:
Allows data to be addressed at any memory location through an offset address stored in
any of these registers BP, BX, DI and SI.
Ex: MOV AX, [BX].
With BX=1000H when the microprocessor is operating in real mode and if DS=0100H
BX= 1000H -> offset address.
+ DS=0100H -> data segment address
Effective address = offset address 1000H
+ 10 times DS 1000H
2000H
Effective address = 2000H
The symbol [ ] denotes indirect addressing in assembly language. In 80386 and above
microprocessors register indirect addressing is done using BP, BX, DI and SI except for
ESP.
Data segment is used by default with register indirect addressing.

JSR, CSE, AMCEC 32
Also for addressing modes which uses BX, DI or SI to address memory, the data segment
is used by default. If the BP register address memory, the stack memory is used by
default. For 80386 and above, EBP addresses the stack memory and EAX, EBX, ECX,
EDX, EDI and ESI address the memory in data segment by default.
The size of the data has to be specified in some cases. The special assembler directives:
BYTE PTR, WORD PTR, DWORD PTR or QWORD PTR specify the size. These directives
indicate the size of the memory data addressed by the memory pointer (PTR).
The operation of the MOV AX,[BX] instruction when BX=1000H and DS=0100H, after
memory contents are transferred to AX
Ex: MOV AL, [DI] ; is a byte-sized move instructions.
MOV [DI], 10H ; does it address a byte, word, double word or Qword sized
;memory location. The assembler can’t determine the size of 10H.
MOV BYTEPTR[DI], 10H ; clearly indicates the DI addresses a byte sized
; memory location.
These directives i.e. BYTEPTR, WORDPTR, DWORDPTR and QWORDPTR are used only
with a pointer or index register for register indirect addressing and immediate addressing.
Indirect addressing can be used to refer data stored in the form of a table in the memory.
For addressing tabular data the BX register is used to hold the staring address of the
table and at the next step register CX is initialized with a counter. Then use the Register
indirect addressing to store the data into each location of the table.

JSR, CSE, AMCEC 33
An array-TABLE containing 50 bytes that are indirectly addressed through register BX
Example Program:
To create a table containing 50 samples taken from the memory location 0000:046C
which has a counter in DOS.
.MODEL SMALL
.DATA
DATAS DW 50 DUP(?) – setup array of 50 words
.CODE
MOV AX, 0 – loads AX with o
MOV ES, AX – ES has 0000
MOV BX, OFFSET DATAS – put offset address of DATAS into BX
MOV CX, 50 - load counter with 50
AGAIN:
MOV AX, ES:[046CH] - get clock value(location 0000:046C contains a counter in DOS)
MOV [BX], AX - save clock value in DATAS
INC BX
INC BX - increment BX to next element
LOOP AGAIN - repeat till CX=0
END - end program
Once the counter and pointer are initialized, a repeat until CX=0 loop executes. Data is
read from extra segment memory location 46CH and stored in the address pointed by BX
by incrementing it each time. The LOOP instruction decrements like CX till CX is zero. If
CX is zero, no jump occurs.
5) Base-Plus-Index Addressing:
This is similar to indirect addressing. In 8086 and 80286 this type of addressing uses
one base register (BP or BX) and one index register (DI or SI) to indirectly address
memory.
Base register holds the starting location of an array in the memory and index register
holds the relative position of an element in the array.
In 80386 and above any two 32-bit extended registers can be combined except ESP.
Ex: MOV DL, [EAX+EBX].
If EBP is used the stack segment will be used instead of data segment.
Locating Data with Base-Plus-Index Addressing:
MOV DX, [BX+DI]
BX=1000H, DI=0010H AND DS=0100H
Therefore, EA= 02010H.
So this instruction copies a word from the location 02010H into the DX register.

JSR, CSE, AMCEC 34
An example showing how the base-plus-index addressing mode functions for the MOV
DX,[BX+DI] instruction
In Intel ASM assembler the instruction MOV DX, [BX+DI] has to be written in the form
MOV DX, [BX][DI].
Ex:
MOV CX, [BX+DI] 16-bits copies word data from EAX of DS to CX.
MOV CH, [BP+SI] 8-bits copies byte data from OS, EA to CH.
MOV [BP+DI], AH 8-bits copies byte data from AH to the DS, EA.
Locating Array Data Using Base-Plus-Index Addressing:
Base-Plus-Index Addressing is mainly used to address elements in a memory array. To
access the elements stored in the form of array in the data segment at the memory
location TABLE, load the BX register with the staring address of the array and the DI
register with the element number to be accessed.
An example of the base-plus-index addressing mode. Here an element(in DI) of an ARRAY(in
BX) is addressed
Example Program:
To move the elements in 10H to element 20H in the array named as USN.
.MODEL SMALL
.DATA
USN DB 16 DUP(?) - setup array of 16 bytes.

JSR, CSE, AMCEC 35
DB 29H - element 10H( 17th element).
DB 20 DUP(?) - setup 20 elements of one byte each.
.CODE - start code segment.
.STARTUP
MOV BX, OFFSET USN - copy starting address of the array USN to BX.
MOV DI, 10H - copy 10H into DI.
MOV AL, [BX+DI] - add contents of BX and DI to get the EA and copy of content of
EA to AL.
MOV DI, 20H - load DI with 20H.
MOV [BX+DI], AL - load the EA with the contents of AL.
.EXIT - exit to DOS.
END - end program.
6) Register Relative Addressing:
This is similar to Base-plus-index addressing and displacement addressing.
In register relative addressing the data present in a memory segment is addressed by
adding the displacement to the contents of a base or an index register i.e. BP, BX, DI or
SI.
Ex: MOV AX, [BX+1000H].
The operation of the MOV AX,[BX+1000H] instruction, when BX=0100H and DS=0200H
In this example let BX=0100H and DS=0200H
BX=0100
Displacement/offset = 1000
= 1100
+ DS X 10H = 2000
Effective address = 3100H
Examples for register relative addressing:
MOV AX, [DI+100H] 16-
bits
Copies contents of EA in DS into AX.
MOV ARRAY[SI], BL 8-bits Copies BL into the EA given by ARRAY+SI.
MOV LIST[SI+2], CL 8-bits Copies CL in the EA given by LIST+SI+2.

JSR, CSE, AMCEC 36
MOV ARRAY[EBX], EAX 32-
bits
Copies EAX into the EA of RRAY+EBX.
Addressing Array Data with Register Relative:
Array data can be addressed with register relative addressing as done in base-plus-index
addressing.
Register Relative addressing used to address an element of ARRAY. The displacement
addresses the start of ARRAY, and DI accesses an element.
Register relative addressing used to address an element of ARRAY.
The displacement of the ARRAY is added to index register DI to refer any element in the
array. Ex: MOV AL, ARRAY[DI].
7) Base Relative-Plus-Index Addressing:
This addressing mode is similar to base-plus-index addressing but it adds a displacement
with the base register and an index register to form the memory address. This addressing
mode often addresses a two-dimensional array of memory data.
An example of base relative-plus-index addressing using a MOV AX,[BX+SI+100H]
instruction.
Ex:
MOV DH, [BX+DI +20H] 8-bits
MOV AX, FILE[BX+DI] 16-bits
MOV LIST[BP+SI+4], DH 8-bits

JSR, CSE, AMCEC 37
Addressing Data with Base Relative-Plus-Index:
This addressing is the least used addressing mode as it is too complex for frequent use
in programming.
For the instruction MOV AX, [BX+SI+100H]
If BX=0020H, SI=0100H and DS=1000H
Effective address
BX=0020H
SI=0010H
Displacement=0100H
DSx10=10000H
EA =10130H
Addressing Arrays with Base Relative-Plus-Index:
If a file with many records exists in memory, and each record contains many elements
then this addressing mode is used to access elements then this addressing mode is used
to access elements of each record.
This is done with displacement addressing the file, the base register addresses a record
and the index register addresses an element of a record.
Ex:
MOV AL, FILE[B+DI].
Base Relative-plus-index addressing used to access a FILE that contains multiple records
(REC)

JSR, CSE, AMCEC 38
8) Scaled-Index Addressing:
This data addressing mode is unique to the 80386 through the core2 microprocessors.
This addressing uses two 32-bit registers i.e. a base register and an index register, to
access the memory. The second register i.e. the index register is multiplied by a scaling
factor. The scaling factor can be 2x, 4x or 8x. Scaling factor of 2x is used to address word-
sized memory arrays, 4x addresses double word-sized memory arrays and a scaling factor
of 8x is used to address Quad word-sized memory arrays.
Ex:
MOV AX, [EDI+2x ECX]
This instruction uses a scaling factor 0f 2x which multiplies the contents of ECX by 2
before adding it to the EDI register to from the memory address.
MOV EAX, [EBX+4x ECX] 32-bits
MOV [EAX+2x EDI+100H] 16-bits
MOV AL, [EBP+2xEDI+2] 8-bits
9) RIP Relative Addressing:
This addressing uses the 64-bit instruction pointer register in the 64-bit mode to address
a linear location in the flat memory model.
As of now only Intel produces a complier with an inline assembler for 64 bit code. Except
this no other assemblers allow to use this mode of addressing.
Data Structures: A data structure specifies how information is used in a memory
array. This is useful for applications that use arrays. Data structure is a template for
data. The start of a data structure is identified with the STRUC assembler directive, and
end is identified with the ENDS statement.
Ex: Define the INFO data structure:
INFO STRUC
NAMES DB 32 dup(?)
STREET DB 32 dup(?)
CITY DB 16 dup(?)
STATE DB 2 dup(?)
ZIP DB 5 dup(?)
INFO ENDS
NAME1 INFO<’AMC Engg college’, ‘Bannerghatta Road’, ‘Bangalore’, ‘KA’, ‘56008’>
NAME2 INFO<’T.JOHN Engg college’, Nice Road’, ‘Bangalore’, ‘KA’, ‘67004’
After using the Data Structure.
This data structure defines five fields of information, with different sizes. When data is
addressed in a structure, the structure name and field name can be used to select a field
from the structure.
Ex:
- The operand NAME2.STREET, selects the STREET field in the NAME2 record.
- The operand NAME1. CITY, selects the CITY field in the NAME1 record.

JSR, CSE, AMCEC 39
PROGRAM MEMORY-ADDRESSING MODES:
The JMP(jump) and CALL instructions use this program memory addressing mode in 3
different forms as – 1.Direct 2. Relative 3.Indirect.
1. Direct Program Memory Addressing:
The instruction for this addressing mode store the address with the opcode.
Ex: JMP[10000H] - shows the direct intersegment JUMP instruction.
This tells the assembler to jump to the memory location 10000H for the next instruction.
Intersegment Jump: (Intersegment jump is jump between different segments)
Is a jump to any to the memory location/segment within the entire memory system.
Direct jump is also called a far jump as it can jump to any memory location for the next
instruction.
CALL instruction also uses direct program addressing for intersegment or far CALLS. The
name of memory address i.e. a label, is referred in a CALL or JMP instruction.
Only CALL and JMP instructions use the direct program memory addressing. Label i.e.
name of a memory address refers to the location that is called or jumped instead of the
actual numeric address.
Ex: JMP L1 - skips to the instruction with label L1.
2. Relative Program Memory Addressing:
Relative means “relative to the instruction pointer (IP)”. This jump is an Intrasegment
Jump.
(Intrasegment-is a jump within the same segment)
Ex: JMP[2] – instruction skips over the 2 bytes of memory that follow JMP instruction.
This instruction is a 1-byte instruction, with 1-byte displacement.
1 byte displacement is used in short jumps/call.
If the displacement is 2 bytes, it is a near jump/call.
Both these are intra segment jumps.
Intra segment jump is a jump anywhere within the current code segment.
In 80386 and above the displacement can be a 32-bit value, which allows the use of
relative addressing to any location within their 4GB code segments.
Relative JMP and CALL instructions contain a 8-bits(1byte) or 16-bits(2bytes) of signed
displacement which allows a forward or reverse memory reference.
3. Indirect Program Memory Addressing:
Many forms of indirect program memory addressing for the JMP and CALL instructions
can be used.
Ex:
JMP AX Jumps to current code segment location addressed by
AX.
JMP NEAR PTR[BX] Jumps to the current CS location addressed by the
contents of BX.
JMP NEAR PTR[DI+2] Jumps to the current CS location addressed by the
contents of DI plus 2.
Indirect program jump instructions can use any 16-bit register any relative register (base
and index) and any relative register with a displacement.

JSR, CSE, AMCEC 40
STACK-MEMORY ADDRESSING MODES:
Stack holds data temporarily and stores the return addresses used by procedures. The
stack memory is LIFO (Last In-First Out) operated memory.
PUSH instruction stores into a stack and POP instruction removes a data from the stack.
The CALL instruction uses the stack to hold the return address for procedures and a RET
(return) instruction to remove the return address from the stack.
Stack memory is maintained by the stack pointer (SP) and stack segment register (SS).
Ex: PUSH BX.
PUSH BX places the contents of BX onto the stack. The diagram is shown after
execution.
To push a word data onto the stack, the high order 8-bits are placed in the location
addressed by SP-1 and the lower-order 8-bits are placed at Sp-2. Then SP is decremented
by 2.
POP instruction the low order 8-bits are removed from location addressed by SP. The
high-order 8-bits are removed from the location addressed by SP+1. The SP register is
then incremented by 2.
POP CX removes data from the stack and places them into CX. The diagram is shown after
execution.
Examples:
PUSH F Copies flag register to the stack.

JSR, CSE, AMCEC 41
POP F Removes a word from the stack and puts it into the flag
register.
PUSH DS Copies the DS register contents to stack.
POP CS Illegal instruction.
POP FD Removes double word from stack and puts into the EFLAG
register.
PUSH FD Copies EFLAG register to stack.
PUSH A Copies the contents of ALL the 16-bit registers except segment
registers onto the stack.
AX…….SI.
POP A Removes the word contents from the stack and puts them into
ALL the 16-bit registers.
SI……….AX.
PUSH AD Copies the contents of 32-bit registers to stack.
EAX……ESI.
POP AD Removes double word contents from the stack and puts them
into 32bit registers. ESI……..EAX.
PUSH 1234H Copies a word-sized data 1234H into the stack.
Data may be popped off the stack into any register or any segment register except CS,
because it only changes part of the next instruction.
PUSH A and POP A instructions either push or pop all. The registers, except segment
registers on to the stack. These instructions are not available for 8086, P4 and Core2
microprocessors.
The instructions PUSH A and POP A given above as examples show the order of the
registers transferred by the PUSH A and POP A instruction.

JSR, CSE, AMCEC 42
CHAPTER – 3
INSTRUCTIONS
MOV Revisited: Here we study the MOV instruction in the machine language instruction
formats available with various addressing modes and instructions.
Machine Language: Machine Language is the binary code that can be understood by the
microprocessor & uses this binary code as instructions to control its operation. Machine
language instructions vary in length from 1 to 13 bytes for 8086 through Core-2
processors. Instructions for 8086 through 80286 are 16-bit mode instructions as shown
below (fig.1). The 16-bit mode instructions are compatible with 80386 and above, if they
are programmed to operate in the 16-bit instruction mode. A prefix has to be added as
shown below (fig.2) to operate the 80386 - to- core2 microprocessors in 16-bit instruction
mode.
The 80386 and above processors assume that all instructions are 16-bit mode
instructions when the machine is operated in the real mode (DOS). In the protected mode
(Windows), the upper byte of the descriptor has the D-bit to select either 16 or 32 bit
mode. The 1st two bytes of 32-bit instruction mode format are called override prefixes.
The first byte modifies the size of the operand address used by the instruction and the
second modifies the register size.
If the 80386 to Pentium-4 machines operate as 16-bit instruction mode machines,
and use a 32-bit register, then the register size prefix (66H) is appended to the front of
the instruction. But if these machines are operated in 32-bit instructions mode, and a
32-bit register is used, then the register size prefix is not needed. Also if a16-bit register
appears in a 32-bit instruction mode, the register-size prefix is present to select a 16-bit
register.
The address size-prefix (67H) is also used in a similar manner. The prefixes toggle
the size of the register & operand addresses from 16-bit to 32-bit or from 32-bit to 16-bit
for the prefixed instructions. The mode of operation (16 or 32-bit) should be selected
to function with the current application. If data varies from 8-bit to 32-bit in the
application, then the 32-bit mode should be selected. This is done by the operating
system usually.
Opcode: Opcode selects the operation performed by the microprocessor. Opcode is either
1 or 2 bytes long for most machine language instructions.

JSR, CSE, AMCEC 43
The above figure shows the general form of the first & second Opcode bytes used by many
machine language instructions.
The first 6-bits of the first byte are the binary Opcode. The remaining 2-bits indicate D-
direction & W-word i.e. the size of the data whether it is a byte or a word.
Double word is also specified by W-bit in 80386 and above. If the direction bit D=1,
( ) data flows to the register REG field from the R/M field located in the second byte.
If D=0, ( ) then data flows to the R/M field from the REG field.
If W-bit=1, the data size is a word or double word, if W=0, the data size is always a byte.
The W-bit appears in most instructions, while D-bit appears only in the MOV and a few
other instructions.
MOD field: This specifies the addressing mode for the selected instruction. It selects the
type of addressing & whether a displacement is present or not.
MOD Function Example Addressing Mode
selected
00 No displacement MOV AL,[DI] Selects Data-Memory
Addressing Mode01 8-bit sign extended
displacement
MOV AL,[DI+2]
10 16-bit signed displacement MOV AL,[DI+1000H]
11 R/M field is a register selects register addressing mode
Table 1: 16-bit Instruction Mode MOD field
As shown in the table, if the MOD field contains 00, 01 or 10, the R/M field selects one
of the data memory addressing modes. If the MOD field is 11, it selects the register-
addressing mode. Register addressing uses R/M field to specify a register instead of a
memory location. If the MOD field is 01, then 8-bit sign extended displacement is
specified.
Ex- If the 8 bit displacement is 00H-7FH(positive), it is sign extended to 0000H-007EH
before adding to the offset address.
If the 8-bit displacement is 80H-FFH(negative), it is sign extended to FF80H-FFFFH. To
sign-extend a number, its sign bit is copied to the next higher-order byte, hence either
00H or FFH is put in the next higher order byte.
In 80386 through Core-2 microprocessors, the MOD fields are same as shown for 16-bit
instruction mode MOD field. Except for Mod-10, a 32-bit signed displacement is indicated
instead of a 16-bit signed displacement.
The MOD field is interpreted as selected by the address-size override prefix or the
operating mode of the microprocessor.
Register Assignments: The register assignments for the REG field and the R/M field is
given in the following table i.e. when the MOD field is 11(in columns 1,2,3,4) & it selects
register addressing mode. Each variation in the REG field assigns specific registers as
given in the table below, depending on the W-bit.
REG & R/M for MOD=11 If MOD = 00,01,10

JSR, CSE, AMCEC 44
Code
W=0
(Byte)
W=1
(Word)
W=1
(Double
word)
R/M field
R/M field for 32-bit
addressing
1 2 3 4 5 6
000 AL AX EAX DS:[BX+SI] DS:[EAX]
001 CL CX ECX DS:[BX+DI] DS:[ECX]
010 DL DX EDX SS:[BP+SI] DS:[EDX]
011 BL BX EBX SS:[BP+DI] DS:[EBX]
100 AH SP ESP DS:[SI] Uses scaled index byte
101 CH BP EBP DS:[DI] SS:[EBP] → special add. mode
110 DH SI ESI SS:[BP] DS:[ESI]
111 BH DI EDI DS:[BX] DS:[EDI]
Table 2: Consolidated table to show the register or addressing mode
assignment based on the MOD field.
Register Addressing Mode: (Use columns 1 to 4) i.e., when MOD=11
Example 1: Consider a 2 byte instruction: 8BECH of machine language.
As 8BECH does not have the prefixes 67H/66H, the first byte i.e. 8B is the opcode.
Since the instruction is 2 bytes long, assume that the microprocessor is operating in
16-bit instruction mode, & convert this machine instruction to binary code.
8B-First Byte EC-Second Byte
1000 1011 1110 1100 in binary
8 B E C
Now place this binary code in the 2 bytes of machine instruction:
Byte:1
100010-is the predefined opcode for the instruction MOV
D= 1, means transfer data to REG field
W=1, means data size is a word as it is a 16-bit instruction
Byte:2
MOD=11, hence it selects register addressing which means R/M field is a Register
REG=101, so choose the register from the table 2, with W=1, i.e., the register assigned
is BP
R/M=100, assigns the register SP as W=1
Hence the assembly language instruction is MOV BP,SP for machine code 8BECH.
Example 2: Convert the machine code 668BE8H into an assembly instruction for
a 80386 machine to operate in real mode.
66-Prefix 8B –First byte E8-Second Byte
Here 66-refers the prefix to change the register size. By default 80386 selects 16 bit
registers for real mode operation. But now because of the prefix it has to select 32 – bit
registers.
Byte1: 8B-1000 1011 Byte2: E8-1110 1000

JSR, CSE, AMCEC 45
Byte:1
100010-is the predefined opcode for the instruction MOV
D= 1, means transfer data to REG field
W=1, means data size is a word as it is a 32-bit register due to the prefix 66H
Byte:2
MOD=11, hence it selects register addressing which means R/M field is a Register
REG=101, so choose the register from the table 2, with W=1, i.e., the register assigned
is EBP
R/M=000, assigns the register EAX as W=1 & due to prefix 66H.
Hence the assembly language instruction is MOV EBP, EAX for machine code 8BECH.
If the same instruction is executed in Protected mode by 80386, then the Register size
prefix selects 16-bit registers and the final assembly instruction will be MOV BP,AX
Memory Addressing Modes: Use column 1 & 5 of table-2 for 16-bit
operations, when MOD=00/01/10
If the MOD field is 00/01/10 then the R/M field refers a particular memory addressing
mode as given in column 5 of table-2.
Displacement size is defined by MOD field.
Ex: If MOD=00 & R/M=101, the addressing mode is [DI];
if MOD=01 or 10, the addressing mode is [DI+33H] or LIST[DI+22H] for 16-bit instruction-
mode.
(displacement is 8 bit if MOD is 01, and 16 bit if MOD is 10)
Convert the machine language code 8A15H into an assembly instruction:
Opcode = MOV
D = 1, transfer to REG
W = 0, 1 byte
MOD = 00, No disp.
REG = 010, DL
R/M = 101, DS:[DI]
Therefore, instruction is MOV DL,[DI].
If the instruction is changed to MOV DL,[DI+2], the MOD field changes to 01 for 8-bit
displacement. Hence the machine instruction now becomes 8A5502H i.e. the instruction
is now 3 bytes long.

JSR, CSE, AMCEC 46
If the instruction is changed to MOV DL,[DI+1000H], then the machine language format
becomes 8A750010H i.e. the displacement 1000H is coded as 0010 in the machine
language. The lower byte is written first and then the higher byte is written, if it is a 16-
bit displacement.
Special Addressing Mode: It occurs when memory data is referenced by only the
displacement mode of addressing for 16-bit instructions.
Ex- MOV [1000H], DL & MOV PAGE, DL. (Here [1000H] & PAGE are only displacements).
When an instruction has only a displacement, the MOD field is always 00 & R/M field is
always 110. As given in the table, the instruction does not have displacement & uses
addressing modes [BP]. Since [BP] addressing mode cannot be used without a
displacement in machine language, the assembler changes to MOD-01 i.e. 8-bit
displacement and adds 00H as displacement. i.e. [BP] addressing mode assembles as
[BP+0].
Ex- MOV [1000H], DL encode this in machine language.
MOV = 100010 -- Machine code of MOV instruction.
D = 0 -- as destination is R/M field.
W = 0 -- as data size is 8-bit because DL is an 8-bit register.
MOV = 00 -- for special addressing mode.
REG = 010 -- for DL
R/M = 110 -- for special addressing mode= DS: [BP]
Displacement = 1000H
Memory Addressing Modes for 80386 and above processors : Use
column 1 & 6 of table -2 for 32-bit operations, when MOD=00/01/10
32-bit Addressing Modes: These are found in 80386 and above processors when these
machines run in the 32-bit mode or 16-bit mode. When the machine is running in 16-bit
mode the address-size prefix 67H is added to the instruction refer table 2. When
R/M=100, an additional scaled index byte is present in the instruction. The scaled index
byte is mainly used when two registers are added to specify the memory address in the
instruction. The format of the scaled-index byte when R/M=100 is as shown below.

JSR, CSE, AMCEC 47
SS
00= X1 Index & Base fields contain register numbers of REG field.
01= X2 Ex- MOV EAX [EBX+4*ECX] in M/C language is 6766880488H
10= X4
11= X8
An Immediate Instruction: Example for a 16-bit instruction using immediate
addressing is
MOV WORD PTR[BX+1000H],1234H. This instruction moves the data- 1234H into the
word sized memory location addressed by [BX+1000H]. This is a 6-byte instruction
where:
 2-bytes are used for Opcode, W, MOD and R/M fields.
 2-bytes are used for the data 1234H.
 2-bytes are used for the displacement 1000H. It is as shown in the fig. below.
Opcode: MOV immediate = 1100011 [is different from the normal MOV].
W = 1 ---- Word
MOD = 10 ---- 16-bit displacement
REG = 000 (not used in immediate addressing)
B/M = DS: [BX]
Displacement = 1000H
Data = 1234H
For immediate instructions the BYTE PTR; WORD PTR or DWORD PTR can be used to
indicate the actual size of the data. Ex- If the instruction is MOV [BX],9, does not indicate
the actual size of the data, as [BX] holds the address. The assembler will be confused
with the data size. Hence, a pointer is used to define the exact size of the data.
Ex- MOV BYTE PTR[BX],9→ stores 9 in a single byte as 09
MOV WORD PTR[BX],9→ stores 9 in a word i.e. 2 bytes as 0009
Segment MOV Instructions: If MOV, PUSH or POP instructions are used to move the
contents of a segment register, the REG field selects the segment register as given in the
table below.

JSR, CSE, AMCEC 48
Code Segment Register
000 ES
001 CS*
010 SS
011 DS
100 FS
101 GS
* MOV CS, R/M & POP CS are not allowed.
This binary machine language code is for the instruction MOV BX, CS
The Opcode for segment MOV is different i.e. 100011. Segment registers can be moved
between any 16-bit register or 16-bit memory location. An immediate segment register
MOV is not available, hence first load any other register with data and then move it to a
segment register.
The 64-Bit Mode for the Pentium-4 and Core-2: In 64-bit mode, an additional prefix
called REX-register extension is added. This REX prefix is encoded as a 40FH to 4FH,
depending on REG & R/M field, and is placed immediately before the Opcode field, to
modify it for 64-bit operation.
REX is necessary to modify the REG & R/M fields in the second byte of the instruction,
and also to address the R8 through R15 registers.
Structure of REX and its application to the second byte of the Opcode:
If W= 1, indicates 64 bits
W= 0, it is a CS descriptor
The registers and memory designators for RRRR and MMMM are as shown in the table
below:
Code Register(RRRR) Memory(MMMM)
0000 RAX [RAX]
0001 RCX [RCX]
0010 RDX [RDX]
0011 RBX [RBX]
0100 RSP Scaled-index byte
0101 RBP [RBP]
0110 RSI [RSI]
0111 RDI [RDI]

JSR, CSE, AMCEC 49
1000 R8 [R8]
1001 R9 [R9]
1010 R10 [R10]
1011 R11 [R11]
1100 R12 [R12]
1101 R13 [R13]
1110 R14 [R14]
1111 R15 [R15]
As seen in the table to address these 15-64 bit registers we need 4 bits for each register.
The second byte of the Opcode contains only 3 bits, hence the 4th bit is given by the REX
prefix as shown in the above table.
For scaled-index addressing, an additional scaling byte is included with the prefix REX,
as shown in the fig. below:
PUSH/POP: PUSH and POP instructions store and retrieve data the LIFO(Last In First
Out) stack memory. There are six forms of PUSH & POP instructions in a
microprocessor.
They are register, memory, immediate, segment register, flags and all registers.
The immediate and all registers forms are not available in 8086/8088 microprocessors.
PUSH: PUSH instruction always transfers data into the stack. In the 8086-80286 the
PUSH instruction transfers 2 bytes of data into the stack, whereas in 80386 and above
microprocessors the PUSH instruction transfers 2 or 4 bytes of data, depending on the
register or memory size. The source of data can be any 16 or 32-bit registers, immediate
data, any segment register, or any 2 bytes of memory data.
PUSH A: This instruction is present to copy the contents of all the internal register set,
except the segment registers, to the stack. It copies the contents of the registers in the
following order: AX, CX, DX, BX, SP, BP, SI & DI.
PUSH F: PUSH Flags instruction copies the contents of the flag register to the stack.
PUSH AD: Instruction stores the contents of all 32-bit registers found in 80386 through
P-4, but not in 64-bit mode of operation.

JSR, CSE, AMCEC 50
The operation of the PUSHAX instruction is shown in the fig. below after execution:
The word contents of AX are stored to stack as shown in the figure. The most significant
or the first byte moves into the stack segment memory location addressed by SP-1,(SP
minus 1) while the second or least –significant byte moves into the stack segment memory
location addressed by SP-2, (SP minus 2) after storing the data into stack, the contents
of SP register is decremented by 2.
The PUSH instruction Examples:
PUSH ‘A’ - stores the ASCII code of A
PUSH BX - store the contents of 16-bit BX register to stack.
PUSH EDX - store the contents of 32-bit EDX register to stack.
PUSH WORD PTR[BX]- store the 16-bit/word data addressed by BX.
PUSH 1000H - store the immediate 16-bit data to stack.
PUSH A - store all registers of 16-bit to stack.
PUSH AD - store all 32-bit registers to stack.
PUSH F - store all flag register to stack.
PUSH FD - store the EFLAG/double word/32-bit flag register.
POP: It removes the data from the stack and puts it into the destination 16-bit register,
segment register or a 16-bit memory location. There is no immediate POP instruction.
POP F: Instruction removes a 16-bit data from the stack and puts it into the flag register.
The POP Instructions:
POP CX : Removes 16-bit data from the stack & places in CX.
POP EBP : Removes 32-bit data from the stack & places in ERP.
POP WORD PTR[BX+1]: Removes 16-bit data from stack & stores to the memory addrs
given in [BX+1]
POP FS : From stack to segment register FS.
POP A : From stack to all 16-bit registers.
POP AD : From stack to all 32-bit registers.
POP F : From stack to flag register 16-bit.
POP FD : From stack to 32-bit flag register.
For POP A, the data from stack is stored into registers in the following order: DI, SI, BP,
SP, BX, DX, CX, AX.

JSR, CSE, AMCEC 51
Figure shows how data from stack is Poped to BX after execution.
Initialization of Stack: To initialize stack, load the stack segment register(SS) & the
stack pointer register(SP) with the starting address in SS & the length of the segment in
SP.
LOAD Effective Address: LEA instruction loads any 16-bit or 32-bit register with the
offset address as given in the instruction. Ex- LEA AX, NUM B→ loads AX with the offset
address of NUM B.
LEA BX,[DI] loads the offset address present in DI i.e. the contents of DI into BX register.
But
MOV BX,[DI] loads the data stored at the memory location address present in DI into the
register BX. MOV BX, OFFSET LIST is same as LEA BX,LIST. Both these instructions
load the offset address of the memory location LIST into BX register.
The OFFSET directive works only with simple operands such as LIST, but not for
operands such as [DI], [SI], LIST [SI], etc. OFFSET directive is more efficient & faster than
LEA for simple operands. OFFSET is faster because the assembler calculates the offset
address for the instruction. MOV BX,OFFSET LIST. Whereas the microprocessor
calculates the address for LEA instruction.
For example- LEA SI,[BX+DI] adds BX to DI & stores the sum in the SI register.
LDS, LES, LFS, LGS & LSS: These instructions load any 16-bit or 32-bit register with
an offset address & the DS, ES, FS, GS or SS segment register with a segment address.
These instructions use any addressing mode to address a 32-bit or 48-bit portion of
memory which contains both the segment and offset address.
32-bit section of memory has: 16-bit offset address and 16-bit segment address.
48-bit section of memory has: 32-bit offset address & 16-bit segment address.
Example- LDS BX,[DI]→ transforms the 32-bit data addressed in DI in the data segment
into BX & DS registers.

JSR, CSE, AMCEC 52
The LDS BX, [DI] instruction loads register BX from address 11000H and 11001H and
register DS from locations 11002H & 11003H.
In 80386 and above an LDS EBX,[DI] instruction loads EBX from the 4-byte section of
memory addressed by [DI] and the remaining word data is loaded to the DS register. Thus
a 48-bit data is loaded into a 32-bit register and a segment register.
The first 4 bytes (32-bits) contain the offset value loaded to the 32-bit register & the last
2 bytes contain the segment address.
STRING DATA TRANSFERS: The instructions for string data transfer are: LODS, STOS,
MOVS, INS & OUTS. Each string instruction can transfer a byte, word or double word
data.
Direction Flag: D in the flag register selects auto decrement if D=1 or selects auto
increment if D=0 for the DI & SI registers during string operations. The direction flag is
used only with the string instructions. The CLD instruction is used to clear the Direction
Flag i.e. D=0 and STD instruction sets D=1. Hence, CLD selects auto increment mode i.e.
D=0 & STD selects auto decrement mode D=1.
Whenever a string instruction transfers a byte, the contents of DI or/and SI are
incremented or decremented by 1. If a word is transferred, the contents of DI and/or SI
is incremented or decremented by 2. Double word Transfers make DI and/or SI to
increment or decrement by 4.
DI and SI: For executing a string instruction, memory is accessed through either DI/SI
or both SI and DI. The DI offset address accesses data in extra segment for all string
instructions. The SI offset address accesses data in the data segment by default.
LODS: Loads AL, AX or EAX with data stored in the data segment offset address indexed
by SI register. After loading the respective register, the contents of SI increments if D=0
or decrements if D=1.
1 is added/subtracted from SI for a byte-sized LODS.
2 is added/subtracted from SI for a word-sized LODS.
4 is added/subtracted from SI for a double-word LODS.
Permissible forms of LODS instruction:
LODS B→ AL=DS:[SI]; SI=SI±1
LODS W→ AX= DS:[SI]; SI=SI±2

JSR, CSE, AMCEC 53
LODS D→ EAX=DS:[SI]; SI=SI±4
LODS Q→ RAX=DS:[SI]; SI=SI±8
LODS LIST→ AL=DS:[SI]; SI=SI±1(if list is a byte)
LODS DATA1→ AX=DS:[SI]; SI=SI±2(if DATA1 is a word)
LODS DATA2→ EAX=DS:[SI]; SI=SI±4(if DATA2 is a doubleword)
STOS: This instruction stores AL, AX, EAX at the extra segment memory location
addressed by DI register.
All forms of STOS instruction:
STOS B→ ES:[DI]=AL; DI=DI±1
STOS W→ ES:[DI]=AX; DI=DI±2
STOS D→ ES:[DI]=EAX; DI=DI±4
STOS Q→ [RDI]=RAX; RDI=RDI±8
STOS LIST→ ES:[DI]=AL; DI=DI±1 for byte
STOS DATA3→ ES:[DI]=AX; DI=DI±2 for word
STOS DATA4→ ES:[DI]=EAX; DI=DI±4 for double word
STOS B: Stores a byte in AL at extra segment memory location addressed by DI. Similarly
STOSW stores a word in ES & STOSD stores a double word in ES. After storing a byte,
word or double word, the contents of DI is incremented or decremented by 1/2/4.
STOS with a REP: The repeat prefix (REP) is added to any string data transfer instruction
except LODS instruction. The REP prefix decrements CX by 1 each time the string
instruction executes. The string instruction repeats till CX=0 and then terminates.
Ex- REP STOS B; if CX= 50, the microprocessor repeats the STOSB instruction 50 times
and stores the contents of AL in a block of memory.
Example: Program to clear an area of the memory named Buffer, with a count using REP
STOS W.
PUSH EDI
PUSH ES Save Registers
PUSH DS
MOV AX,0
MOV ECX,count
MOV EDI,buffer
POP ES ; loads CS with DS
REP STOSW ; clear buffer
POP ES ; restore registers
POP EDI
MOVS: Transfers data from one memory location to another. MOVS transfers a byte,
word or double word from the data segment location addressed by SI to extra segment
location addressed by DI. SI & DI are then decremented or incremented depending on D
flag.
List of all permissible MOVS instructions are:
MOVSB ES:[DI]= DS:[SI]; DI & SI= ±1, Byte transfer
MOVSW ES:[DI]= DS:[SI]; DI & SI= ±2, Word transfer
MOVSD ES:[DI]= DS;[SI]; DI & SI= ±4, double word transfer
MOVSQ
MOVS BYTE1, BYTE2
MOVS WORD1, WORD2

JSR, CSE, AMCEC 54
MOVS TED, FRED
Example: Program to transfer two blocks of double word memory i.e. copy block A into
block B using the MOVSD instruction:
PUSH ES
PUSH EDI ; save registers
PUSH ESI
PUSH DS
POP ES ; copy DS into ES
MOV ESI, blockA ; copy address of block A to ESI
MOV EDI, blockB ; copy address of block B to EDI
MOV ECX, blocksize ; load count
REP MOVSD ; mov data
POP ESI
POP EDI ; restore registers
POP ES
INS(Input String)- not available in 8086/88 microprocessors:
INS transfers a byte, word or doubleword of data from an I/O device into the extra
segment memory location addressed by the DI register.
The I/O device address will be in DX register. This instruction is useful for inputting a
block of data from an external I/O device directly into the memory.
Forms of INS Instruction:
Assembly Language Operation Performed
INS B ES:[DI]= [DX]; DI=DI±1; byte transferred
INS W ES:[DI]= [DX]; DI=DI±2; word transferred
INS D ES:[DI]= [DX]; DI= DI±4; double word transferred
INS LIST ES:[DI]= [DX]; DI= ±1; if LIST is a byte
INS DATA4 ES:[DI]= [DX]; DI= ±2; if DATA4 is a word
INS DATA5 ES:[DI]= [DX]; DI= ±4; if DATA5 is a double word
Here, [DX] is the I/O device address.
OUTS(Output String)- not available in 8086/88:
OUTS transfers a byte, word or double word of data from the data segment memory
location, addressed by SI to an I/O device. I/O device address is in the DX register.
Forms of OUTS instruction:
OUTS B [DX]= DS:[SI]; SI±1(byte transferred)
OUTS W [DX]= DS:[SI]; SI±2(word transferred)
OUTS D [DX]= DS:[SI]; SI±4(double word transferred)
OUTS DATA7 [DX]= DS:[SI]; SI±1(if DATA7 is a byte)
OUTS DATA8 [DX]= DS:[SI]; SI±2(if DATA8 is a word)
OUTS DATA9 [DX]= DS:[SI]; SI±4(if DATA9 is a doubleword)
Miscellaneous Data Transfer Instructions:
XCHG, LAHF, SAHF, XLAT, IN, OUT, BSWAP, MOVSX, MOVZX & CMOV.

JSR, CSE, AMCEC 55
Note: These are not used as often as MOV instruction.
XCHG(Exchange): Instruction exchanges the contents of a register with the contents of
any other register or memory location. This instruction cannot exchange segment
registers or memory to memory data.
Forms of XCHG instructions:
XCHG AL, CL Exchanges the contents of AL with CL
XCHG ECX, EBP Exchanges the contents of ECX with EBP
XCHG AL, DATA2 Exchanges the contents of AL with memory location DATA2
XCHG RBX,RCX Exchanges the contents of RBX with RCX
LAHF and SAHF (load AH with Flag, store AH to flag):
These instructions are rarely used since they are bridge instructions.
LAHF- Transfers the rightmost 8 bits of the flag register into the AH register.
SAHF- Transfers the contents of AH register into the rightmost 8 bits of the flag register.
These instructions do not function in 64-bit mode.
XLAT(Translate): XLAT converts the contents of AL register into a no. stored in a memory
table. It performs the direct table lookup technique which is used to convert one code to
another. XLAT inst. first adds the contents of AL to BX, to form a memory address within
the data segment. Then it copies the contents of this address into AL.
Operation of the XLAT instruction just before 6DH is loaded in AL
IN & OUT: An IN instruction transfers data from an external I/O device into AL, AX or
EAX and an OUT instruction transfers data from AL, AX, or EAX to an external I/O
device.
Forms of IN & OUT Instructions:
Assembly Language Operation
IN AL,P8 8 bits are input to AL from I/O port P8
IN AX,P8 16 bits are input to AX from I/O port P8 Fixed
Port
IN EAX,P8 32 bits are input to EAX from I/O port P8
IN AL,DX 8 bits are input to AL from I/O port DX
IN AX,DX 16 bits are input to AX from I/O port DX Var. Port
IN EAX,DX 32 bits are input to EAX from I/O port DX
OUT P8,AL 8 bits are output from AL to the I/O port P8
OUT P8,AX 16 bits are output from AX to the I/O port P8

JSR, CSE, AMCEC 56
OUT DX,AL 8 bits are output from AL to the I/O port DX
OUT DX,EAX 32 bits are output from EAX to the I/O port DX
Note: P8 is a 8 bit I/O port number.
DX is a 16 bit I/O port number.
There are two forms of I/O device addressing for IN & OUT instructions, which are
Fixed Port and Variable Port address:
 If the port no. follows the instructions Opcode, it is called Fixed-Port addressing.
Ex- IN AL,P8
 If the port address is 16-bit and is stored in DX, it is called a variable-port
addressing. Ex- IN AL,DX
The Signals found in the microprocessor- based system for an OUT 19H,AX instruction
The above fig. illustrates the execution of OUT 19H, AX instruction, which transfers the
contents of AX to I/O port 19H. The system control signal IOWC -I/O write control is a
logic zero to enable the I/O device.
MOVSX and MOVZX:
MOVSX- move and sign extend & MOVZX- move and zero extend.
These instructions are found in 80386- P4 instruction sets. These inst. move data and
also extend the sign bit or zero bit. When a no. is zero- extended, the most significant
part fills with zeros. When a no. is sign- extended, its sign- bit is copied into the most
significant part.
The MOVSX & MOV ZX instructions:
Instruction Operation
MOVSX CX,BL Extends the sign bit of BL into CX
MOVSX ECX,AX Extends the sign bit of AX into ECX
MOVSX BX,DATA1 Extends the sign bit of DATA1 contents into BX
MOVSX EAX,[EDI] Extends the sign bit of the word addressed by EDI
into EAX
MOVZX DX,AL Extends zero of AL into DX
MOVZX EBP,DI Extends zero of DI into EBP
MOVZX EAX,DATA3 Extends zero of the word at DATA3 into EAX
BSWAP(Byte Swap): This instruction is available only in 80486- P4 microprocessors. It
takes the contents of any 32 bit register and swaps the 1st byte with the 4th & 2nd with
the 3rd. This inst. converts data between the big and little Endian forms. Ex- BSWAP
EAX, with EAX= 11223344; after swapping EAX= 44332211.

JSR, CSE, AMCEC 57
CMOV(Conditional Move): It is for Pentium Pro- Core- 2 instruction sets only. The many
variations of the CMOV instructions are listed as below. These instructions move the data
only if the condition is true.
Instruction Flags Tested Operation
CMOV B C=1 Move if below
CMOV AE C=0 Move if above or equal
CMOV BE Z=1 or C=1 Move if below or equal
CMOV A Z=0 or C=0 Move if above
CMOV E or CMOV Z Z=1 Move if equal or zero
CMOV NE or CMOV NZ Z=0 Move if not equal or not zero
CMOV L S!=0 Move if less than
Similarly CMOV can be used with LE- if less than or equal, G- if greater than, GE- if
greater than or equal, S- if sign negative(-), NS- if no sign(+), C- if carry, NC- if no carry,
O- if overflow, NO- if no overflow, P/PE- if parity or if parity even, NP/PO- if no parity or
if parity odd.
Segment Override Prefix: This prefix can be added to any instruction in any memory
addressing mode. This allows the programmer to deviate from the default segment. This
is an additional byte that appends in the front of an instruction to select an alternate
segment register. Ex- MOV AX,[DI] instruction accesses data within the data segment by
default. But if a segment override prefix is added i.e. MOV AX,ES:[DI], it addresses the
extra segment instead of data segment.
Instructions which include Segment Override prefixes:
Assembly Language Segment Accessed Default Segment
MOV AX,DS:[BP] Data Stack
MOV AX,ES:[BP] Extra Stack
MOV AX,SS:[DI] Stack Data
MOV AX,CS:LIST Code Data
LODS ES:DATA1 Extra Data
MOV EAX,FS:DATA2 FS Data
MOV GS:[ECX],BL GS Data
Assembler Details:
The assembler for microprocessor can be used in two ways:
 With models that are unique to a particular assembler.
 With full- segment definitions which allow complete control over the assembly
process and are universal to all assemblers.
Directives: Directives are (Pseudo- operations) instructions which control the assembly
process. Directives indicate how an operand or section of a program should be processed
by the assembler. Some directives generate and store information in the memory, but
Byte PTR directive only indicates the size of the data referred by a pointer or index register
but does not store any data.

JSR, CSE, AMCEC 58
By default, the assembler accepts only 8086/88 instructions. If a program is preceded
by the .686 or .686 P directives, it tells the assembler to use the Pentium Pro instruction
set(.686) or Pentium Pro protected instruction set(.686 P). This can vary from .286 to
.686 & .287, .387 for math coprocessor.
Storing Data in a Memory Segment: The DB(Define Byte), DW(Define Word), DD(Define
Doubleword) & (DT- Define ten bytes) are used to define and store memory data. These
directives label or name defines a memory location with a symbolic name & indicate its
size. Memory is reserved to use in future by using a question mark(?) as an operand for
DB, DW or DD directive. The assembler reserves a location and does not initialize it to
any value. The DUP(duplicate) directive creates an array. Ex- 10 DUP(?) reserves 10
locations of memory, but does not store any value. If a no. is given with the () of a DUP
statement, the assembler initializes the reserved section of memory with this data. Ex-
LIST2 DB DUP(3)- this instruction reserves 10 bytes of memory for the array LIST2 and
initializes each location with 03H.
Few Common MASM directives are listed below:
Directive Function
.286 Selects the 80286 instruction set
.286 P Selects the 80286 protected mode inst. set
.287 Selects the 80287 math coprocessor
.387 Selects the 80387 math coprocessor
.CODE(Models only) Indicates the start of the code segment
.DATA(Models only) Indicates the start of the data segment
.EXIT(Models only) Exits to DOS
.MODEL Selects the programming model
.STACK(Models only) Starts the stack segment
.STARTUP(Models only) Indicates the starting inst. in a program
ALIGN n Aligns to boundary n(n=2 for words, n=4 for doubleword)
ASSUME Informs the assembler to name each segment
BYTE Indicates the byte- sized data, as in BYTE PTR
DB Defines a byte or bytes(8 bits)
DO Defines doublewords(32 bits)
DQ Defines Quadwords(64 bits)
DT Defines Ten bytes(80 bits)
DUP Generates duplicates
DW Defines word(16 bits)
DWORD Indicates doubleword- sized dat,a as in DWORD PTR
END Ends a program file
ENDM Ends a Macro sequence
ENDP Ends a Procedure
ENDS Ends a segment or data structure
EQU Equates data or a label to a lebel
FAR Defines a FAR pointer, as in FAR PTR
MACRO Indicates the start of a Macro sequence
NEAR Defines a near pointer, as in NEAR PTR
OFFSET Specifies an offset address
ORG Set the origin within a segment

Adv mp&arm.pdf

Recommended

Recommended

More Related Content

What's hot

What's hot (19)

Similar to Adv mp&arm.pdf

Similar to Adv mp&arm.pdf (20)

Recently uploaded

Recently uploaded (20)

Adv mp&arm.pdf

Adv mp&amp;arm.pdf

Recommended

Recommended

More Related Content

What's hot

What's hot (19)

Similar to Adv mp&amp;arm.pdf

Similar to Adv mp&amp;arm.pdf (20)

Recently uploaded

Recently uploaded (20)

Adv mp&amp;arm.pdf

Adv mp&arm.pdf

Similar to Adv mp&arm.pdf

Similar to Adv mp&arm.pdf (20)

Adv mp&arm.pdf