3. 3
Outline
Performance Limitations
- Resolution
- Offset and Gain Error
- Accuracy and Linearity
Nyquist-rate D/A converters
- Resistor String Converters
- Binary-Weighted Resistor Converters
4. 4
ADC Performance metrics – A High Level ADC
Model
S
X
d
dt
Vin
jRMS
njitter
S
S
nQ
nps
nthermal
nD
Nout
ADC Model jRMS = clock jitter (RMS cycle
to cycle)
nD = distortion (RMS value)
nQ = quantization noise (RMS
value, uniform)
nSupply = power supply noise (RMS value,
spikes) PSRR can be modeled as LPF
nthermal = thermal noise (RMS
value, gaussian)
nSupply
PSRR
ABW
ABW = analog (full power)
bandwidth
The signal to noise and distortion ratio (SNDR) (assuming a full scale single tone
input) is:
Based on the SNDR, the effective number of bits ENOB are defined as:
2
2
2
2
2
8
2
log
10
ps
jitter
thermal
D
Q
VFS
n
n
n
n
n
SNDR
02
.
6
76
.
1
SNDR
ENOB
5. 5
ADC Performance metrics – Static Characteristic
of an Ideal ADC
Vin
Nout
-VFS/2 VFS/2
VLSB
VLSB
1/2
-1/2
NoutMax
-NoutMax
-NoutMax
NoutMax
NLEV odd
NLEV even
Vi Vi+1
Vci
VLSB=VFS/NLEV
NoutMax=(NLEV-1)/2
Vci=i*VLSB
Vi=(i-½)*VLSB
1
-1
NLEV
VFS
VLSB
ideal
Max
Max
i
Nout
i
Nout
i
VLSB
V
1
for
)
( 2
1
ideal
ideal
Decision levels:
12
2
2 VLSB
nQ
Quantization error
(noise):
Assumes uniform signal
PDF over the code bin.
ADC Resolution:
For a full-scale single tone signal quantized by an ideal ADC:
76
.
1
02
.
6
)
log(
20
log
10
)
log(
10
log
10
2
2
3
2
2
3
2
8
ideal
2
Nbit
NLEV
n
SNDR
Nbit
NLEV
VLSB
VFS
Q
VFS
)
(
log2 NLEV
Nbit
ENOB
definition
6. 6
ADC Performance metrics – Offset and Gain Error
Offset and gain errors
can be defined by end-
to-end or by best fit.
End-to end definitions
(using the outer
decision levels):
Vin
Nout
-VFS/2 VFS/2
1/2
-1/2
NoutMax
-NoutMax
Ideal ADC
Vi
ideal
V-Noutmax+1
VNoutmax
Non-Ideal ADC
NoutMax-1/2
-NoutMax+1/2
(NLEV-2)*VLSB
Vi
Voff
i
Gain Error
2
1 Max
Max Nout
Nout V
V
Voff
2
1
NLEV
V
V
VLSB Max
Max Nout
Nout
[%]
100
1
ideal
VLSB
VLSB
GE
7. 7
ADC Performance metrics – INL and DNL
INL (integral non-linearity) and DNL
(differential non-linearity) are defined
AFTER correcting for linear (offset
and gain) errors.
Vin
Nout
-VFS/2 VFS/2
V-Noutmax+1
VNoutmax
Non-Ideal ADC
NoutMax-1/2
-NoutMax+1/2
(NLEV-2)*VLSB
Vi
INLi*VLSB
Voff
Vi
*ideal
Offset and Gain Fitted
Ideal ADC
i
2
1
i
VLSB
Voff
V
INL i
i
i
i
i
i
i INL
INL
VLSB
V
V
DNL
1
1
1
INL can be interpreted as the distance
between the actual decision level
and the decision level of an ideal
ADC that has been gain and offset
corrected expressed in VLSB units.
The DNL expresses the difference
between the actual and the ideal code
bin widths in VLSB units.
The first and last code bin widths are
defined by extension by VLSB, so that
by definition:
0
0
1
Max
Max
Max
Max Nout
Nout
Nout
Nout DNL
DNL
INL
INL
1
i
Nout
k
k
i
Max
DNL
INL
Max
Max
Nout
Nout
k
k
DNL 0
8. 8
ADC Performance metrics – From INL to ENOB
There is no simple conversion from the two metrics, however:
Max
Max
i
i
Nout
Nout
i
V
V
i
i
i
DQ dv
Vc
v
V
V
NLEV
n
1
2
ideal
*
1
2
)
(
1
1
2
2
2
1
1
2
2
2
2
3
12
D
Max
Max
Q n
Nout
Nout
i
i
i
i
i
n
DQ INL
INL
INL
INL
NLEV
VLSB
VLSB
n
i
INL
INL
2
2
2
2
27
2
12
3
2
12
2
2
2
2
2
2
2
D
Q
D
Q n
Max
n
n
INL
n
DQ
INL
VLSB
VLSB
VLSB
VLSB
n
2
2
2
1
1
2
2
2
2
3
12
D
Max
Max
Q n
Nout
Nout
i
i
i
i
i
i
n
DQ INL
INL
INL
INL
P
VLSB
VLSB
n
i
P
The mean square error (quantization and distortion) can be calculated (assuming the input signal has an uniform probability density
function):
(uniform PDF input)
We observe that equation above contains the quantization and the distortion components. Making the further assumption that
are uncorrelated, with a normal distribution of standard deviation then we get:
(uniform PDF input)
For signals that do not have an uniform probability density function, assuming the probability density is uniform within each code bin we get:
where is the probability that the input signal is within code bin i.
9. 9
ADC Performance – A Glimpse at ADC State of the Art
(1)
R.H. Walden, “Analog-to-digital converter survey and analysis,” IEEE Journal on Selected Areas in Communications,
vol. 17, no. 4, pp. 539-550, April 1999.
ADC performance is limited by fundamental laws of nature
10. 10
ADC Performance – A Glimpse at ADC State of the Art
(2)
Additional performance metrics are customary:
Nbit
te
SamplingRa
Power
2
ision
Energy/Dec
ENOB
te
SamplingRa
age
SupplyVolt
Power
2
FOM
Merit
of
Figure
R.H. Walden, “Analog-to-digital converter survey and analysis,” IEEE Journal on Selected Areas in Communications,
vol. 17, no. 4, pp. 539-550, April 1999.
Progress in ADC performance in terms of ENOB is slow
11. 11
ADC Performance – A Glimpse at ADC State of the Art
(3)
Yun Chiu; Gray, P.R.; Nikolic, B.,"A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR", IEEE Journal of
Solid-State Circuits, , Volume: 39 , Issue: 12 , Dec. 2004
Progress in ADC power consumption (Figure of Merit) is fast
12. 12
ADC Performance – A Glimpse at ADC State of the Art
(4)
Where do we stand today?
0
2
4
6
8
10
12
14
16
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10
Sampling Rate [Samples/s]
ENOB
[bit]
ISSCC2009 ISSCC2007 ADI
0.000
0.500
1.000
1.500
2.000
2.500
1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10
Sampling Rate [Samples/s]
Energy
per
decision
[pJ]
ISSCC2009 ISSCC2007 ADI
Research papers quote net power, industrial data is for a packaged ADC
13. 13
ADC Performance – A Glimpse at ADC State of the Art
(4)
Recent trends in ADC design
- Very high sampling rate modest resolution low power converters
for serial communications
- High complexity DSP-intensive solutions
- ADC power has decreased x10 in the last decade,
- In the same period, digital circuit power has decreased x100.
- SNR > 50 digital is very cheap
- SNR >70 it is for free.
- New design paradigm: analog, DSP and system level have to go
hand in hand.
14. 14
ADC Measurement Techniques – The Histogram Method
Setup for ADC Characterization
For measurement purposes we
need a very accurate signal
source - single and dual tone
sources are used
In order to get a clean
measurement, a very large
number of samples is required
A convenient way to reduce the
storage requirements for the
samples is to collect a histogram:
count the occurrences h(i) of
each code bin I
The normalized cumulative
normalized histogram is defined:
Generator
Clock Source
Data Collection
ADC Under Test
Post-
Processing
BPF
f
f
f
The spectral purity of the signal applied to
the ADC is very important
The jitter on the clock source has to be well
controlled
The clock and signal frequencies have to
be close to independent to make sure all
possible clock-signal phase relationships
are swept
)
(
)
(
)
(
)
( 1
0
0
i
L
k
i
k
V
v
P
k
h
k
h
i
ch
15. 15
ADC Measurement Techniques – The Histogram Method
Sine Wave Quantization
If we know the signal amplitude
and offset we can calculate the
decision levels from the
normalized cumulative histogram
of the code bins
The signal at the input of the
ADC is usually not directly
accessible for measurement:
- The parameters A and d
have to be estimated
- Note: V is measured here in
LSB units
A
d
p
p f
fi pfi
Vi
d+Asin(fi)
p
p
p
f
p
f
2
arcsin
2
2
2
)
)
(
(
A
d
V
V
v
P
i
i
i
1
)
)
(
(
cos
i
ch
i
i V
v
P
A
d
V f
p
16. 16
ADC Measurement Techniques – The Histogram Method
Simple Sine Fitting
The simplest way to estimate the parameters A and d is to assume the
outmost excited decision levels are correct
If l and h are respectively the lowest and highest non-empty code bins, we
assume Vl+1 and Vh-1 to be correct. (Reminder- V is in LSB units)
)
1
(
cos
)
(
cos
)
(
cos
)
1
(
)
1
(
cos
)
1
(
cos
)
(
cos
1
h
ch
l
ch
l
ch
h
h
ch
l
d
h
ch
l
ch
l
h
A
p
p
p
p
p
p
Next All the decision levels can be estimated and then the INL and
DNL
The ENOB and SNDR parameters can also be estimate from the
histogram data
For accurate results a more sophisticated sine fitting method has to be
used that uses the whole of the information in the histogram.
h
h
ch
A
d
V
l
l
ch
A
d
V
h
l
)
1
(
cos
1
)
(
cos
1
p
p
17. 17
ADC Calibration Techniques – Definition of the
Problem
ADC calibration techniques aim to improve the overall performance of a
given ADC by means of added circuitry
Raw
Output
ADC
Calibration System
N Bit
Corrected
Output
M >= N Bit
vin
Reference Control
18. 18
Limitations of ADC Calibration Techniques
Calibration techniques can not cancel:
- Random effects (thermal noise, jitter)
- Quantization noise (an 8 bit ADC can not become 9 bit after
calibration)
- Fast events (spikes, metastability)
19. 19
Classification of ADC Calibration Techniques (1)
By the domain of the correction:
- Analog calibration techniques
- Adjust reference voltages
- Adjust components (capacitors, resistors)
- Dynamic matching techniques
- Digital calibration techniques
- No adjustment is performed on the analog circuitry
- Some analog calibration source is always needed
(By the nature of the problem any calibration technique is a mixed-
mode circuit)
20. 20
By the time the correction is performed:
- Background calibration techniques
- Calibration circuits run in parallel and not interfering with the
normal functioning of the ADC
- Off-line calibration techniques
- Require a specially allocated training mode
- Offline calibration can be performed
- At fabrication (expensive, done at testing time)
- At power-up
- Periodically (but it incurs inactive times)
Classification of ADC Calibration Techniques (2)
21. 21
By the nature of the underlying ADC model :
- Static calibration
- The ADC is described by a static (memory-less) non-linear function
- Dynamic (slope dependent) impairments can not be corrected
- Dynamic calibration
- The ADC is described by a non-linear dynamic system
- Increased complexity of the calibration technique
Classification of ADC Calibration Techniques (3)
22. 22
Analog Calibration by Capacitor Trimming
(in pipe-line ADC)
The Capacitor Trimming Technique by Capacitor
Divider Network
Comparator Based Trimming Technique
Delta-Sigma Trimming Technique
Limitations and Benefits of Trimming
23. 23
Capacitor Divider (1)
In practice several taps are
built and the trimming is done
with a resolution of up to 3-4
bits C
C1 C2
Ct
b 0
1
Ceq
Vt
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
C
C
C
C
b
C
C
C
C
C
C
C
C
C
C
C
C
b
C
C
C
C
C
Ceq t
t
t
24. 24
Capacitor Divider (2)
Parasitic capacitances on the floating nodes increase the effect
of parasitic capacitances to the substrate
Depending on technology, non-discharged floating nodes can be
a problem
The additional switches used for trimming will increase the
leakage problems
C
C1 C2
Ct
b 0
1
Ceq
Vt
Cp
C2+bCt
Ceq C
C1*Cp
C1+C2+bCt+Cp
C1*(C2+bCt)
C1+C2+bCt+Cp
C2*Cp
C1+C2+bCt+Cp
25. 25
Comparator Based Trimming Technique
The comparator can use the
stage amplifier
Offset Cancellation is needed
This is an off-line technique
-
+
F2
F1
Cf
Ci
Va
F1 Comp
F2
F1
Vref
Vref
Search Engine
(Logic)
Ci
Cf
Ci
Cf
Vref
Va
At the end of phase F2:
Y.-M. Lin, B. Kim, and P. R. Gray, “A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-um
CMOS,” IEEE J. Solid-State Circuits, vol. 26, pp. 628–636, Apr. 1991
26. 26
Delta-Sigma Based Trimming Technique
Calibration only when
The error term in this case has a
constant sign
This is an fully background
technique
1
Ctrl
if
)
1
(
)
2
(
1
1
2
0
Ctrl
if
)
1
(
)
2
(
Vref
b
Vin
Vout
Vref
b
Vin
Vout
Vref
b
Vin
Vout
Seung-Tak Ryu, Sourja Ray, Bang-Sup Song, Gyu-Hyeong Cho, and Kanti Bacrania ,"A 14-b Linear
Capacitor Self-Trimming Pipelined ADC", IEEE Journal of Solid-State Circuits, VOL. 39, NO. 11,
November 2004
-
+
F2
F1
F1
F2
Vin
bi*Vref
From DAC
C
C*(1+)
Va
Vout
F1
Ctrl=(bi=1)*(PRN=1)
Ctrl
Ctrl
Ctrl
Ctrl
bi = -1, 0, +1
PRN = -1, +1
bi
PRN
Generator
Delta-Sigma
Polarity Detector
And Control
bi
0
i
b
27. 27
Benefits & Limitations of Trimming
If we implement a 3 bit trimming we can gain ~ 2 bits over the
matching given by the capacitors
The price of trimming is paid in
- Complexity
- Power
- Increased sensitivity to parasitic capacitance / leakage
Trimming should be used only for the first stages of the pipe-line ADC
to get closer to the thermal limited capacitor size
28. 28
Digital Calibration by the Precision Bootstrapping Algorithm
(in pipe-line ADC) (1)
- This is an off-line digital
static calibration technique
- The analog calibration
source is a DC voltage -
advantage
- The control machine for the
training sequence is
complicated
E. G. Soenen and R. L. Geiger, “An architecture and an algorithm for fully digital correction of monolithic pipelined ADC’s,” IEEE Trans. Circuits
Syst. II, vol. 42, pp. 143–153, Mar. 1995.
Vin
Stage L
Vres1
Vresi+1
Nout
Encoder
Vref1
Vrefk
Vref2
+
-
gi
ni (-ki/2, ki/2)
Vdac (ki+1 levels)
Flash
ki comparators
T&H Amplifier
nL
VresL
Stage 1
Stage L-1
nL-1
VresL-1
Stage i
ni n1
Vresi
Vresi
Stage i
DAC
Digital Correction
Calibrate
ncal
Vfix
wL
LUT LUT
LUT
LUT
w1
wi
wL-1
29. 29
Effect and Limitations of Fully Digital Calibration
The output of the ADC is a higher
resolution representation but the
decision points are the same as for an
un-calibrated ADC.
Calibrated
Uncalibrated
Nout
Vin
0
1
2
3
4
5
6
7
Decision Points
v0 v7
v6
v5
v4
v3
v2
v1
INL is improved but DNL not and
even non-monotone errors can
occur.
Digital Calibration by the Precision Bootstrapping Algorithm
(in pipe-line ADC) (2)
30. 30
Digital Calibration with State Space Error Table
ADC Z-1
Vin
Lookup
Table (LUT)
Address
2N bits
Nout(i)
Nout(i-1)
Nout_corrected
N bits
> N bits
Correction Phase
- This is an off-line digital
dynamic calibration technique
- The analog calibration source
is a known-statistics signal
source
- Theoretically higher order
dynamic calibrations are
possible
J . Tsimbinos K,.V. Lever “Improved error-table compensation of A/D converters” IEE Proc.-Circuits
Devices Syst., Vol. 144, No 6, December 1997
ADC Z-1
Lookup
Table (LUT)
Address
2N bits
Nout(i)
Nout(i-1)
N_estimate
N bits
> N bits
Calibration
Source
Analysis Engine
Calibration Phase
