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All-Digital Phase Lock Loop Imran Bashir “The Lab Guy” March 10 th , 2009
Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL ...
All-Digital PLL (ADPLL) References [1], [3] -  Bogdan Staszewski,  John Wallberg   1 3 4 2 ADPLL operates in  phase   doma...
Digitally-Controlled Oscillator Core <ul><li>Cross coupled NMOS pair </li></ul><ul><li>Three banks of capacitors: PB(MIM),...
Digitally-Controlled Oscillator Core The C-V curve of the MOS can have a large linear  range which is function of the DCO ...
DCO: Design Considerations <ul><li>Given: </li></ul><ul><li>f = 4 GHz, C = 1pF,  δ C = 1.5 fF </li></ul><ul><li>Then:  δ f...
DCO  ΣΔ <ul><li>MASH-3 structure </li></ul><ul><li>Order: 1 st  (N=1), 2 nd  (N=2) </li></ul><ul><li>Configurable clock, D...
DCO  ΣΔ : Design Considerations Composite ΣΔ Noise ↑, N  ↑ , M  ↓ ,   TB size ↑, f CLK  ↓ Critical parameters: M, CLK, N, ...
DCO  ΣΔ : Design Considerations Effect of SD order (N) M = 10,  Δ f = 30kHz,  f CLK  = 450MHz   N = 1   N = 2   N ↑ , L SD...
DCO  ΣΔ : Design Considerations Effect of Fractional Word Length (M) N = 2,  Δ f = 30kHz,  f CLK  = 450MHz   M = 2   M = 1...
DCO  ΣΔ : Design Considerations Effect of Capacitor Size ( Δ f) M = 10,  N = 2,  f CLK  = 450MHz   Δ f = 10kHz Δ f = 30kHz...
DCO  ΣΔ : Design Considerations Effect of  ΣΔ  Clock ( f CLK ) M = 10,  N = 2,  Δ f = 30kHz f CLK  = 225MHz   f CLK  = 450...
DCO  ΣΔ : Final Design M = 10,  N = 2,  Δ f = 30kHz,  f CLK  = 450MHz (Div-4)   Simulation Measurement <ul><li>Root cause ...
Phase Detector CKR = Re-timed FREF CKV = DCO clock
Phase Detector Integer Error Correction Reference [6] -  Bogdan Staszewski Φ  = 3  Φ  = 0  Modulo-16 N = 10 Error Resoluti...
Time-to-digital Converter (TDC) <ul><li>Quantized phase detector with resolution of 20 ps </li></ul><ul><li>DCO clock pass...
Time-to-digital Converter (TDC)
Time-to-digital Converter (TDC)
TDC: Important Concepts <ul><li>ε  =  Φ E  for –ve phase error </li></ul><ul><li>ε  ≠  Φ E  for +ve phase error </li></ul>...
TDC: Important Concepts Effect of DCO Frequency ADPLL Frequency  ↓ # of Inverters  ↑ Current consumption ↑
TDC: Important Concepts Effect of Inverter Delay Δ t inv   ↓ TDC Quantization Noise  ↓ # of Inverters (L) ↑ Current consum...
Digital Phase Error Signal: PHE <ul><li>The phase error signal PHE is the output of the loop’s phase detector </li></ul><u...
Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL ...
Noise Modeling in ADPLL References [1], [3] -  Bogdan Staszewski,  John Wallberg   Loop parameters   1-4
Noise Modeling in ADPLL <ul><li>Only three noise sources </li></ul><ul><ul><li>Frequency reference – low pass </li></ul></...
Noise Modeling in ADPLL <ul><li>Type-II 6 th -order PLL </li></ul><ul><li>Settings:    = 2 -7 ,    = 2 -15 ,    = 2 -[3...
Noise Modeling in ADPLL Tip: When even debugging spur source, study the effect of loop bandwidth on spur level. FREF harmo...
Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL ...
Tuning the ADPLL <ul><li>Scenario: </li></ul><ul><ul><li>Part is in the lab. Customer is waiting on 1 st  pass software in...
Tuning the ADPLL: Step 1 <ul><li>Define  two  most important parameters. </li></ul><ul><li>For GSM: </li></ul><ul><ul><li>...
Tuning the ADPLL: Step 2 <ul><li>Validate  the ADPLL model. </li></ul>ADPLL MATLAB Model Inverter Delay Δ t inv 1. FREF 2....
Tuning the ADPLL: Step 2 -119dBc/Hz -119dBc/Hz PN @ 400kHz - 64-kHz 0-dB CL BW - 13.7dB Gain Margin 0.9 ° 1.1 ° PTE - -36d...
Tuning the ADPLL: Step 3 <ul><li>Using the validated model, determine possible settings of  α ,  ρ , and  λ   with a compa...
Loop Setting 1 <ul><li>α =6,  ρ =14,  λ =0x2344 </li></ul><ul><li>0-dB close loop BW = 120-kHz, PM=47°, GM=15dB, CL @ 400k...
Loop Setting 1 <ul><li>α =6,  ρ =14,  λ =0x2344 </li></ul><ul><li>0-dB close loop BW = 120-kHz, PM=47°, GM=15dB, CL @ 400k...
Loop Setting 2 <ul><li>α =7,  ρ =16,  λ =0x3555 </li></ul><ul><li>0-dB close loop BW = 64-kHz, PM=44°, GM=14dB, CL @ 400kH...
Loop Setting 2 <ul><li>α =7,  ρ =16,  λ =0x3555 </li></ul><ul><li>0-dB close loop BW = 64-kHz, PM=44°, GM=14dB, CL @ 400kH...
Loop Setting 3 <ul><li>α =8,  ρ =17,  λ =0x3335 </li></ul><ul><li>0-dB close loop BW = 32-kHz, PM=43°, GM=20dB, CL @ 400kH...
Loop Setting 3 <ul><li>α =8,  ρ =17,  λ =0x3335 </li></ul><ul><li>0-dB close loop BW = 32-kHz, PM=43°, GM=20dB, CL @ 400kH...
Tuning the ADPLL: Step 4 <ul><li>Set the ADPLL bandwidth </li></ul><ul><ul><li>Narrow enough such that 400-kHz offset is d...
Tuning the ADPLL: Step 5 <ul><li>Check loop stability: Apply step in FREF </li></ul>DFT features in ADPLL allows to look a...
Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL ...
DCO Capacitor Mismatch <ul><li>Purpose: </li></ul><ul><ul><li>Natural mismatches  =  variability within the unit-weighted ...
DCO Capacitor Mismatch Compensation <ul><li>Each experiment consists of 1500 trials. </li></ul><ul><li>Each trial is a mea...
ΣΔ  Noise on DCO <ul><li>Spectral growth at offsets between 300kHz – 5MHz from the carrier  -> Marginal or failing spectru...
ΣΔ  Noise on DCO <ul><li>Periodic behavior of RMS phase error and 400kHz modulated spectrum with delay. </li></ul><ul><li>...
RF to FREF Interference <ul><li>ADPLL’s F ref  clock jittered when  F TX  = N   F ref   ( “integer channel”):  Transmitte...
DCO Pulling <ul><li>Issue: GSM Peak PE > 10 ˚ </li></ul><ul><li>Root Cause: </li></ul><ul><ul><li>There is excessive drift...
DCO Pulling: Solution α =7,  ρ =16,  λ =0x3555 Loop Bandwidth = 64-kHz Phase margin = 44 ˚ Gain margin = 13.7 dB α =5,  ρ ...
DCO Pulling: Measurement Results
DCO Pulling: Measurement Results <ul><li>Max RMS PE & Peak PE improvement </li></ul>Default Worst case DOE part @ 1880MHz ...
Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL ...
Characteristics of Calibration & Compensation Processes <ul><li>Calibration: </li></ul><ul><ul><li>Sometimes performed in ...
DCO Gain Calibration & Compensation <ul><li>Estimation of oscillator modulation gain ( K DCO ) is critical  </li></ul><ul>...
DCO Gain Calibration & Compensation 40% Variation over Process & 15% Variation over Temperature
DCO Gain Calibration & Compensation
DCO Gain Calibration & Compensation Without calibration and compensation, the phase error of the transmitter will fail 3GP...
DCO Gain Calibration & Compensation Data Packet DCO Gain Estimation
TDC Calibration & Compensation <ul><li>Purpose:  </li></ul><ul><ul><li>TDC inverter delay varies over voltage, temperature...
TDC Calibration & Compensation Error needs to be within  ±2% to meet 3   RMS phase-error spec.
Calibration of DCO Current Problem Statement <ul><li>The oscillator noise performance varies over process and temperature....
Calibration of DCO Current Variation of DCO Phase Noise Operating beyond optimum bias setting effects the DCO reliability....
Calibration of DCO Current Proposed Solution <ul><li>Digital processing of ADPLL’s phase error signal  </li></ul><ul><li>N...
Calibration of DCO Current Validation of Proposed Solution Optimum DCO current   using PHE based estimation PHE based esti...
DCO Frequency Calibration & Compensation <ul><li>Purpose: </li></ul><ul><ul><li>Ensure that the ADPLL will lock reliably o...
DCO Frequency Calibration & Compensation The allocated time for   ADPLL lock may not be adequate given DCO center frequenc...
Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL ...
Motivation <ul><li>Cellular phone market volumes and competitiveness drive cost reduction </li></ul><ul><li>Test costs, as...
Noisy/Defective vs. Normal DCO  PTE is determined based on PHE based estimation of DCO noise. References [5] -  Oren Eliez...
Block Diagram for Cap. Test DCO phase capacitor toggling time domain PHE waveform H(S) References [5] -  Oren Eliezer, Imr...
Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL ...
Summary From a Wireless SoC Perspective <ul><li>Pro’s: </li></ul><ul><ul><li>Configurability </li></ul></ul><ul><ul><li>Si...
References <ul><li>Robert Bogdan Staszewski.  IWSOC-2005 Tutorial #4 – Wireless SoC:  Digital Radio Processor Alternative ...
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All Digital Phase Lock Loop 03 12 09

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Fundamentals of All-Digital Phase Lock Loop Used in Digital Radio Processor

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All Digital Phase Lock Loop 03 12 09

  1. 1. All-Digital Phase Lock Loop Imran Bashir “The Lab Guy” March 10 th , 2009
  2. 2. Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL for GSM? </li></ul><ul><li>Impairments </li></ul><ul><li>Calibration & Compensation </li></ul><ul><li>Built-In Self Test </li></ul><ul><li>Summary </li></ul>
  3. 3. All-Digital PLL (ADPLL) References [1], [3] - Bogdan Staszewski, John Wallberg 1 3 4 2 ADPLL operates in phase domain.
  4. 4. Digitally-Controlled Oscillator Core <ul><li>Cross coupled NMOS pair </li></ul><ul><li>Three banks of capacitors: PB(MIM), AB(MOS), TB(MOS) </li></ul><ul><ul><li>Coarse Tuning: PB, AB </li></ul></ul><ul><ul><li>Fine Tuning/Modulation: TB, TB operated by ΣΔ </li></ul></ul><ul><li>Operates on current limiting scheme. </li></ul>OSCM OSCP
  5. 5. Digitally-Controlled Oscillator Core The C-V curve of the MOS can have a large linear range which is function of the DCO swing.
  6. 6. DCO: Design Considerations <ul><li>Given: </li></ul><ul><li>f = 4 GHz, C = 1pF, δ C = 1.5 fF </li></ul><ul><li>Then: δ f = 3 MHz -> PB Step Size </li></ul><ul><li>If total number of PB capacitors = 128 </li></ul><ul><li>Tuning Range (DCO)= 128 x 3 MHz = 384 MHz </li></ul><ul><li>Tuning Range (div-2)= 384 /2 = 192 MHz </li></ul><ul><li>Tuning Range (div-4)= 384 /4 = 96 MHz </li></ul><ul><li>Low Band: f min =824.2 MHz, f max =958.8 MHz, Δ f LB =134.6 MHz </li></ul><ul><li>High Band: f min =1710.2 MHz, f max =1989.8 MHz, Δ f HB =279.6 MHz </li></ul>-> Not enough for GSM } Need to have control on inductance to increase tuning range. TB is designed with enough capacitors to support FM in presence of DCO drift.
  7. 7. DCO ΣΔ <ul><li>MASH-3 structure </li></ul><ul><li>Order: 1 st (N=1), 2 nd (N=2) </li></ul><ul><li>Configurable clock, Div-1/2/4/8 </li></ul><ul><li>Critical parameters: M, CLK, N, δ C </li></ul>N=1, WFrac = 0.5 Duty Cycle = 50% C eff = δ C/2
  8. 8. DCO ΣΔ : Design Considerations Composite ΣΔ Noise ↑, N ↑ , M ↓ , TB size ↑, f CLK ↓ Critical parameters: M, CLK, N, δ C -> Δ f Due to resolution of digital input (M) Due to size of capacitor Δ f Reference [3] - Bogdan Staszewski, Chih-Ming Hung
  9. 9. DCO ΣΔ : Design Considerations Effect of SD order (N) M = 10, Δ f = 30kHz, f CLK = 450MHz N = 1 N = 2 N ↑ , L SD,M Х , L SD, Δ f lower between 1-10M & higher @ 100MHz Composite response (solid black line) DOES NOT include natural DCO phase noise!
  10. 10. DCO ΣΔ : Design Considerations Effect of Fractional Word Length (M) N = 2, Δ f = 30kHz, f CLK = 450MHz M = 2 M = 10 Composite response (solid black line) DOES NOT include natural DCO phase noise! M ↑ , L SD,M ↑ , L SD, Δ f X, Current consumption ↑
  11. 11. DCO ΣΔ : Design Considerations Effect of Capacitor Size ( Δ f) M = 10, N = 2, f CLK = 450MHz Δ f = 10kHz Δ f = 30kHz Δ f ↑ , L SD,M ↑ , L SD, Δ f ↑ Composite response (solid black line) DOES NOT include natural DCO phase noise!
  12. 12. DCO ΣΔ : Design Considerations Effect of ΣΔ Clock ( f CLK ) M = 10, N = 2, Δ f = 30kHz f CLK = 225MHz f CLK = 450MHz f CLK ↑ , L SD,M X , L SD, Δ f ↑ Composite response (solid black line) DOES NOT include natural DCO phase noise!
  13. 13. DCO ΣΔ : Final Design M = 10, N = 2, Δ f = 30kHz, f CLK = 450MHz (Div-4) Simulation Measurement <ul><li>Root cause of discrepancies -> ideal assumptions in model </li></ul><ul><li>Skew b/w SD output pins </li></ul><ul><li>SD capacitors not similar </li></ul><ul><li>Malfunction @ high speeds </li></ul>1.80GHz 900MHz 450MHz 225MHz
  14. 14. Phase Detector CKR = Re-timed FREF CKV = DCO clock
  15. 15. Phase Detector Integer Error Correction Reference [6] - Bogdan Staszewski Φ = 3 Φ = 0 Modulo-16 N = 10 Error Resolution of Integer Correction = ±0.5 · DCO Cycle
  16. 16. Time-to-digital Converter (TDC) <ul><li>Quantized phase detector with resolution of 20 ps </li></ul><ul><li>DCO clock passes through the inverter chain </li></ul><ul><li>Delayed outputs are sampled by FREF </li></ul>
  17. 17. Time-to-digital Converter (TDC)
  18. 18. Time-to-digital Converter (TDC)
  19. 19. TDC: Important Concepts <ul><li>ε = Φ E for –ve phase error </li></ul><ul><li>ε ≠ Φ E for +ve phase error </li></ul><ul><li>ε = 1 – TR/TV </li></ul><ul><ul><li>TV is the number of inverters covering 1 full CKV cycle </li></ul></ul><ul><ul><li>TV has to be know -> Requires compensation </li></ul></ul>
  20. 20. TDC: Important Concepts Effect of DCO Frequency ADPLL Frequency ↓ # of Inverters ↑ Current consumption ↑
  21. 21. TDC: Important Concepts Effect of Inverter Delay Δ t inv ↓ TDC Quantization Noise ↓ # of Inverters (L) ↑ Current consumption ↑
  22. 22. Digital Phase Error Signal: PHE <ul><li>The phase error signal PHE is the output of the loop’s phase detector </li></ul><ul><li>Computed and captured digitally </li></ul><ul><li>The processing (rms calculation) is software based. </li></ul>PHE serves as a ‘noise meter’ in DRP.
  23. 23. Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL for GSM? </li></ul><ul><li>Impairments </li></ul><ul><li>Calibration & Compensation </li></ul><ul><li>Built-In Self Test </li></ul><ul><li>Summary </li></ul>
  24. 24. Noise Modeling in ADPLL References [1], [3] - Bogdan Staszewski, John Wallberg Loop parameters  1-4
  25. 25. Noise Modeling in ADPLL <ul><li>Only three noise sources </li></ul><ul><ul><li>Frequency reference – low pass </li></ul></ul><ul><ul><li>TDC quantization – low pass </li></ul></ul><ul><ul><li>DCO oscillator – high pass </li></ul></ul>References [1], [3] - Bogdan Staszewski, John Wallberg
  26. 26. Noise Modeling in ADPLL <ul><li>Type-II 6 th -order PLL </li></ul><ul><li>Settings:  = 2 -7 ,  = 2 -15 ,  = 2 -[3 3 3 4] </li></ul><ul><li>Provides 33 dB of attenuation at 400 kHz </li></ul><ul><li>Provides 40 dB/dec filtering of 1/f DCO noise </li></ul>FREF / TDC path DCO path References [1], [3] - Bogdan Staszewski, John Wallberg f BW ↑ corner moves f BW ↑ corner moves
  27. 27. Noise Modeling in ADPLL Tip: When even debugging spur source, study the effect of loop bandwidth on spur level. FREF harmonic spur Blue Trace = Yellow Trace = DCO Supply spur Blue Trace = Yellow Trace = Wide Loop Narrow Loop Wide Loop Narrow Loop
  28. 28. Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL for GSM? </li></ul><ul><li>Impairments </li></ul><ul><li>Calibration & Compensation </li></ul><ul><li>Built-In Self Test </li></ul><ul><li>Summary </li></ul>
  29. 29. Tuning the ADPLL <ul><li>Scenario: </li></ul><ul><ul><li>Part is in the lab. Customer is waiting on 1 st pass software in order to make a phone call. All TX blocks are functional but before running the first round of regression, the loop parameters α , ρ , and λ need to be finalized. </li></ul></ul><ul><li>Given: </li></ul><ul><ul><li>All system and design guys are busy making press releases and working on journal publications and upcoming conferences. So its all up to “The Lab Guy.” </li></ul></ul>
  30. 30. Tuning the ADPLL: Step 1 <ul><li>Define two most important parameters. </li></ul><ul><li>For GSM: </li></ul><ul><ul><li>Phase Trajectory Error </li></ul></ul><ul><ul><li>Modulated spectrum @ 400kHz </li></ul></ul>
  31. 31. Tuning the ADPLL: Step 2 <ul><li>Validate the ADPLL model. </li></ul>ADPLL MATLAB Model Inverter Delay Δ t inv 1. FREF 2. TDC 3. DCO + Composite Simulated ADPLL spectrum Measure noise sources Simulated vs. Measured GMSK Filter Composite Simulated Modulated spectrum X 3 L FREF (dBc/Hz) f 3 L DCO (dBc/Hz) f 2
  32. 32. Tuning the ADPLL: Step 2 -119dBc/Hz -119dBc/Hz PN @ 400kHz - 64-kHz 0-dB CL BW - 13.7dB Gain Margin 0.9 ° 1.1 ° PTE - -36dB CL gain @ 400kHz -67dB -67.5dB MODSPEC @ 400kHz - 44 ° Phase Margin Measured Simulated Parameter 0.1 ° -74 DCXO 1.1 ° -49.7 Composite 1.1 ° -50 DCO 0.3 ° -62 TDC RMS PE dB Noise Source
  33. 33. Tuning the ADPLL: Step 3 <ul><li>Using the validated model, determine possible settings of α , ρ , and λ with a comparable phase margin but wide range of 0-dB close loop (CL) bandwidth </li></ul>PM is comparable between all settings.
  34. 34. Loop Setting 1 <ul><li>α =6, ρ =14, λ =0x2344 </li></ul><ul><li>0-dB close loop BW = 120-kHz, PM=47°, GM=15dB, CL @ 400kHz=-17dB </li></ul>RMS PE is low since composite close in noise is low. ADPLL 400-kHz phase noise is dominated by the TDC and DCO @ 400kHz.
  35. 35. Loop Setting 1 <ul><li>α =6, ρ =14, λ =0x2344 </li></ul><ul><li>0-dB close loop BW = 120-kHz, PM=47°, GM=15dB, CL @ 400kHz=-17dB </li></ul>ADPLL 400-kHz phase noise is dominated by the TDC and DCO @ 400kHz. Open Loop Close Loop Modulated Open Loop Close Loop Modulated
  36. 36. Loop Setting 2 <ul><li>α =7, ρ =16, λ =0x3555 </li></ul><ul><li>0-dB close loop BW = 64-kHz, PM=44°, GM=14dB, CL @ 400kHz=-36dB </li></ul>RMS PE is moderate since composite close in noise is moderate. ADPLL 400-kHz phase noise is dominated by the DCO @ 400kHz.
  37. 37. Loop Setting 2 <ul><li>α =7, ρ =16, λ =0x3555 </li></ul><ul><li>0-dB close loop BW = 64-kHz, PM=44°, GM=14dB, CL @ 400kHz=-36dB </li></ul>ADPLL 400-kHz phase noise is dominated by the DCO @ 400kHz. Open Loop Close Loop Modulated Open Loop Close Loop Modulated
  38. 38. Loop Setting 3 <ul><li>α =8, ρ =17, λ =0x3335 </li></ul><ul><li>0-dB close loop BW = 32-kHz, PM=43°, GM=20dB, CL @ 400kHz=-42dB </li></ul>RMS PE is high since composite close in noise is high. ADPLL 400-kHz phase noise is dominated by the DCO @ 400kHz.
  39. 39. Loop Setting 3 <ul><li>α =8, ρ =17, λ =0x3335 </li></ul><ul><li>0-dB close loop BW = 32-kHz, PM=43°, GM=20dB, CL @ 400kHz=-42dB </li></ul>ADPLL 400-kHz phase noise is dominated by the DCO @ 400kHz. Open Loop Close Loop Modulated Open Loop Close Loop Modulated
  40. 40. Tuning the ADPLL: Step 4 <ul><li>Set the ADPLL bandwidth </li></ul><ul><ul><li>Narrow enough such that 400-kHz offset is dominated by DCO exclusively. </li></ul></ul><ul><ul><li>Wide enough such that DCO noise does not start degrading PTE. </li></ul></ul>This number is not close to -70dB due to presence of impairment DCO capacitor mismatch. Set the ADPLL bandwidth in this region. PM is comparable between all settings. 400kHz MODSPEC [dB] DCO Dominant Contributor DCO + TDC 0-dB Loop Bandwidth [kHz] RMS Phase Error [deg]
  41. 41. Tuning the ADPLL: Step 5 <ul><li>Check loop stability: Apply step in FREF </li></ul>DFT features in ADPLL allows to look at ADPLL output OTW or digital phase error PHE.
  42. 42. Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL for GSM? </li></ul><ul><li>Impairments </li></ul><ul><li>Calibration & Compensation </li></ul><ul><li>Built-In Self Test </li></ul><ul><li>Summary </li></ul>
  43. 43. DCO Capacitor Mismatch <ul><li>Purpose: </li></ul><ul><ul><li>Natural mismatches = variability within the unit-weighted varactors </li></ul></ul><ul><ul><li>As capacitors are turned on and off, distortion will be evident in the resultant frequency </li></ul></ul><ul><li>Solution: </li></ul><ul><ul><li>Dynamic element matching (DEM) employed to improve digital-to-frequency conversion linearity </li></ul></ul>Progression of time (8 cycles shown ) 8x8 varactor encoding matrix:
  44. 44. DCO Capacitor Mismatch Compensation <ul><li>Each experiment consists of 1500 trials. </li></ul><ul><li>Each trial is a measurement over 200 bursts. </li></ul>Digital activity in DEM results in spurs.
  45. 45. ΣΔ Noise on DCO <ul><li>Spectral growth at offsets between 300kHz – 5MHz from the carrier -> Marginal or failing spectrum performance </li></ul><ul><li>The extent of degradation is a function of the phase of ΣΔ clock adjusted by flyback delay circuit. </li></ul>
  46. 46. ΣΔ Noise on DCO <ul><li>Periodic behavior of RMS phase error and 400kHz modulated spectrum with delay. </li></ul><ul><li>Solution </li></ul><ul><ul><li>Flyback delay calibration and compensation -> Reference [7] </li></ul></ul><ul><ul><li>Reduce ΣΔ clock </li></ul></ul>
  47. 47. RF to FREF Interference <ul><li>ADPLL’s F ref clock jittered when F TX = N  F ref ( “integer channel”): Transmitter often fails its phase-error spec (3  RMS) </li></ul><ul><ul><li>Severity changes when ADPLL is relocked (‘state’ dependent) </li></ul></ul><ul><ul><li>Does not depend much on output power, but is impacted by the CKV divider and by the TX divider (resetting it affects the performance) </li></ul></ul><ul><ul><li>More than one aggressor involved (challenging debugging…) </li></ul></ul>References [8] - Oren Eliezer
  48. 48. DCO Pulling <ul><li>Issue: GSM Peak PE > 10 ˚ </li></ul><ul><li>Root Cause: </li></ul><ul><ul><li>There is excessive drift in DCO before and during TX burst (payload). </li></ul></ul><ul><ul><li>Due to Narrow loop BW, the ADPLL is not able to track the DCO and therefore a maximum peak phase error is experienced at the beginning of the burst. </li></ul></ul>OTW Over TX Burst DCO drift is experienced even before TX payload
  49. 49. DCO Pulling: Solution α =7, ρ =16, λ =0x3555 Loop Bandwidth = 64-kHz Phase margin = 44 ˚ Gain margin = 13.7 dB α =5, ρ =14, λ =0x2334 Loop Bandwidth = 233-kHz Phase margin = 49 ˚ Gain margin = 11.1 dB Dynamic adjustment of ADPLL bandwidth between 64-kHz and 233-kHz.
  50. 50. DCO Pulling: Measurement Results
  51. 51. DCO Pulling: Measurement Results <ul><li>Max RMS PE & Peak PE improvement </li></ul>Default Worst case DOE part @ 1880MHz Bandwidth Adjustment Worst case DOE part @ 1880MHz
  52. 52. Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL for GSM? </li></ul><ul><li>Impairments </li></ul><ul><li>Calibration & Compensation </li></ul><ul><li>Built-In Self Test </li></ul><ul><li>Summary </li></ul>
  53. 53. Characteristics of Calibration & Compensation Processes <ul><li>Calibration: </li></ul><ul><ul><li>Sometimes performed in factory after assembly (when external measurements needed) </li></ul></ul><ul><ul><li>Certain calibrations are done at power-up (internal measurements) </li></ul></ul><ul><ul><li>Typically performed using on-chip digital logic and/or software </li></ul></ul><ul><ul><li>Primary purpose is to account for process variations </li></ul></ul><ul><ul><li>Sometimes done only once in a lifetime of the system </li></ul></ul><ul><ul><li>Results are stored in memory to be used for compensation </li></ul></ul><ul><li>Compensation: </li></ul><ul><ul><li>Performed before or while signal is transmitted or received </li></ul></ul><ul><ul><li>Performed using hardware and/or software </li></ul></ul><ul><ul><li>Primary focus is to account for environmental variations such as temperature changes etc. </li></ul></ul><ul><ul><li>Process is invoked for each packet transmitted/received or periodically </li></ul></ul>
  54. 54. DCO Gain Calibration & Compensation <ul><li>Estimation of oscillator modulation gain ( K DCO ) is critical </li></ul><ul><ul><li>RX: sets the loop bandwidth and affects noise performance </li></ul></ul><ul><ul><li>TX: sets transfer function of the direct frequency modulation path </li></ul></ul><ul><ul><li>Tolerated gain estimation error: several % (GSM, Bluetooth) </li></ul></ul><ul><ul><li>Calibration routine for K DCO runs before each packet </li></ul></ul>
  55. 55. DCO Gain Calibration & Compensation 40% Variation over Process & 15% Variation over Temperature
  56. 56. DCO Gain Calibration & Compensation
  57. 57. DCO Gain Calibration & Compensation Without calibration and compensation, the phase error of the transmitter will fail 3GPP GSM specification. GSM 3GPP limit (5 degrees) Measured Simulated Target specification (3 degrees)
  58. 58. DCO Gain Calibration & Compensation Data Packet DCO Gain Estimation
  59. 59. TDC Calibration & Compensation <ul><li>Purpose: </li></ul><ul><ul><li>TDC inverter delay varies over voltage, temperature, and process. </li></ul></ul><ul><ul><li>The large variations can degrade system performance. </li></ul></ul><ul><ul><li>Calibration must be accurate within ±2% to comply with GSM spec. </li></ul></ul>9% Variation over Temperature 50% Variation over Process Weak Process Nominal Process Strong Process <ul><li>Solution: </li></ul><ul><ul><li>Internal digital measurements of inverter delay </li></ul></ul>
  60. 60. TDC Calibration & Compensation Error needs to be within ±2% to meet 3  RMS phase-error spec.
  61. 61. Calibration of DCO Current Problem Statement <ul><li>The oscillator noise performance varies over process and temperature. </li></ul><ul><li>These variations can be compensated by adjusting the bias setting. </li></ul><ul><li>Strong process -> ibias ↓ </li></ul><ul><li>Temperature ↑ -> ibias ↑ </li></ul><ul><li>Need a sensor for estimating DCO noise in order to calibrate bias setting </li></ul>
  62. 62. Calibration of DCO Current Variation of DCO Phase Noise Operating beyond optimum bias setting effects the DCO reliability. 400kHz Offset
  63. 63. Calibration of DCO Current Proposed Solution <ul><li>Digital processing of ADPLL’s phase error signal </li></ul><ul><li>Noise of DCO is digitized </li></ul><ul><li>ADPLL operation in closed loop with narrow loop bandwidth. </li></ul>
  64. 64. Calibration of DCO Current Validation of Proposed Solution Optimum DCO current using PHE based estimation PHE based estimation of DCO noise correlates with the measured DCO integrated noise.
  65. 65. DCO Frequency Calibration & Compensation <ul><li>Purpose: </li></ul><ul><ul><li>Ensure that the ADPLL will lock reliably over all process corners and temperatures. </li></ul></ul><ul><li>Solution: </li></ul><ul><ul><li>Store capacitor code in memory and retrieve before locking to a channel. </li></ul></ul>Variation in DCO center frequency over process can be as high as 2% at 1.8GHz operation.
  66. 66. DCO Frequency Calibration & Compensation The allocated time for ADPLL lock may not be adequate given DCO center frequency variation.
  67. 67. Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL for GSM? </li></ul><ul><li>Impairments </li></ul><ul><li>Calibration & Compensation </li></ul><ul><li>Built-In Self Test </li></ul><ul><li>Summary </li></ul>
  68. 68. Motivation <ul><li>Cellular phone market volumes and competitiveness drive cost reduction </li></ul><ul><li>Test costs, as part of the production costs, must be minimized </li></ul><ul><ul><li>Use very low cost testers (VLCT) </li></ul></ul><ul><ul><li>Test many devices in parallel: massive multi-site testing (MMST) </li></ul></ul><ul><ul><li>Implement built-in self-testing (BIST) </li></ul></ul><ul><li>The system-on-chip (SoC) has resources available for BIST at massproduction (processor, memory, data converters…) </li></ul><ul><li>BIST allows for concurrency  reduction in test time </li></ul><ul><li>BIST can increase coverage “at probe” (before packaging)  increase in yield </li></ul><ul><li>DRP architecture allows for simple digital signal processing based BIST </li></ul>
  69. 69. Noisy/Defective vs. Normal DCO PTE is determined based on PHE based estimation of DCO noise. References [5] - Oren Eliezer, Imran Bashir
  70. 70. Block Diagram for Cap. Test DCO phase capacitor toggling time domain PHE waveform H(S) References [5] - Oren Eliezer, Imran Bashir
  71. 71. Outline <ul><li>All-Digital PLL (ADPLL) </li></ul><ul><li>Noise Modeling in ADPLL </li></ul><ul><li>How to tune the ADPLL for GSM? </li></ul><ul><li>Impairments </li></ul><ul><li>Calibration & Compensation </li></ul><ul><li>Built-In Self Test </li></ul><ul><li>Summary </li></ul>
  72. 72. Summary From a Wireless SoC Perspective <ul><li>Pro’s: </li></ul><ul><ul><li>Configurability </li></ul></ul><ul><ul><li>Size </li></ul></ul><ul><ul><li>Design for Test (DFT) </li></ul></ul><ul><ul><li>Fast lock time 10 μ s-20 μ s </li></ul></ul><ul><ul><li>No over-head </li></ul></ul><ul><li>Con’s: </li></ul><ul><ul><li>High Risk: </li></ul></ul><ul><ul><ul><li>DCO ΣΔ Dithering of capacitor </li></ul></ul></ul><ul><ul><ul><li>Quantization noise of PPA </li></ul></ul></ul><ul><ul><li>Low Risk: </li></ul></ul><ul><ul><ul><li>Spurious Emissions </li></ul></ul></ul><ul><ul><ul><li>Current consumption </li></ul></ul></ul>For EDGE/WCDMA
  73. 73. References <ul><li>Robert Bogdan Staszewski. IWSOC-2005 Tutorial #4 – Wireless SoC: Digital Radio Processor Alternative to Conventional RF </li></ul><ul><li>C. M. Hung, R. B. Staszewski, N. Barton, M. C. Lee, and D. Leipold,``A digitally controlled oscillator system for SAW-less transmitters in cellular handsets,'' IEEE Journal of Solid-State Circuits , vol. 41, no. 5, pp. 1160--1170, May 2006. </li></ul><ul><li>R. B. Staszewski, C. M. Hung, N. Barton, M. C. Lee, and D. Leipold,``A Digitally Controlled Oscillator in a 90nm Digital CMOS Process for Mobile Phones,'' IEEE Journal of Solid-State Circuits , vol. 40, no. 11, pp. 2203-2211, Nov. 2005. </li></ul><ul><li>R. B. Staszewski, J. L. Wallberg, S. Rezeq, C. M. Hung, O. E. Eliezer, S. K. Vemulapalli, C. Fernando, K. Maggio, R. Staszewski, N. Barton, M. C. Lee, P. Cruise, M. Entezari, K. Muhammad, and D. Leipold, “All-Digital PLL and Transmitter for Mobile Phones” , IEEE Journal of Solid-State Circuits , vol. 40, no. 12, December 2005. </li></ul><ul><li>O. Eliezer, I. Bashir, R. B. Staszewski, and P. T. Balsara, ``Built-in Self Testing of a DRP-Based GSM Transmitter'', Proc. of IEEE RFIC Symposium pp. 339-342, June 2007. </li></ul><ul><li>R. B. Staszewski, All Digital Frequency Synthesizers in Deep-Submicron CMOS, Wiley, NJ, 2006. </li></ul><ul><li>I. Bashir, ON-CHIP CALIBRATION AND COMPENSATION TECHNIQUES FOR WIRELESS SoCs, MS. Thesis, University of Texas at Dallas, 2008. </li></ul><ul><li>O. Eliezer, R. B. Staszewski, S. Bhatara, I. Bashir, and P. T. Balsara,`` Active Mitigation of Induced Phase Distortion in a GSM SoC,'' Proc. of IEEE RFIC Symposium, pp. 17-20, June 2008. </li></ul><ul><li>O. Eliezer, I. Bashir, “Digital Hardware and Software Based Mechanisms for Compensation and Calibration in Wireless SoCs,” Proc. of IEEE RFIC Symposium, “On-Chip Calibration, Compensation, and Filtering Techniques for Wireless SoCs,” Workshop, Session WSL-2, June 2008. </li></ul>

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