The document presents a new approach for transistor sizing in digital integrated circuits using the firefly algorithm. It first describes the firefly algorithm and its characteristics that make it suitable for optimization problems. Equations for power, delay, and power-delay product (PDP) of an inverter circuit are provided. A new design methodology is proposed that uses HSPICE simulation within a MATLAB optimization loop using the firefly algorithm to vary transistor widths and minimize PDP. This is done to improve over equation-based methods by directly incorporating non-linear transistor effects from simulation. The approach is applied to an inverter design and able to find optimized dimensions for low power and delay.
Using spectral radius ratio for node degreeIJCNCJournal
In this paper, we show that the spectral radius ratio for node degree could be used to analyze the variation of node degree during the evolution of complex networks. We focus on three commonly studied models of complex networks: random networks, scale-free networks and small-world networks. The spectral radius ratio for node degree is defined as the ratio of the principal (largest) eigenvalue of the adjacency matrix of a network graph to that of the average node degree. During the evolution of each of the above three categories of networks (using the appropriate evolution model for each category), we observe the spectral radius ratio for node degree to exhibit high-very high positive correlation (0.75 or above) to that of the
coefficient of variation of node degree (ratio of the standard deviation of node degree and average node degree). We show that the spectral radius ratio for node degree could be used as the basis to tune the operating parameters of the evolution models for each of the three categories of complex networks as well as analyze the impact of specific operating parameters for each model.
Firefly Algorithm to Opmimal Distribution of Reactive Power Compensation Units IJECEIAES
The issue of electric power grid mode of optimization is one of the basic directions in power engineering research. Currently, methods other than classical optimization methods based on various bio-heuristic algorithms are applied. The problems of reactive power optimization in a power grid using bio-heuristic algorithms are considered. These algorithms allow obtaining more efficient solutions as well as taking into account several criteria. The Firefly algorithm is adapted to optimize the placement of reactive power sources as well as to select their values. A key feature of the proposed modification of the Firefly algorithm is the solution for the multi-objective optimization problem. Algorithms based on a bio-heuristic process can find a neighborhood of global extreme, so a local gradient descent in the neighborhood is applied for a more accurate solution of the problem. Comparison of gradient descent, Firefly algorithm and Firefly algorithm with gradient descent is carried out.
APPROXIMATING NASH EQUILIBRIUM UNIQUENESS OF POWER CONTROL IN PRACTICAL WSNSIJCNCJournal
Transmission power has a major impact on link and communication reliability and network lifetime in Wireless Sensor Networks. We study power control in a multi-hop Wireless Sensor Network where nodes' communication interfere with each other. Our objective is to determine each node's transmission power level that will reduce the communication interference and keep energy consumption to a minimum. We propose a potential game approach to obtain the unique equilibrium of the network transmission power allocation. The unique equilibrium is located in a continuous domain. However, radio transceivers accept only discrete values for transmission power level setting. We study the viability and performance of mapping the continuous solution from the potential game to the discrete domain required by the radio. We demonstrate the success of our approach through TOSSIM simulation when nodes use the Collection Tree Protocol for routing the data. Also, we show results of our method from the Indriya testbed. We compare it with the case where the motes use Collection Tree Protocol with the maximum transmission power.
Enriched Firefly Algorithm for Solving Reactive Power Problemijeei-iaes
In this paper, Enriched Firefly Algorithm (EFA) is planned to solve optimal reactive power dispatch problem. This algorithm is a kind of swarm intelligence algorithm based on the response of a firefly to the light of other fireflies. In this paper, we plan an augmentation on the original firefly algorithm. The proposed algorithm extends the single population FA to the interacting multi-swarms by cooperative Models. The proposed EFA has been tested on standard IEEE 30 bus test system and simulation results show clearly the better performance of the proposed algorithm in reducing the real power loss.
Novel design of a fractional wavelet and its application to image denoisingjournalBEEI
This paper proposes a new wavelet family based on fractional calculus. The Haar wavelet is extended to fractional order by a generalization of the associated conventional low-pass filter using the fractional delay operator Z-D. The high-pass fractional filter is then designed by a simple modulation of the low-pass filter. In contrast, the scaling and wavelet functions are constructed using the cascade Daubechies algorithm. The regularity and orthogonality of the obtained wavelet basis are ensured by a good choice of the fractional filter coefficients. An application example is presented to illustrate the effectiveness of the proposed method. Thanks to the flexibility of the fractional filters, the proposed approach provides better performance in term of image denoising.
Discrete wavelet transform-based RI adaptive algorithm for system identificationIJECEIAES
In this paper, we propose a new adaptive filtering algorithm for system identifica- tion. The algorithm is based on the recursive inverse (RI) adaptive algorithm which suffers from low convergence rates in some applications; i.e., the eigenvalue spread of the autocorrelation matrix is relatively high. The proposed algorithm applies discrete-wavelet transform (DWT) to the input signal which, in turn, helps to overcome the low convergence rate of the RI algorithm with relatively small step-size(s). Different scenarios has been investigated in different noise environments in system identification setting. Experiments demonstrate the advantages of the proposed DWT recursive inverse (DWT-RI) filter in terms of convergence rate and mean-square-error (MSE) compared to the RI, discrete cosine transform LMS (DCT-LMS), discretewavelet transform LMS (DWT-LMS) and recursive-least-squares (RLS) algorithms under same conditions.
Optimum capacity allocation of distributed generation units using parallel ps...eSAT Journals
Abstract This paper proposes the application of Parallel Particle Swarm Optimization (PPSO) technique to find the optimal sizing of multiple DG(Distributed Generation) units in the radial distribution network by reduction in real power losses and enhancement in voltage profile. Message passing interface (MPI) is used for the parallelization of PSO. The initial population of PSO algorithm has been divided between the processors at run time. The proposed technique is tested on standard 123-bus test system and the obtained results show that the simulation time is significantly reduced and is concluded that parallelization helps in enhancing the performance of basic PSO. The procedure has been implemented in an environment in which OpenDSS (Open Distribution System Simulator) is driven from MATLAB. An adaptive weight particle swarm optimization algorithm has been developed in MATLAB , parallelization is achieved using MATLABMPI and the unbalanced three-phase distribution load flow (DLF) has been performed using Electric Power Research Institute’s (EPRI) open source tool OpenDSS. Index Terms: Distributed Generation, Message Passing Interface, Optimal Placement, Parallel Particle Swarm Optimisation
OPTIMIZED TASK ALLOCATION IN SENSOR NETWORKSZac Darcy
The document proposes an approach to optimize energy consumption in sensor networks. It allocates tasks to sensor nodes using a particle swarm optimization algorithm that considers energy for data communication between nodes. Simulation results show the proposed approach reduces energy consumption and increases network lifetime compared to existing approaches that only allocate tasks to cluster gateways. The key aspects of the proposed approach are using a cost function that includes communication energy in the task allocation algorithm and having nodes send combined data from neighboring nodes to reduce the number of messages.
Using spectral radius ratio for node degreeIJCNCJournal
In this paper, we show that the spectral radius ratio for node degree could be used to analyze the variation of node degree during the evolution of complex networks. We focus on three commonly studied models of complex networks: random networks, scale-free networks and small-world networks. The spectral radius ratio for node degree is defined as the ratio of the principal (largest) eigenvalue of the adjacency matrix of a network graph to that of the average node degree. During the evolution of each of the above three categories of networks (using the appropriate evolution model for each category), we observe the spectral radius ratio for node degree to exhibit high-very high positive correlation (0.75 or above) to that of the
coefficient of variation of node degree (ratio of the standard deviation of node degree and average node degree). We show that the spectral radius ratio for node degree could be used as the basis to tune the operating parameters of the evolution models for each of the three categories of complex networks as well as analyze the impact of specific operating parameters for each model.
Firefly Algorithm to Opmimal Distribution of Reactive Power Compensation Units IJECEIAES
The issue of electric power grid mode of optimization is one of the basic directions in power engineering research. Currently, methods other than classical optimization methods based on various bio-heuristic algorithms are applied. The problems of reactive power optimization in a power grid using bio-heuristic algorithms are considered. These algorithms allow obtaining more efficient solutions as well as taking into account several criteria. The Firefly algorithm is adapted to optimize the placement of reactive power sources as well as to select their values. A key feature of the proposed modification of the Firefly algorithm is the solution for the multi-objective optimization problem. Algorithms based on a bio-heuristic process can find a neighborhood of global extreme, so a local gradient descent in the neighborhood is applied for a more accurate solution of the problem. Comparison of gradient descent, Firefly algorithm and Firefly algorithm with gradient descent is carried out.
APPROXIMATING NASH EQUILIBRIUM UNIQUENESS OF POWER CONTROL IN PRACTICAL WSNSIJCNCJournal
Transmission power has a major impact on link and communication reliability and network lifetime in Wireless Sensor Networks. We study power control in a multi-hop Wireless Sensor Network where nodes' communication interfere with each other. Our objective is to determine each node's transmission power level that will reduce the communication interference and keep energy consumption to a minimum. We propose a potential game approach to obtain the unique equilibrium of the network transmission power allocation. The unique equilibrium is located in a continuous domain. However, radio transceivers accept only discrete values for transmission power level setting. We study the viability and performance of mapping the continuous solution from the potential game to the discrete domain required by the radio. We demonstrate the success of our approach through TOSSIM simulation when nodes use the Collection Tree Protocol for routing the data. Also, we show results of our method from the Indriya testbed. We compare it with the case where the motes use Collection Tree Protocol with the maximum transmission power.
Enriched Firefly Algorithm for Solving Reactive Power Problemijeei-iaes
In this paper, Enriched Firefly Algorithm (EFA) is planned to solve optimal reactive power dispatch problem. This algorithm is a kind of swarm intelligence algorithm based on the response of a firefly to the light of other fireflies. In this paper, we plan an augmentation on the original firefly algorithm. The proposed algorithm extends the single population FA to the interacting multi-swarms by cooperative Models. The proposed EFA has been tested on standard IEEE 30 bus test system and simulation results show clearly the better performance of the proposed algorithm in reducing the real power loss.
Novel design of a fractional wavelet and its application to image denoisingjournalBEEI
This paper proposes a new wavelet family based on fractional calculus. The Haar wavelet is extended to fractional order by a generalization of the associated conventional low-pass filter using the fractional delay operator Z-D. The high-pass fractional filter is then designed by a simple modulation of the low-pass filter. In contrast, the scaling and wavelet functions are constructed using the cascade Daubechies algorithm. The regularity and orthogonality of the obtained wavelet basis are ensured by a good choice of the fractional filter coefficients. An application example is presented to illustrate the effectiveness of the proposed method. Thanks to the flexibility of the fractional filters, the proposed approach provides better performance in term of image denoising.
Discrete wavelet transform-based RI adaptive algorithm for system identificationIJECEIAES
In this paper, we propose a new adaptive filtering algorithm for system identifica- tion. The algorithm is based on the recursive inverse (RI) adaptive algorithm which suffers from low convergence rates in some applications; i.e., the eigenvalue spread of the autocorrelation matrix is relatively high. The proposed algorithm applies discrete-wavelet transform (DWT) to the input signal which, in turn, helps to overcome the low convergence rate of the RI algorithm with relatively small step-size(s). Different scenarios has been investigated in different noise environments in system identification setting. Experiments demonstrate the advantages of the proposed DWT recursive inverse (DWT-RI) filter in terms of convergence rate and mean-square-error (MSE) compared to the RI, discrete cosine transform LMS (DCT-LMS), discretewavelet transform LMS (DWT-LMS) and recursive-least-squares (RLS) algorithms under same conditions.
Optimum capacity allocation of distributed generation units using parallel ps...eSAT Journals
Abstract This paper proposes the application of Parallel Particle Swarm Optimization (PPSO) technique to find the optimal sizing of multiple DG(Distributed Generation) units in the radial distribution network by reduction in real power losses and enhancement in voltage profile. Message passing interface (MPI) is used for the parallelization of PSO. The initial population of PSO algorithm has been divided between the processors at run time. The proposed technique is tested on standard 123-bus test system and the obtained results show that the simulation time is significantly reduced and is concluded that parallelization helps in enhancing the performance of basic PSO. The procedure has been implemented in an environment in which OpenDSS (Open Distribution System Simulator) is driven from MATLAB. An adaptive weight particle swarm optimization algorithm has been developed in MATLAB , parallelization is achieved using MATLABMPI and the unbalanced three-phase distribution load flow (DLF) has been performed using Electric Power Research Institute’s (EPRI) open source tool OpenDSS. Index Terms: Distributed Generation, Message Passing Interface, Optimal Placement, Parallel Particle Swarm Optimisation
OPTIMIZED TASK ALLOCATION IN SENSOR NETWORKSZac Darcy
The document proposes an approach to optimize energy consumption in sensor networks. It allocates tasks to sensor nodes using a particle swarm optimization algorithm that considers energy for data communication between nodes. Simulation results show the proposed approach reduces energy consumption and increases network lifetime compared to existing approaches that only allocate tasks to cluster gateways. The key aspects of the proposed approach are using a cost function that includes communication energy in the task allocation algorithm and having nodes send combined data from neighboring nodes to reduce the number of messages.
Mathematical Modelling and Parameter Optimization of Pulsating Heat PipesXin-She Yang
This document presents a simplified mathematical model for pulsating heat pipes and uses parameter optimization to estimate key parameters from limited experimental data. The model considers the temperature evolution and mass transfer of vapor bubbles as well as the motion of liquid plugs using governing equations. Parameter estimation is framed as a nonlinear constrained optimization problem solved using the firefly algorithm to efficiently estimate parameters. The model is intended to reproduce key physics while obtaining good parameter estimates from sparse data.
A HYBRID CLUSTERING ALGORITHM FOR DATA MININGcscpconf
The document proposes a hybrid clustering algorithm that combines K-means and K-harmonic mean algorithms. It performs clustering by alternating between using harmonic mean and arithmetic mean to recalculate cluster centers after each iteration. Experimental results on five datasets show the hybrid algorithm produces clusters with lower mean values, indicating tighter grouping, compared to traditional K-means and K-harmonic mean algorithms. The hybrid approach overcomes issues with initialization sensitivity and helps improve computation time and clustering accuracy.
Fdtd calculation model for the transient analyses of grounding systemsHimmelstern
This document evaluates different parameters for calculating the transient impedance of grounding systems using the finite-difference time-domain (FDTD) method. It first adjusts the derivation of transient current to obtain more accurate impedance values. It then evaluates the FDTD calculation model to determine optimized parameters that accurately predict impedance without requiring huge computational resources. Specifically, it analyzes the effects of transient voltage integration path, reference electrode length and distance, injected current type and height. It finds that integrating the transient voltage parallel to the connecting line provides the most accurate impedance results without large computational needs.
LIDAR POINT CLOUD CLASSIFICATION USING EXPECTATION MAXIMIZATION ALGORITHMijnlc
EM algorithm is a common algorithm in data mining techniques. With the idea of using two iterations of E and M, the algorithm creates a model that can assign class labels to data points. In addition, EM not only optimizes the parameters of the model but also can predict device data during the iteration. Therefore, the paper focuses on researching and improving the EM algorithm to suit the LiDAR point cloud classification. Based on the idea of breaking point cloud and using the scheduling parameter for step E to help the algorithm converge faster with a shorter run time. The proposed algorithm is tested with measurement data set in Nghe An province, Vietnam for more than 92% accuracy and has faster runtime than the original EM algorithm.
The document summarizes research on using the Expectation Maximization (EM) algorithm for LiDAR point cloud classification. It discusses how the EM algorithm works and related work applying it for point cloud classification. The author proposes improvements to the basic EM algorithm by: 1) Splitting the point cloud vertically to reduce computation time, 2) Initializing model parameters, and 3) Using a scheduling parameter to speed convergence. The proposed algorithm is tested on a LiDAR dataset from Vietnam, achieving over 92% accuracy and faster runtime than the original EM algorithm.
A Counterexample to the Forward Recursion in Fuzzy Critical Path Analysis Und...ijfls
This document presents a counterexample demonstrating that the fuzzy forward recursion method for determining critical paths does not always produce results consistent with the extension principle when discrete fuzzy sets are used to represent activity durations.
The document first provides background on fuzzy sets and critical path analysis. It then presents a proposition stating that the membership function for fuzzy critical path lengths can be determined by taking the maximum of the minimum membership values across all activity durations in each configuration.
The document goes on to present a counterexample using a simple series-parallel network with 18 configurations. It shows that applying the fuzzy forward recursion produces a different membership value for one critical path length compared to directly applying the extension principle. This difference proves the fuzzy forward
Oscillatory Stability Prediction Using PSO Based Synchronizing and Damping To...journalBEEI
This paper presents the assessment of stability domains for the angle stability condition of the power system using Particle Swarm Optimization (PSO) technique. An efficient optimization method using PSO for synchronizing torque coefficients Ksand damping torque coefficients Kd to identify the angle stability condition on multi-machine system. In order to accelerate the determination of angle stability, PSO is proposed to be implemented in this study. The application of the proposed algorithm has been justified as the most accurate with lower computation time as compared to other optimization techniques such as Evolutionary Programming (EP) and Artificial Immune System (AIS). Validation with respect to eigenvalues determination, Least Square (LS) method and minimum damping ratio ξmin confirmed that the proposed technique is feasible to solve the angle stability problems.
This document discusses modelling errors introduced in the deterministic calculational path for analyzing a mini-core reactor problem. It presents the methodology used to quantify individual and combined effects of simplifications like energy group condensation, spatial homogenization, and the diffusion approximation. The results show that spectral, diffusion, and environmental errors are significant for a 6-group model of the mini-core problem, with combined errors over 4000 pcm. Equivalence theory resolved errors except for a remaining 733 pcm environmental error. Future work will further investigate environmental errors and apply these findings to improve reactor modelling calculations.
Power consumption is an important metric tool in the context of the wireless sensor networks
(WSNs). In this paper, we described a new Energy-Degree (EDD) Clustering Algorithm for the
WSNs. A node with higher residual energy and higher degree is more likely elected as a
clusterhead (CH). The intercluster and intracluster communications are realized on one hop.
The principal goal of our algorithm is to optimize the energy power and energy load among all
nodes. By comparing EDD clustering algorithm with LEACH algorithm, simulation results
have showen its effectiveness in saving energy.
Route Optimization to make Energy Efficient MANET using Vishal Fuzzy Genetic ...ijsrd.com
In any network QOS is one the basic requirement and when we talk about the MANET(mobile AD-HOC network) this is the highly constraint requirement of a user. To improve the quality of service we use different changes in MANET protocols, its parameter, routing algorithm etc. In this proposed work we are also improving the QOS by modifying the routing algorithm. The proposed routing algorithm is inspired from the genetic approach. The proposed algorithm will follow all the basic steps of routing algorithm in the sequence. As in initializing phase we will select the shortest path and one alternative aggregative path. The shortest path selection always returns the congestion over the network. Instead of using the shortest path we will select a genetic inspired path. In this work, the selection of the next cross over child path will be identified based on cyclic fuzzy logic. The whole process will optimize the routing algorithm to improve the QOS. In this work, the fuzzy-improved Genetic algorithm will be implemented on MATLAB 7.1 for the route generation.
IMAGE REGISTRATION USING ADVANCED TOPOLOGY PRESERVING RELAXATION LABELING csandit
This paper presents a relaxation labeling technique with newly defined compatibility measures
for solving a general non-rigid point matching problem. In the literature, there exists a point
matching method using relaxation labeling, however, the compatibility coefficients always take
a binary value zero or one depending on whether a point and a neighboring point have
corresponding points. Our approach generalizes this relaxation labeling approach. The
compatibility coefficients take n-discrete values which measures the correlation between edges.
We use log-polar diagram to compute correlations. Through simulations, we show that this
topology preserving relaxation method improves the matching performance significantly
compared to other state-of-the-art algorithms such as shape context, thin plate spline-robust
point matching, robust point matching by preserving local neighborhood structures and
coherent point drift.
The MSc defense ceremony was held on 6-7-2017 in Mansoura University, Faculty of Engineering. This presentation is shared to help MSc students in Faculty of Engineering prepare their thesis presentation and ease their tension before their presentation time
SOLVING OPTIMAL COMPONENTS ASSIGNMENT PROBLEM FOR A MULTISTATE NETWORK USING ...ijmnct
Optimal components assignment problem subject to system reliability, total lead-time, and total cost
constraints is studied in this paper. The problem is formulated as fuzzy linear problem using fuzzy
membership functions. An approach based on genetic algorithm with fuzzy optimization to sole the
presented problem. The optimal solution found by the proposed approach is characterized by maximum
reliability, minimum total cost and minimum total lead-time. The proposed approach is tested on different
examples taken from the literature to illustrate its efficiency in comparison with other previous methods
SOLVING OPTIMAL COMPONENTS ASSIGNMENT PROBLEM FOR A MULTISTATE NETWORK USING ...ijmnct
The document summarizes research on solving the optimal components assignment problem for a multistate network using fuzzy optimization. It discusses how the problem can be formulated as a fuzzy linear program by defining fuzzy membership functions for the objectives of maximizing reliability, minimizing total lead time, and minimizing total cost. The paper then proposes using a genetic algorithm combined with fuzzy linear programming to find component assignments that maximize the fuzzy objective membership degree.
Analysis of parallel algorithms for energy consumptionare you
This document analyzes the energy characteristics of parallel algorithms executed on multicore processors. It aims to (a) analyze energy usage of parallel algorithms, (b) study how energy is affected by parameters like computation vs communication power ratio, and (c) determine the optimal number of cores to minimize energy consumption. The methodology evaluates energy scalability under constant performance. It models computation, communication and idle energy usage to derive an expression for total energy. This expression is then analyzed to obtain the optimal number of cores as a function of input size and other parameters.
Multiobjective Firefly Algorithm for Continuous Optimization Xin-She Yang
This document describes a new algorithm called the Multiobjective Firefly Algorithm (MOFA) for solving multiobjective optimization problems. MOFA extends the existing Firefly Algorithm, which is based on the flashing behavior of fireflies, to handle problems with multiple objectives. The key steps of MOFA are: (1) Initialize a population of fireflies randomly in the search space, (2) Evaluate each firefly's approximation to the Pareto front, (3) Move fireflies towards brighter ones if they are dominated, (4) Generate new fireflies if constraints are violated, (5) Update the non-dominated solutions, (6) Randomly walk fireflies towards the best solution to sample the Pareto front. MO
EMBC'13 Poster Presentation on "A Bio-Inspired Cooperative Algorithm for Dist...Md Kafiul Islam
The document proposes an algorithm for distributed optimization with mobile nodes that do not know the cost function beforehand. Each node estimates the gradient vector to update its location. The proposed algorithm improves upon an existing algorithm by relying on information-rich nodes in the neighborhood instead of a linear combination of neighbors' estimates. It also uses a variable step size to increase the probability of finding information-rich nodes early in the iterations. Simulation results show the proposed algorithm achieves better performance than the existing algorithm and a non-cooperative scheme. The algorithm has applications in sensor networks, environmental monitoring, and other domains.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Here we describe the design details and performance of proposed Carry Propagate Adder based on GDI
technique. GDI technique is power efficient technique for designing digital circuit that consumes less
power as compare to most commonly used CMOS technique. GDI also has an advantage of minimum
propagation delay, minimum area required and less complexity for designing any digital circuit. We
designed Carry Propagate Adder using GDI technique and compared its performance with CMOS
technique in terms of area, delay and power dissipation. Circuit designed using CADENCE EDA tool and
simulated using SPECTRE VIRTUOSO tool at 0.18m technology. Comparative performance result shows
that Carry Propagate Adder using GDI technique dissipated 55.6% less power as compare to Carry
Propagate Adder using CMOS technique.
Accelerating system verilog uvm based vip to improve methodology for verifica...VLSICS Design
In this paper we present the development of Acceleratable UVCs from standard UVCs in System Verilog
and their usage in UVM based Verification Environment of Image Signal Processing designs to increase
run time performance. This paper covers development of Acceleratable UVCs from standard UVCs for
internal control and data buses of ST imaging group by partitioning of transaction-level components and
cycle-accurate signal-level components between the software simulator and hardware accelerator
respectively. Standard Co-Emulation API: Modeling Interface (SCE-MI) compliant, transaction-level
communications link between test benches running on a host system and Emulation machine is established.
Accelerated Verification IPs are used at UVM based Verification Environment of Image Signal Processing
designs both with simulator and emulator as UVM acceleration is an extension of the standard simulationonly
UVM and is fully backward compatible with it. Acceleratable UVCs significantly reduces development
schedule risks while leveraging transaction models used during simulation.
In this paper, we discuss our experiences on UVM based methodology adoption on TestBench-Xpress
(TBX) based technology step by step. We are also doing comparison between the run time performance
results from earlier simulator-only environment and the new, hardware-accelerated environment. Although
this paper focuses on Acceleratable UVC’s development and their usage for image signal processing
designs. Same concept can be extended for non-image signal processing designs.
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
This document summarizes a research paper on designing a low power encoder for a threshold inverter quantization (TIQ) based flash analog-to-digital converter (ADC). The paper proposes using a fat tree encoder and TIQ comparators to achieve high speed and low power consumption. A 3-bit ADC was designed and simulated in 45nm CMOS technology. Simulation results showed the ADC has low power of 185nw, high speed of 6.5ps delay, and better performance compared to other encoder designs. The fat tree encoder and TIQ comparators allow the ADC to operate at high speeds while consuming low power, making it suitable for applications requiring both.
Mathematical Modelling and Parameter Optimization of Pulsating Heat PipesXin-She Yang
This document presents a simplified mathematical model for pulsating heat pipes and uses parameter optimization to estimate key parameters from limited experimental data. The model considers the temperature evolution and mass transfer of vapor bubbles as well as the motion of liquid plugs using governing equations. Parameter estimation is framed as a nonlinear constrained optimization problem solved using the firefly algorithm to efficiently estimate parameters. The model is intended to reproduce key physics while obtaining good parameter estimates from sparse data.
A HYBRID CLUSTERING ALGORITHM FOR DATA MININGcscpconf
The document proposes a hybrid clustering algorithm that combines K-means and K-harmonic mean algorithms. It performs clustering by alternating between using harmonic mean and arithmetic mean to recalculate cluster centers after each iteration. Experimental results on five datasets show the hybrid algorithm produces clusters with lower mean values, indicating tighter grouping, compared to traditional K-means and K-harmonic mean algorithms. The hybrid approach overcomes issues with initialization sensitivity and helps improve computation time and clustering accuracy.
Fdtd calculation model for the transient analyses of grounding systemsHimmelstern
This document evaluates different parameters for calculating the transient impedance of grounding systems using the finite-difference time-domain (FDTD) method. It first adjusts the derivation of transient current to obtain more accurate impedance values. It then evaluates the FDTD calculation model to determine optimized parameters that accurately predict impedance without requiring huge computational resources. Specifically, it analyzes the effects of transient voltage integration path, reference electrode length and distance, injected current type and height. It finds that integrating the transient voltage parallel to the connecting line provides the most accurate impedance results without large computational needs.
LIDAR POINT CLOUD CLASSIFICATION USING EXPECTATION MAXIMIZATION ALGORITHMijnlc
EM algorithm is a common algorithm in data mining techniques. With the idea of using two iterations of E and M, the algorithm creates a model that can assign class labels to data points. In addition, EM not only optimizes the parameters of the model but also can predict device data during the iteration. Therefore, the paper focuses on researching and improving the EM algorithm to suit the LiDAR point cloud classification. Based on the idea of breaking point cloud and using the scheduling parameter for step E to help the algorithm converge faster with a shorter run time. The proposed algorithm is tested with measurement data set in Nghe An province, Vietnam for more than 92% accuracy and has faster runtime than the original EM algorithm.
The document summarizes research on using the Expectation Maximization (EM) algorithm for LiDAR point cloud classification. It discusses how the EM algorithm works and related work applying it for point cloud classification. The author proposes improvements to the basic EM algorithm by: 1) Splitting the point cloud vertically to reduce computation time, 2) Initializing model parameters, and 3) Using a scheduling parameter to speed convergence. The proposed algorithm is tested on a LiDAR dataset from Vietnam, achieving over 92% accuracy and faster runtime than the original EM algorithm.
A Counterexample to the Forward Recursion in Fuzzy Critical Path Analysis Und...ijfls
This document presents a counterexample demonstrating that the fuzzy forward recursion method for determining critical paths does not always produce results consistent with the extension principle when discrete fuzzy sets are used to represent activity durations.
The document first provides background on fuzzy sets and critical path analysis. It then presents a proposition stating that the membership function for fuzzy critical path lengths can be determined by taking the maximum of the minimum membership values across all activity durations in each configuration.
The document goes on to present a counterexample using a simple series-parallel network with 18 configurations. It shows that applying the fuzzy forward recursion produces a different membership value for one critical path length compared to directly applying the extension principle. This difference proves the fuzzy forward
Oscillatory Stability Prediction Using PSO Based Synchronizing and Damping To...journalBEEI
This paper presents the assessment of stability domains for the angle stability condition of the power system using Particle Swarm Optimization (PSO) technique. An efficient optimization method using PSO for synchronizing torque coefficients Ksand damping torque coefficients Kd to identify the angle stability condition on multi-machine system. In order to accelerate the determination of angle stability, PSO is proposed to be implemented in this study. The application of the proposed algorithm has been justified as the most accurate with lower computation time as compared to other optimization techniques such as Evolutionary Programming (EP) and Artificial Immune System (AIS). Validation with respect to eigenvalues determination, Least Square (LS) method and minimum damping ratio ξmin confirmed that the proposed technique is feasible to solve the angle stability problems.
This document discusses modelling errors introduced in the deterministic calculational path for analyzing a mini-core reactor problem. It presents the methodology used to quantify individual and combined effects of simplifications like energy group condensation, spatial homogenization, and the diffusion approximation. The results show that spectral, diffusion, and environmental errors are significant for a 6-group model of the mini-core problem, with combined errors over 4000 pcm. Equivalence theory resolved errors except for a remaining 733 pcm environmental error. Future work will further investigate environmental errors and apply these findings to improve reactor modelling calculations.
Power consumption is an important metric tool in the context of the wireless sensor networks
(WSNs). In this paper, we described a new Energy-Degree (EDD) Clustering Algorithm for the
WSNs. A node with higher residual energy and higher degree is more likely elected as a
clusterhead (CH). The intercluster and intracluster communications are realized on one hop.
The principal goal of our algorithm is to optimize the energy power and energy load among all
nodes. By comparing EDD clustering algorithm with LEACH algorithm, simulation results
have showen its effectiveness in saving energy.
Route Optimization to make Energy Efficient MANET using Vishal Fuzzy Genetic ...ijsrd.com
In any network QOS is one the basic requirement and when we talk about the MANET(mobile AD-HOC network) this is the highly constraint requirement of a user. To improve the quality of service we use different changes in MANET protocols, its parameter, routing algorithm etc. In this proposed work we are also improving the QOS by modifying the routing algorithm. The proposed routing algorithm is inspired from the genetic approach. The proposed algorithm will follow all the basic steps of routing algorithm in the sequence. As in initializing phase we will select the shortest path and one alternative aggregative path. The shortest path selection always returns the congestion over the network. Instead of using the shortest path we will select a genetic inspired path. In this work, the selection of the next cross over child path will be identified based on cyclic fuzzy logic. The whole process will optimize the routing algorithm to improve the QOS. In this work, the fuzzy-improved Genetic algorithm will be implemented on MATLAB 7.1 for the route generation.
IMAGE REGISTRATION USING ADVANCED TOPOLOGY PRESERVING RELAXATION LABELING csandit
This paper presents a relaxation labeling technique with newly defined compatibility measures
for solving a general non-rigid point matching problem. In the literature, there exists a point
matching method using relaxation labeling, however, the compatibility coefficients always take
a binary value zero or one depending on whether a point and a neighboring point have
corresponding points. Our approach generalizes this relaxation labeling approach. The
compatibility coefficients take n-discrete values which measures the correlation between edges.
We use log-polar diagram to compute correlations. Through simulations, we show that this
topology preserving relaxation method improves the matching performance significantly
compared to other state-of-the-art algorithms such as shape context, thin plate spline-robust
point matching, robust point matching by preserving local neighborhood structures and
coherent point drift.
The MSc defense ceremony was held on 6-7-2017 in Mansoura University, Faculty of Engineering. This presentation is shared to help MSc students in Faculty of Engineering prepare their thesis presentation and ease their tension before their presentation time
SOLVING OPTIMAL COMPONENTS ASSIGNMENT PROBLEM FOR A MULTISTATE NETWORK USING ...ijmnct
Optimal components assignment problem subject to system reliability, total lead-time, and total cost
constraints is studied in this paper. The problem is formulated as fuzzy linear problem using fuzzy
membership functions. An approach based on genetic algorithm with fuzzy optimization to sole the
presented problem. The optimal solution found by the proposed approach is characterized by maximum
reliability, minimum total cost and minimum total lead-time. The proposed approach is tested on different
examples taken from the literature to illustrate its efficiency in comparison with other previous methods
SOLVING OPTIMAL COMPONENTS ASSIGNMENT PROBLEM FOR A MULTISTATE NETWORK USING ...ijmnct
The document summarizes research on solving the optimal components assignment problem for a multistate network using fuzzy optimization. It discusses how the problem can be formulated as a fuzzy linear program by defining fuzzy membership functions for the objectives of maximizing reliability, minimizing total lead time, and minimizing total cost. The paper then proposes using a genetic algorithm combined with fuzzy linear programming to find component assignments that maximize the fuzzy objective membership degree.
Analysis of parallel algorithms for energy consumptionare you
This document analyzes the energy characteristics of parallel algorithms executed on multicore processors. It aims to (a) analyze energy usage of parallel algorithms, (b) study how energy is affected by parameters like computation vs communication power ratio, and (c) determine the optimal number of cores to minimize energy consumption. The methodology evaluates energy scalability under constant performance. It models computation, communication and idle energy usage to derive an expression for total energy. This expression is then analyzed to obtain the optimal number of cores as a function of input size and other parameters.
Multiobjective Firefly Algorithm for Continuous Optimization Xin-She Yang
This document describes a new algorithm called the Multiobjective Firefly Algorithm (MOFA) for solving multiobjective optimization problems. MOFA extends the existing Firefly Algorithm, which is based on the flashing behavior of fireflies, to handle problems with multiple objectives. The key steps of MOFA are: (1) Initialize a population of fireflies randomly in the search space, (2) Evaluate each firefly's approximation to the Pareto front, (3) Move fireflies towards brighter ones if they are dominated, (4) Generate new fireflies if constraints are violated, (5) Update the non-dominated solutions, (6) Randomly walk fireflies towards the best solution to sample the Pareto front. MO
EMBC'13 Poster Presentation on "A Bio-Inspired Cooperative Algorithm for Dist...Md Kafiul Islam
The document proposes an algorithm for distributed optimization with mobile nodes that do not know the cost function beforehand. Each node estimates the gradient vector to update its location. The proposed algorithm improves upon an existing algorithm by relying on information-rich nodes in the neighborhood instead of a linear combination of neighbors' estimates. It also uses a variable step size to increase the probability of finding information-rich nodes early in the iterations. Simulation results show the proposed algorithm achieves better performance than the existing algorithm and a non-cooperative scheme. The algorithm has applications in sensor networks, environmental monitoring, and other domains.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Here we describe the design details and performance of proposed Carry Propagate Adder based on GDI
technique. GDI technique is power efficient technique for designing digital circuit that consumes less
power as compare to most commonly used CMOS technique. GDI also has an advantage of minimum
propagation delay, minimum area required and less complexity for designing any digital circuit. We
designed Carry Propagate Adder using GDI technique and compared its performance with CMOS
technique in terms of area, delay and power dissipation. Circuit designed using CADENCE EDA tool and
simulated using SPECTRE VIRTUOSO tool at 0.18m technology. Comparative performance result shows
that Carry Propagate Adder using GDI technique dissipated 55.6% less power as compare to Carry
Propagate Adder using CMOS technique.
Accelerating system verilog uvm based vip to improve methodology for verifica...VLSICS Design
In this paper we present the development of Acceleratable UVCs from standard UVCs in System Verilog
and their usage in UVM based Verification Environment of Image Signal Processing designs to increase
run time performance. This paper covers development of Acceleratable UVCs from standard UVCs for
internal control and data buses of ST imaging group by partitioning of transaction-level components and
cycle-accurate signal-level components between the software simulator and hardware accelerator
respectively. Standard Co-Emulation API: Modeling Interface (SCE-MI) compliant, transaction-level
communications link between test benches running on a host system and Emulation machine is established.
Accelerated Verification IPs are used at UVM based Verification Environment of Image Signal Processing
designs both with simulator and emulator as UVM acceleration is an extension of the standard simulationonly
UVM and is fully backward compatible with it. Acceleratable UVCs significantly reduces development
schedule risks while leveraging transaction models used during simulation.
In this paper, we discuss our experiences on UVM based methodology adoption on TestBench-Xpress
(TBX) based technology step by step. We are also doing comparison between the run time performance
results from earlier simulator-only environment and the new, hardware-accelerated environment. Although
this paper focuses on Acceleratable UVC’s development and their usage for image signal processing
designs. Same concept can be extended for non-image signal processing designs.
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of
VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of
retrieving input logic from an output logic because of bijective mapping between input and output. In this
manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of
the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage
outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative
study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from
full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS
transistor with less number of MOS transistor count.
This document summarizes a research paper on designing a low power encoder for a threshold inverter quantization (TIQ) based flash analog-to-digital converter (ADC). The paper proposes using a fat tree encoder and TIQ comparators to achieve high speed and low power consumption. A 3-bit ADC was designed and simulated in 45nm CMOS technology. Simulation results showed the ADC has low power of 185nw, high speed of 6.5ps delay, and better performance compared to other encoder designs. The fat tree encoder and TIQ comparators allow the ADC to operate at high speeds while consuming low power, making it suitable for applications requiring both.
Advanced atpg based on fan, testability measures and fault reductionVLSICS Design
A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a
circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI
circuit has become a major constrain in a battery operated device for technology node below 90nm, as it
drains the battery even when a circuit is in standby mode. Major concern is the leakage even in run time
condition, here aim is to focus on run time leakage reduction technique of integrated Circuit. It is inherited
by stacking effect when the series transistors are maximized in OFF state condition. This method is
independent of process technology and does not require any additional power supply. This paper gives an
optimized solution of input pattern determination of some small circuit to find minimum leakage vector
considering promising and non-promising node which helps to reduce the time complexity of the algorithm.
Proposed algorithm is simulated using HSPICE simulator for 2 input NAND gate and different standard
logic cells and achieved 94.2% and 54.59 % average leakage power reduction for 2 input NAND cell and
different logics respectively.
Crdom cell re ordering based domino on-the-fly mappingVLSICS Design
This Domino logic is often the choice for designing high speed CMOS circuits. Often VLSI designers
choose library based approaches to perform technology mapping of large scale circuits involving static
CMOS logic style. Cells designed using Domino logic style have the flexibility to accommodate wide range
of functions in them. Hence, there is a scope to adopt a library free synthesis approach for circuits
designed using Domino logic. In this work, we present an approach for mapping a domino logic circuit
using an On-the-fly technique. First, we present a node mapping algorithm which maps a given Domino
logic netlist using On-the-fly technique. Next, using an Equivalence Table, we re-order the cells along the
critical path for delay, area benefit. Finally, we find an optimum re-ordering set which can obtain
maximum delay savings for a minimum area penalty. We have tested the efficacy of our approach with a
set of standard benchmark circuits. Our proposed mapping approach (CRDOM) obtained 21%
improvement in area and 17% improvement in delay compared to existing work.
ENHANCING MULTIPLIER SPEED IN FAST FOURIER TRANSFORM BASED ON VEDIC MATHEMATICSVLSICS Design
Vedic mathematics is an ancient system of mathematics which has a unique technique of calculations based
on 16 sutras. The performance of high speed multiplier is designed based on Urdhva Tiryabhyam, Nikhilam
Navatashcaramam Dashatah, and Anurupye Vedic mathematical algorithms. These algorithms gives
minimum delay and used for multiplication of all types of numbers. The performance of high speed multiplier
is designed and compared using these sutras for various NxN bit multiplications and implemented on the
FFT of the DSP processor. Anurupye sutra on FFT is made efficient than Urdhva tiryabhyam and Nikhilam
Navatashcaramam Dashatah sutras by more reduction in computation time. This gives the method for
hierarchical multiplier design. Logic verification of these designs is verified by simulating the logic circuits
in XILINX ISE 9.1 and MODELSIM SE 5.7g using VHDL coding.
ESTABLISHING A MOLECULAR COMMUNICATION CHANNEL FOR NANO NETWORKSVLSICS Design
This document summarizes research on establishing molecular communication channels for nano networks. Molecular communication provides a practical way for nano machines to communicate by using encoded molecules as information carriers. Researchers have modeled molecular propagation using Brownian motion and Fick's laws of diffusion. Channel characterization involves estimating parameters like channel capacity, gain, and delay. Simulations show molecular channels exhibit properties like linearity and time-invariance. Open issues remain around negative molecular drift, synchronization, and inter-symbol interference mitigation. Higher network layer functions for molecular communication also require further investigation.
Nowadays exponential advancement in reversible comp
utation has lead to better fabrication and
integration process. It has become very popular ove
r the last few years since reversible logic circuit
s
dramatically reduce energy loss. It consumes less p
ower by recovering bit loss from its unique input-o
utput
mapping. This paper presents two new gates called
RC-I and RC-II to design an n-bit signed binary
comparator where simulation results show that the p
roposed circuit works correctly and gives significa
ntly
better performance than the existing counterparts.
An algorithm has been presented in this paper for
constructing an optimized reversible n-bit signed c
omparator circuit. Moreover some lower bounds have
been proposed on the quantum cost, the numbers of g
ates used and the number of garbage outputs
generated for designing a low cost reversible sign
ed comparator. The comparative study shows that the
proposed design exhibits superior performance consi
dering all the efficiency parameters of reversible
logic
design which includes number of gates used, quantum
cost, garbage output and constant inputs. This
proposed design has certainly outperformed all the
other existing approaches.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
Design of 6 bit flash analog to digital converter using variable switching vo...VLSICS Design
This paper presents the design of 6-bit flash analog to digital Converter (ADC) using the new variable
switching voltage (VSV) comparator. In general, Flash ADCs attain the highest conversion speed at the
cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits
significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation
result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of
1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral
nonlinearities (DNL and INL) of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.
Low power reduced instruction set architecture using clock gating techniqueVLSICS Design
The document describes a low power reduced instruction set architecture (RISA) using a clock gating technique. The proposed RISA uses clock gating to reduce power consumption by disabling the clock signals to unused modules. The architecture includes a RISC processor, interrupt controller, port controller, program flow controller, transmitter and receiver modules. An interrupt controller handles interrupts from multiple sources and prioritizes them. Separate transmitter and receiver modules allow for serial communication. The architecture was implemented on an FPGA using VerilogHDL and clock gating was applied to reduce power in key modules like the ALU, interrupt controller, transmitter and receiver.
Optimization of Cmos 0.18 µM Low Noise Amplifier Using Nsga-Ii for UWB Applic...VLSICS Design
A design and optimization of 3-5 GHz single ended Radio Frequency (RF) Low Noise Amplifier (LNA) for
ultra-wide-band (UWB) applications using standard UMC 0.18 μm CMOS technology is reported.
Designing of RF circuit components is a challenging job, since even after performing lengthy calculations
and finding parameter values it is less guarantee that the design performs as expected. In view of this the
optimization tool; Elitist Non-Dominated Sorting Genetic Algorithm (NSGA-II); has been employed to get
the optimized starting values of components in the proposed LNA design. The obtained NSGA-II
parameters were simulated using Cadence Spectre- RF simulator. The designed Low Noise Amplifier
achieves a power gain of 22 dB and a minimum Noise Figure of 3 dB is achieved. It dissipates 12.5 mW of
power out of 1.8 V supply.
Analytical modeling of electric field distribution in dual material junctionl...VLSICS Design
In this paper, electric field distribution of the junctionless dual material surrounding gate MOSFETs
(JLDMSG) is developed. Junctionless is a device that has similar characteristics like junction based
devices, but junctionless has a positive flatband voltage with zero electric field. In Surrounding gate
MOSFETs gate material surrounds the channel in all direction , therefore it can overcome the short
channel effects effectively than other devices. In this paper, surface potential and electric field distribution
is modelled. The proposed surface potential model is compared with the existing central potential model. It
is observed that the short channel effects (SCE) is reduced and the performance is better than the existing
method.
DESIGN OF HIGH EFFICIENCY TWO STAGE POWER AMPLIFIER IN 0.13UM RF CMOS TECHNOL...VLSICS Design
This two-stage power amplifier was designed in 0.13um RF CMOS technology for 2.4GHz WLAN applications. It consists of a driver stage using a cascode topology and a power stage using a basic topology. At 1dB compression, it delivers 20.028dBm of output power with 44.669% power added efficiency. Maximum output power is 22.002dBm with 70.196% efficiency. Input and output return losses are -11.132dB and -12.467dB respectively, with a gain of 43.745dB at 1dB compression.
Dynamic task scheduling on multicore automotive ec usVLSICS Design
Automobile manufacturers are controlled by stringent govt. regulations for safety and fuel emissions and
motivated towards adding more advanced features and sophisticated applications to the existing electronic
system. Ever increasing customer’s demands for high level of comfort also necessitate providing even more
sophistication in vehicle electronics system. All these, directly make the vehicle software system more
complex and computationally more intensive. In turn, this demands very high computational capability of
the microprocessor used in electronic control unit (ECU). In this regard, multicore processors have
already been implemented in some of the task rigorous ECUs like, power train, image processing and
infotainment. To achieve greater performance from these multicore processors, parallelized ECU software
needs to be efficiently scheduled by the underlaying operating system for execution to utilize all the
computational cores to the maximum extent possible and meet the real time constraint. In this paper, we
propose a dynamic task scheduler for multicore engine control ECU that provides maximum CPU
utilization, minimized preemption overhead, minimum average waiting time and all the tasks meet their
real time deadlines while compared to the static priority scheduling suggested by Automotive Open Systems
Architecture (AUTOSAR).
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Techn...VLSICS Design
Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very
Large Scale Integration) technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area
,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic
Circuits) are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs
have been proposed over last few years with different logic styles. To reduce the power consumption
several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets,
charge sharing by parasitic components while connecting source and drain of CMOS transistors There are
situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset
themselves) after some prescribed delays. These circuits are hence called postcharge or self-resetting logic
which are widely used in dynamic logic circuits. Overall performance of various adder designs is
evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using
Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V.
On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low
PDP among its counterparts.
Analysis of pocket double gate tunnel fet for low stand by power logic circuitsVLSICS Design
This document analyzes and compares the pocket double gate tunnel FET (DGTFET) and MOSFET for use in low standby power logic circuits. Simulation results show that the pocket DGTFET has lower leakage current than the MOSFET. A pocket DGTFET inverter is designed in 32nm technology with a supply voltage of 0.6V. The pocket DGTFET inverter has significantly lower leakage power of 0.116pW compared to 1.83pW for a multi-threshold CMOS inverter. Therefore, the pocket DGTFET is well-suited to replace the MOSFET for low standby power applications.
Investigation of Ant Colony Optimization Algorithm for Efficient Energy Utili...IJCNCJournal
Maintaining the energy conservation is considered as an important approach to increase the lifetime of WSN. In fact, an energy reduction mechanism is considered as the main concept to enhance the lifespan of the network. In this paper, the performance analysis/evaluation of optimization technique, specifically, Ant Colony Optimization (ACO) and modified ACO (m-ACO) in the routing method are investigated. This network analysis is done by 100 iterations and differentiated with 50, 75 and 100 numbers of nodes. Finally, experimental results illustrate that the performance of m-ACO algorithm obtained the obvious performance, which is comparatively better than ACO algorithm, because it improves the routing efficiency by pheromone evaporation control and energy threshold value. It demonstrates that m-ACO algorithm gives better results than ACO in terms of throughput (1.41%), transmission delay (1.43%), packet delivery ratio (1.41%), energy consumption (2.05%), and the packet loss (9.70%). The convergence rate is analysed for ACO and m-ACO algorithms with respect to 100 number of iterations for WSNs.
Investigation of Ant Colony Optimization Algorithm for Efficient Energy Utili...IJCNCJournal
Maintaining the energy conservation is considered as an important approach to increase the lifetime of WSN. In fact, an energy reduction mechanism is considered asthe main concept to enhance the lifespan of the network. In this paper, the performance analysis/evaluation of optimization technique, specifically, Ant Colony Optimization (ACO) and modified ACO (m-ACO) in the routing method are investigated. This network analysis is done by 100 iterations and differentiated with 50, 75 and 100 numbers of nodes. Finally, experimental results illustrate that the performance of m-ACO algorithm obtained the obvious performance,which is comparatively better than ACO algorithm, because it improves the routing efficiency by pheromone evaporation control and energy threshold value. It demonstrates that m-ACO algorithm gives better results than ACO in terms of throughput (1.41%), transmission delay (1.43%), packet delivery ratio (1.41%), energy consumption (2.05%), and the packet loss (9.70%). The convergence rate is analysed for ACO and m-ACO algorithms with respect to 100 number of iterations for WSNs.
This document describes a method for maximizing the total throughput of a two-way relay network using orthogonal frequency-division multiplexing (OFDM). The method jointly optimizes subcarrier pairing and relay selection by formulating the problem as a maximum weighted bipartite matching problem, which can be solved in polynomial time. Simulation results show that the proposed method increases total throughput compared to benchmark methods, especially as the number of relays increases. The throughput is evaluated for different numbers of subcarriers and relays to analyze the system's performance under various conditions.
Optimum Network Reconfiguration using Grey Wolf OptimizerTELKOMNIKA JOURNAL
Distribution system Reconfiguration is the process of changing the topology of the distribution
network by opening and closing switches to satisfy a specific objective. It is a complex, combinatorial
optimization problem involving a nonlinear objective function and constraints. Grey Wolf Optimizer (GWO)
is a recently developed metaheuristic search algorithm inspired by the leadership hierarchy and hunting
strategy of grey wolves in nature. The objective of this paper is to determine an optimal network
reconfiguration that presents the minimum power losses, considering network constraints, and using GWO
algorithm. The proposed algorithm was tested using some standard networks (33 bus, 69 bus, 84 bus and
118 bus), and the obtained results reveal the efficiency and effectiveness of the proposed approach.
Ieee transactions 2018 topics on wireless communications for final year stude...tsysglobalsolutions
This document contains summaries of several academic papers related to wireless communications and signal processing. The summaries are 3 sentences or less and provide the high level purpose and key findings of each paper. The papers cover topics like content placement in cache-enabled small cell networks, joint beamformer design for wireless fronthaul and access links, long-term power procurement scheduling for smart grids, and frequency-domain compressive channel estimation for hybrid mmWave MIMO systems among others.
Optimal placement of distributed power flow controller for loss reduction usi...eSAT Journals
Abstract
The aim of this paper is to reduce power loss and improve the voltage profiles in an electrical system in optimal manner. The flexible AC transmission system (FACTS) device such as Distributed power flow controller (DPFC) can strongly improve the different parameters in a power system. DPFC can be used to reduce line losses and increase voltage profiles. The optimized allocation of FACTS devices is an important issue, so the Voltage stability index (L-index) has been used in order to place UPFC in power system. The advantage of the L-index is to accelerate the optimization process. After placing the DPFC, Firefly optimization method is used for finding the rating of DPFC. The results obtained using Firefly optimization method is compared with Genetic Algorithm. To show the validity of the proposed techniques and for comparison purposes, simulation carried out on an IEEE- 14 Bus and IEEE- 30 Bus test system for different loading conditions.
Keywords: Distributed power flow controllers (DPFC), Optimized Placement, Voltage stability index (L-index), Firefly optimization method, Genetic algorithm.
Spatial correlation based clustering algorithm for random and uniform topolog...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
This document presents a two-stage approach for optimal capacitor placement in distribution systems to minimize losses using fuzzy logic and bat algorithm. In the first stage, fuzzy logic is used to determine optimal capacitor locations based on power loss index and voltage levels. In the second stage, the bat algorithm is used to determine the optimal capacitor sizes at the identified locations to minimize losses. The methodology is tested on 15-bus and 34-bus test systems and results are presented. Capacitor placement helps improve power factor, voltage profile, reduces power losses and increases feeder capacity of distribution systems.
Ieee transactions 2018 on wireless communications Title and Abstracttsysglobalsolutions
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Analysis of the Use of Universal Distribution Factors in SEC Power Gridresearchinventy
Distribution factors have been extensively used in many power system analysis and planning studies. In recent power system studies, the AC distribution factors are insensitive to the operating point and relatively sensitive at certain degree to changes in network topology. These factors are linear approximations of sensitivities of variables with various inputs. This paper presents the calculation of the universal distribution factors (UDF’s) applies them on several practical scenarios of Saudi Electricity Company (SEC) power grid. The results are analyzed and evaluated considering various system conditions of SEC load. The results show that the accuracy of the used approach is acceptable compared with exact method. This is practically beneficial to SEC in computing its grid complex power flows using UDF's at the base case without the need to recalculate UDF’s which save efforts and time.
Cluster head election using imperialist competitive algorithm (chei) for wire...ijmnct
One of the most important challenges of wireless sensor network is how to prolong its life time. The main
obstacle in these networks is the limited energy of nodes. We can overcome this problem by optimizing the
nodes' power consumption. The clustering mechanismis the one of the representative approachesto reduce
energy consumption, but optimum clustering of wireless sensor network is an NP-Hard problem. This
paper proposes a hybrid algorithm based on Imperialist competitive algorithm to overcome this clustering
problem. The proposed method, acts on one of the clusters in the network to choose the best sensor in
the cluster as a cluster head. To perform this action, the cluster is divided into several sub-clusters,
each of which has a cluster head. These cluster heads using Assimilation
policies, try to attract the regular nodes to themselves, and Using Imperialistic competition,
they compete with each other until one of these cluster heads is selected as the final cluster head. After this
stage, the algorithm work ends. This algorithm will balance the energy consumption in the network and
improve the network lifetime. To prove efficiency of proposed algorithm(CHEI), we simulated the proposed
algorithm compared with two clustering algorithms using the matlab
This document presents a proposed aging-aware reliable multiplier design with an adaptive hold logic (AHL) circuit. The multiplier uses a variable-latency technique and can adjust the AHL circuit to achieve reliable operation under negative bias temperature instability and positive bias temperature instability effects, which degrade transistor speed over time. The AHL circuit can determine if an input pattern requires one or two clock cycles to complete, and can adjust its judging criteria to minimize performance degradation from aging. Experimental results on 16x16 and 32x32 column-bypassing and row-bypassing multipliers show the proposed design achieves significant performance improvements compared to fixed-latency designs.
This document discusses using a learning automata approach to predict target locations in wireless sensor networks to reduce energy consumption and improve tracking accuracy. It proposes a learning automata based method that uses a target's movement history to predict its next location. Related works on target tracking techniques like tree-based, cluster-based, and prediction-based methods are summarized. Learning automata concepts are introduced. Simulation results are said to show the proposed method improves energy efficiency, reduces missed targets, and decreases transmitted packets compared to other methods.
Transmission Loss Allocation Based on Lines Current FlowIJAPEJOURNAL
In this paper, the transmission loss allocation problem has been studied and a new method for loss allocation in pool electricity markets has been proposed. To do that, at first using a transmission line loss equations respect to bus injected currents, the share of each bus from the mentioned transmission line losses has been determined. Then, this method has been applied to the total network transmission lines and the share of each bus from the total losses has been acquired. The proposed method is based on the main network relations and no any simplifying suppose has been used. Finally, the proposed method is studied on a typical network.
Distance based cluster head section in sensor networks for efficient energy u...IAEME Publication
The document describes a proposed distance-based cluster head selection algorithm for wireless sensor networks to improve energy efficiency. The key aspects of the proposed algorithm are:
1. It defines a threshold distance based on node transmission range to select cluster heads, avoiding nodes within this distance of the sink node or other cluster heads.
2. Cluster heads are selected in rounds based on this threshold distance to ensure even distribution across the network.
3. Simulation results show the proposed algorithm outperforms LEACH, reducing network energy usage and increasing network lifetime by up to 9% compared to LEACH.
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A New Transistor Sizing Approach for Digital Integrated Circuits Using Firefly Algorithm
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
DOI : 10.5121/vlsic.2015.6601 1
A NEW TRANSISTOR SIZING APPROACH FOR
DIGITAL INTEGRATED CIRCUITS USING
FIREFLY ALGORITHM
Nima Talebpour Anaraki1
, Mehdi Dolatshahi2*
and
Mohammad Hossein Nadimi Shahraki1
1
Faculty of Computer Engineering,
Najafabad Branch, Islamic Azad University, Najafabad, Iran
2*
Department of Electrical Engineering,
Najafabad Branch, Islamic Azad University, Najafabad, Iran
ABSTRACT
Due to the fact that, the power consumption and speed of a VLSI circuit are dependent on the transistor
sizes, efficient transistor sizing is a new challenge for VLSI circuit designers. However, evolutionary
computation can be successfully used for complex VLSI transistor sizing which reduces the time to market
and enables the designer to find the optimized solutions for a non-linear and complex circuit design
process. In this paper, a new digital integrated circuit design approach is proposed based on the firefly
artificial intelligence optimization algorithm. In order to justify the effectiveness of the proposed algorithm
in the design of VLSI circuits, an inverter (NOT gate) is designed and optimized by the proposed algorithm.
As the simulation results show, the inverter circuit has a very good performance for power and delay
parameters.
KEYWORDS
VLSI, firefly algorithm, transistor sizing, power, delay
1. INTRODUCTION
Due to the current rapid advances in the field of portable electronic systems such as: mobile
phones, laptop and tablets, the demand for low-power and battery-powered electronic devices is
increasing. However, the battery technology did not develop with the rate of microelectronic
technology; so, it is required to design low-power electronic circuits and systems. Although,
reducing the clock frequency of the system leads to a reduced power value, but, it also reduces
the computation speed which is one of the major challenges in the design of integrated circuits.
Furthermore, reducing the supply voltage causes a reduction in speed value [1]. So, the main
performance parameters such as: delay, power and chip area are in a trade-off with each other.
So, choosing a proper value for transistor dimensions (W, L) is the major step in the field of
integrated circuit design [2].
However, due to the complex design process of sub-micron integrated circuits, conventional
design approaches based on trial and error require a long design time, so, automatic design
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
2
algorithms which use optimization algorithms to find the best solutions for design variables
(transistor dimensions) are very demanding. However, the optimization constraints should
prevent the blind search, while, choosing the transistor dimensions should satisfy the feasibility
and fabrication considerations [3]. Furthermore, non-linearity issues are other major problem in
optimization based design algorithms [4], which can be solved by meta-heuristic algorithms that
try to simulate the social behaviour [5, 6]. In the meta-heuristic approaches the searchable area is
considered around the best candidates to solve the design problem. However, a meta-heuristic
optimization algorithm called as firefly optimization algorithm is introduced by Yang [7]. The
firefly optimization algorithm operates based on flashing characteristics of biological fireflies and
has been used more successfully than conventional optimization approaches such as: genetic
algorithm (GA), PSO [8, 9].
However, the firefly algorithm is successfully used in applications such as: wireless network
design [10], dynamic pricing [11] and mobile agents [12]. As it is discussed in the literature,
optimization algorithms such as: Genetic algorithm [13], PSO [3, 14], are successfully used in the
design of integrated circuits. As it is discussed in [13], GA is used to optimize the propagation
delay of a full adder circuit by selecting optimized values for transistor dimensions. Also, the
PSO algorithm is successfully used to optimize the delay of an inverter circuit [3, 14]. However,
in both approaches the performance measure of the circuit is formulated as a fitness function in
MATLAB and the theoretical values obtained from MATLAB are compared with the circuit
simulation results obtained from HSPICE which is a very complex and time consuming task and
may face convergence problems especially in sub-micron devices. But, the main idea in this
paper is to use directly the HSPICE simulation results in a loop of optimization in MATLAB,
where, the firefly optimization algorithm evaluates the fitness value and checks for the
termination condition of design algorithm by considering the design problem constraints which
leads to an improved accuracy and design time.
This paper is organized as follows: section 2, introduces the firefly optimization algorithm. In
section 3, the power and delay equations are presented. In section 4, the proposed design
algorithm is discussed in details and the simulation results are presented in section 5. Finally, the
conclusions are presented in section 6.
2. THE FIREFLY OPTIMIZATION ALGORITHM
To clarify the performance and operation of the optimization algorithm used in this paper, first
we study the behaviour and operation of the firefly optimization algorithm.
The fireflies attract mating partners and potential prey by flashing the light from themselves. The
rate, rhythm and the flashing reflection time causes to absorb the fireflies together. Furthermore,
different species of fireflies detect each other by imitating optical waves. Generally, fireflies have
the following specifications [15]:
• Relaxing from the gender of fireflies, they absorb together.
• Attractiveness is proportional to their brightness, thus, for any two flashing fireflies, the
less brighter one will move towards the brighter one. The attractiveness is proportional to
the brightness and they both decrease as their distance increases. If there is no brighter
one than a particular firefly, it will move randomly;
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
3
• The brightness of a firefly is affected or determined by the landscape of the objective
function.
The main characteristic of fireflies is the light intensity which is radiated from them and the
attraction of each firefly is evaluated using a fitness function in which the fitness value is the
value of brightness of each firefly [15].
However, in the simplest form, the light intensity I(r) varies according to the inverse square law:
ܫሺݎሻ =
ூೞ
మ (1)
Where, Is is the intensity at the source. For a given medium with a fixed light absorption
coefficient γ, the light intensity I varies with the distance r as follows:
ܫሺݎሻ = ܫ × ݁ିఊమ
(2)
As it is discussed above, the attractiveness of each firefly is proportional to the light intensity, so,
the value of each firefly's attractiveness (β) is obtained as follows:
ߚ = ߚ × ݁ିఊమ
(3)
The two dimensional (2D) distance between the two fireflies is calculated based on the eq.(4) and
the movement value for ith firefly to the jth firefly is obtained from eq.(5):
ݎ = ට൫ݔ − ݔ൯
ଶ
+ ൫ݕ − ݕ൯
ଶ
(4)
ݔ = ݔ + ߚ × ݁ିఊమ
൫ݔ − ݔ൯ + ܽߝ (5)
In eq.(5), x, is the initial and final position for ith firefly, while, β part in eq.(5) is the
attractiveness of each firefly. Furthermore, the parameter ε is used when no firefly is detected.
So, as it is obvious in the above equation, the next position of each firefly is defined based on the
attractiveness value of the target's firefly, while, for the cases that no target's firefly exists, the
firefly moves randomly [16].
However, the β0 parameter is usually considered as 1, due to the fact that, the attractiveness value
has the highest value at the origin point because each firefly has the highest light intensity
(attractiveness value) at it's location, while, the attractiveness value reduces when the distance
increases from the origin point [9].
As it is obvious in eq.(5), if β0=0, then there is no more attractive firefly in the region and the
firefly moves randomly. If, γ→0, then, β=β0 which means that there is no attenuation in light
intensity and the firefly's emitted light is detectable everywhere [17]. Also, when γ→∞ , all the
emitted light is absorbed which causes that the firefly moves randomly again. In theoretical point
of view, the γ value may vary between 0 to ∞, while, in practical conditions the γ parameter
varies between 0.1 to 10. The semi-code of the firefly algorithm is as follows:
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
4
Fig 1.The semi-code of firefly algorithm [9]
3. POWER-DELAY EQUATIONS AND DISCUSSION
As it is discussed above, there is an inherent conflict between power and delay parameters, but,
the delay parameter is proportional to the values of circuit's on-resistance (Ron) and capacitance
(C) [2]. Furthermore, the circuit's resistance is proportional to the inverse of transistor width (W),
so, the larger W leads to a smaller resistance as well as delay values.
Moreover, the power consumption is proportional to the value of circuit’s capacitance, so, the
larger capacitor causes the higher power consumption value. On the other hand, the capacitance
value of an integrated circuit is proportional to the value of the circuit area (W, L), so, increasing
the transistor width (W) leads to a higher circuit's capacitance and power consumption.
Giving the above facts, if the value of W is chosen based on a reasonable trade-off between the
power and delay parameters, it is possible to design an optimized low-power and high-speed
digital integrated circuit.
However, the power-delay product (PDP) parameter, which considers both power and speed of
the circuit is used as an effective performance parameter to show the inherent trade-off between
power and speed performances of a digital integrated circuit. As a result, minimizing the PDP
parameter guaranties the optimized values for both the power consumption and speed parameters
of the circuit.
However, as it is discussed in [2], the switching behaviour of the inverter can be generalized by
examining the parasitic capacitances and resistances associated with the inverter circuit which is
modelled in Fig. 2.
Although the model is shown with both switches open, in practice one of the switches is closed,
keeping the output connected to VDD or ground. The effective input capacitance of the inverter is
[2]:
ܥ =
ଷ
ଶ
ሺܥ௫ଵ + ܥ௫ଶሻ = ܥ + ܥ (6)
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
5
The effective output capacitance of the inverter is simply:
The intrinsic propagation delays of the inverter are:
In which the Ctot is the total capacitance seen at the output node which is as follows:
Where, the COX is:
The propagation delay of the circuit is as follows:
On the other hand, the average power is as follows:
So, the power-delay product (PDP) which is considered as the main optimization objective of this
paper is as follows:
Fig 2. The CMOS inverter switching characteristics using the digital model [2]
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
4. THE PROPOSED ALGORITHM
As it is mentioned before, the conventional equation
on manual calculations of transistor sizes, is a very time consuming and complex task which has
a large amount of errors between the theoretical results and th
simulations in HSPICE due to the non
transistor behaviour. So, the artificial intelligence based design methodologies are successfully
used for design and optimization of V
is considered for optimization and the design algorithm tries t
(power consumption or propagation delay) to find the best solutions for design variables (W, L).
However, there is always an error value between the theoretical results which are obtained from
design equations and simulation
due to the fact that, theoretical calculations do not consider the higher
in the transistor behaviour, while, circuit simulations consider such effects and use complex
transistor models. So, in this paper, as fig. 3 shows, a SPICE
circuit and the values for design performance measures such as: delay, power, PDP are calculated
in HSPICE and the simulation results are transferred to MATL
algorithm. In the proposed design algorithm, the firefly optimization algorithm varies the value of
W and the main circuit performance parameter which is PDP is evaluated by the circuit simulator
HSPICE and the process continues until the termination condition satisfied which is based on the
termination of the number generations or achieving a desired value of PDP parameter. Finally,
the minimum value of the PDP parameter as well as the corresponding transistor dimensions (
L) are obtained from the optimization algorithm.
Fig 3. Block diagram of proposed approach
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
LGORITHM
As it is mentioned before, the conventional equation-based design method of VLSI circuits, based
on manual calculations of transistor sizes, is a very time consuming and complex task which has
a large amount of errors between the theoretical results and the results obtained from circuit
simulations in HSPICE due to the non-linear and second-order effects which appear in the
transistor behaviour. So, the artificial intelligence based design methodologies are successfully
used for design and optimization of VLSI circuits [3, 13, 14]. In these methods a fitness function
is considered for optimization and the design algorithm tries to minimize the fitness function
(power consumption or propagation delay) to find the best solutions for design variables (W, L).
However, there is always an error value between the theoretical results which are obtained from
design equations and simulation values which are obtained from circuit simulations in HSPICE
due to the fact that, theoretical calculations do not consider the higher-order effects which appear
in the transistor behaviour, while, circuit simulations consider such effects and use complex
transistor models. So, in this paper, as fig. 3 shows, a SPICE-Netlist file is generated for each
circuit and the values for design performance measures such as: delay, power, PDP are calculated
in HSPICE and the simulation results are transferred to MATLAB to be optimized by the firefly
algorithm. In the proposed design algorithm, the firefly optimization algorithm varies the value of
W and the main circuit performance parameter which is PDP is evaluated by the circuit simulator
tinues until the termination condition satisfied which is based on the
termination of the number generations or achieving a desired value of PDP parameter. Finally,
the minimum value of the PDP parameter as well as the corresponding transistor dimensions (
L) are obtained from the optimization algorithm.
Fig 3. Block diagram of proposed approach
International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
6
based design method of VLSI circuits, based
on manual calculations of transistor sizes, is a very time consuming and complex task which has
e results obtained from circuit
order effects which appear in the
transistor behaviour. So, the artificial intelligence based design methodologies are successfully
. In these methods a fitness function
o minimize the fitness function
(power consumption or propagation delay) to find the best solutions for design variables (W, L).
However, there is always an error value between the theoretical results which are obtained from
values which are obtained from circuit simulations in HSPICE
order effects which appear
in the transistor behaviour, while, circuit simulations consider such effects and use complex
Netlist file is generated for each
circuit and the values for design performance measures such as: delay, power, PDP are calculated
AB to be optimized by the firefly
algorithm. In the proposed design algorithm, the firefly optimization algorithm varies the value of
W and the main circuit performance parameter which is PDP is evaluated by the circuit simulator
tinues until the termination condition satisfied which is based on the
termination of the number generations or achieving a desired value of PDP parameter. Finally,
the minimum value of the PDP parameter as well as the corresponding transistor dimensions (W,
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
7
5. SIMULATION RESULTS
The proposed design and optimization algorithm is implemented in MATLAB, while, the circuit
simulations are done in HSPICE for a CMOS inverter circuit shown in fig. 2, in 0.25µm
technology at 2.5v supply voltage. Furthermore, the number of generations is 100 while, the
population size is 50 and the range for selection the main design variable (W) is 0.25µm to 25µm.
Moreover, the firefly algorithm is initialized using the parameter values given in table. 1.
Table 1. Variables of firefly algorithm
ValueVariables
0.5(randomness) α
1.0(absorption) γ
0.2β
1β0
However, in order to justify the effectiveness of the proposed algorithm over other design
methods, the performance of the proposed algorithm is compared with the performance of the [3]
and [14] which use particle swarm optimization (PSO) based design and optimization algorithm.
Table 2, compares the simulation results which is obtained from simulations of firefly design
algorithm and those obtained from PSO design method.
As table 2 shows, Tphl and Tplh of the proposed algorithm is reduced significantly in comparison
with the value obtained from [3], due to the fact that, the value of load capacitor (Cload) is 73%
smaller than [3]. Also, in order to justify the effectiveness of the proposed algorithm, the Tphl of
the proposed algorithm is reduced considerable (≈62.7%) and the Tplh is reduced 8% in
comparison with the value obtained from [14] for the same Cload value. According to the
comparisons, the proposed algorithm has the best performance over previously reported design
methodologies.
Table 2. Simulation Results
[14][3]Proposed
Algorithm
110110040.95Tphl(ps)
100110091.17Tplh(ps)
0.311.120.3Cload(pf)
2.52.52.5VDD(v)
0.250.250.25Tech(um)
Finally, the MATLAB simulation result of the fitness function (PDP) is shown in fig. 4, which
shows the evolution and optimization of PDP parameter versus the number of generations.
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
Fig 4. PDP parameter performance for proposed algorithm
6. CONCLUSIONS
A CMOS inverter circuit is designed and optimized in this paper for the main purpose of
minimizing the power and delay of the circuit (PDP), using the firefly
0.25µm at 2.5v supply voltage. As it is discussed in the paper, to increase the design accuracy,
the circuit simulator (HSPICE) is directly used in the MATLAB which implements the firefly
optimization algorithm to find a verified
problem in a reduced design time and complexity.
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International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
Fig 4. PDP parameter performance for proposed algorithm
A CMOS inverter circuit is designed and optimized in this paper for the main purpose of
minimizing the power and delay of the circuit (PDP), using the firefly optimization algorithm in
0.25µm at 2.5v supply voltage. As it is discussed in the paper, to increase the design accuracy,
the circuit simulator (HSPICE) is directly used in the MATLAB which implements the firefly
optimization algorithm to find a verified and feasible solution with a good accuracy for the design
problem in a reduced design time and complexity.
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International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
8
A CMOS inverter circuit is designed and optimized in this paper for the main purpose of
optimization algorithm in
0.25µm at 2.5v supply voltage. As it is discussed in the paper, to increase the design accuracy,
the circuit simulator (HSPICE) is directly used in the MATLAB which implements the firefly
and feasible solution with a good accuracy for the design
power full-adder cell
R. J. Baker, CMOS: circuit design, layout, and simulation vol. 18: John Wiley & Sons, 2011.
R. A. Vural, O. Der, and T. Yildirim, "Particle swarm optimization based inverter design considering
A. Kaveh and S. Talatahari, "A novel heuristic optimization method: charged system search," Acta
inspired optimization algorithm,"
4845, 2012.
ms for multimodal optimization," in Stochastic algorithms: foundations
S. Yang, and A. H. Alavi, "Mixed variable structural optimization using firefly
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.6, No.6, December 2015
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